Chapter 5 Interconnect RLC Model n Efficient capacitance model Efficient inductance model Efficient...
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Chapter 5 Interconnect RLC Model
Efficient capacitance modelEfficient capacitance model
Efficient inductance modelEfficient inductance model
RC and RLC circuit model generationRC and RLC circuit model generation
Numeric based interconnect modelingNumeric based interconnect modeling
Is RC Model still Sufficient?
Interconnect impedance is more than resistanceInterconnect impedance is more than resistance Z Z R +j R +jLL 1/t1/trr
On-chip inductance should be considered On-chip inductance should be considered When When L becomes comparable to R as we move L becomes comparable to R as we move
towards Ghz+ designstowards Ghz+ designs
Candidates for On-Chip Inductance
Wide clock treesWide clock trees Skews are different under RLC and RC modelsSkews are different under RLC and RC models Neighboring signals are disturbed due to large clock Neighboring signals are disturbed due to large clock di/dt di/dt
noisenoise
Fast edge rate (~100ps) busesFast edge rate (~100ps) buses RC model RC model under-estimatesunder-estimates crosstalk crosstalk
P/G grids (and C4 bumps)P/G grids (and C4 bumps) di/dtdi/dt noise might overweight IR drop noise might overweight IR drop
Resistance vs Inductance
0
20
40
60
80
100
120
140
160
180
200
1.00E+08 1.00E+09 1.00E+10 1.00E+11
frequency (100M-100G)
Rea
ctan
ce R
wL
2.50E-09
2.60E-09
2.70E-09
2.80E-09
2.90E-09
3.00E-09
3.10E-09
3.20E-09
1.00E+08 1.00E+10 1.00E+12 1.00E+14
frequency (100M-100T)Hz
Indu
ctan
ce(H
)
Self
mutual
R and R and L for a single wireL for a single wire Ls and Lx for two parallel wiresLs and Lx for two parallel wires
Length = 2000, Width = 0.8 Length = 2000, Width = 0.8
Thickness = 2.0, Space = 0.8Thickness = 2.0, Space = 0.8
Impact of InductanceImpact of Inductance
GndGnd GndGndClkClk
RLC modelRLC modelRC modelRC model
6000
u
6000
u
10u10u5u5u 5u5u
Inductance Extraction from Geometries
Numerical method based on Maxwell’s equations Accurate, but way too slow for iterative physical design
and verification
Efficient yet accurate models Coplanar bus structure [He-Chang-Shen-et al, CICC’99]
Strip-lines and micro-strip bus lines [Chang-Shen-He-et al, DATE’2K]
Used in HP for state-of-the-art CPU design
Definition of Loop Inductance
The loop inductance isThe loop inductance is
ViVj
Ii Ij
jiji
loop a ijloop ajijiij dadadIdI
rIIaaL
j ji i
111
4
Loop Inductance for N TracesTw Tw Tw
Ts Ts
TwL TwR
TsL TsR
Assume edge traces are AC-groundedAssume edge traces are AC-grounded leads to 3x3 loop inductance matrixleads to 3x3 loop inductance matrix
Inductance has a long range effectInductance has a long range effect non-negligible coupling between tnon-negligible coupling between t11 and t and t3, 3, even with t even with t22
between thembetween them
1.73 1.15 0.531.15 1.94 1.240.53 1.24 1.92tL t1 t2 t3 tR
It is not sufficient to consider only a single net, It is not sufficient to consider only a single net, as did by most interconnect modeling and as did by most interconnect modeling and optimization worksoptimization works
Table in Brute-Force Way is Expensive
Self inductance has nine dimensions:Self inductance has nine dimensions: (n, length, location,Tw(n, length, location,TwLL,Ts,TsLL,Tw,Ts,Tw,Tw,Ts,TwRR,Ts,TsRR))
Mutual inductance has ten dimensions:Mutual inductance has ten dimensions: (n, length, location1, location2,Tw(n, length, location1, location2,TwLL,Ts,TsLL,Tw,Ts,Tw,Tw,Ts,TwRR,Ts,TsRR))
Length is needed because inductance is not linearly Length is needed because inductance is not linearly scalablescalable
Tw Tw Tw
Ts Ts
TwL TwR
TsL TsR
1.73 1.15 0.531.15 1.94 1.240.53 1.24 1.92tL t1 t2 t3 tR
Definition of Partial Inductance
Partial inductance is the portion of loop inductance for Partial inductance is the portion of loop inductance for a segment when its current returns via the infinitya segment when its current returns via the infinity called partial element equivalent circuit (PEEC) modelcalled partial element equivalent circuit (PEEC) model
If current is uniform (no skin effect), the partial If current is uniform (no skin effect), the partial inductance isinductance is
ViVj
il
ib
ic
jb
jc
lj
i
i i
j
j j
c
b a
c
b a
jiij
ji
jiij dada
r
dldl
aaL
1
4
Partial Inductance for N Traces
6.17 5.43 5.12 4.89 4.665.43 6.79 6.10 5.48 5.045.12 6.10 6.79 6.10 5.334.89 5.48 6.10 6.79 5.774.66 5.04 5.33 5.77 6.50
Treat edge traces same as inner tracesTreat edge traces same as inner traces lead to 5x5 partial inductance tablelead to 5x5 partial inductance table
Partial inductance model is more accurate Partial inductance model is more accurate compared to loop inductance modelcompared to loop inductance model Without pre-setting current return loopWithout pre-setting current return loop
Tw Tw Tw
Ts Ts
TwL TwR
TsL TsRtL t1 t2 t3 tR
Foundation I
The self inductance under the PEEC model The self inductance under the PEEC model for a trace depends only on the trace itself for a trace depends only on the trace itself (w/ skin effect for a given frequency).(w/ skin effect for a given frequency).
Tw Tw Tw
Ts Ts
TwL TwR
TsL TsRtL t1 t2 t3 tR
6.17 5.43 5.12 4.89 4.665.43 6.79 6.10 5.48 5.045.12 6.10 6.79 6.10 5.334.89 5.48 6.10 6.79 5.774.66 5.04 5.33 5.77 6.50
6.50
Foundation II The mutual inductance under the PEEC model for The mutual inductance under the PEEC model for
two traces depends only on the traces themselves two traces depends only on the traces themselves (w/ skin effect for given frequency).(w/ skin effect for given frequency).
Tw Tw Tw
Ts Ts
TwL TwR
TsL TsRtL t1 t2 t3 tR
6.17 5.43 5.12 4.89 4.665.43 6.79 6.10 5.48 5.045.12 6.10 6.79 6.10 5.334.89 5.48 6.10 6.79 5.774.66 5.04 5.33 5.77 6.50
4.666.50
6.174.66
Foundation III
The self loop inductance for a trace on top The self loop inductance for a trace on top of a ground plane depends only on the trace of a ground plane depends only on the trace itself (its length, width, and thickness)itself (its length, width, and thickness)
4.8 2.5 1.3 0.7 0.142.5 5.5 2.9 1.5 0.71.3 2.9 5.7 2.9 1.30.7 1.5 2.9 2.5 2.50.14 0.7 1.3 2.5 4.8
Tw Tw Tw
Ts Ts
TwL TwR
TsL TsRtL t1 t2 t3 tR
4.8
tR
Foundation IV
The mutual loop inductance for two traces on The mutual loop inductance for two traces on top of a ground plane depends only on the two top of a ground plane depends only on the two traces themselves traces themselves (their lengths, widths, and thickness)(their lengths, widths, and thickness)
4.8 2.5 1.3 0.7 0.142.5 5.5 2.9 1.5 0.71.3 2.9 5.7 2.9 1.30.7 1.5 2.9 2.5 2.50.14 0.7 1.3 2.5 4.8
Tw Tw Tw
Ts Ts
TwL TwR
TsL TsRtL t1 t2 t3 tR
0.14
tRtL
4.8
0.14 4.8
Validation and Implication of Foundations
Foundations I and II can be validated theoretically Foundations I and II can be validated theoretically Foundations III and IV were verified experimentallyFoundations III and IV were verified experimentally
Problem size of inductance extraction can be greatly reduced w/o loss of accuracyProblem size of inductance extraction can be greatly reduced w/o loss of accuracy Solve 1-trace problem for self inductanceSolve 1-trace problem for self inductance
Reduce 9-D table to 2-D table Reduce 9-D table to 2-D table Solve 2-trace problem for mutual inductanceSolve 2-trace problem for mutual inductance
Reduce 10-D table to 3-D tableReduce 10-D table to 3-D table
Analytical Solutions to Inductance
Without considering skin effect and Without considering skin effect and internal inductanceinternal inductance Self inductanceSelf inductance
k=f(w,t)k=f(w,t) 0 < k < 0.0025 0 < k < 0.0025
Mutual inductanceMutual inductance
]5.0)2
[ln(2)( ktw
llnHL
]1)2
[ln(2
)(l
s
s
llnHL
Inductance is not sensitive to width, thickness and spacingInductance is not sensitive to width, thickness and spacing No need to consider process variations for inductanceNo need to consider process variations for inductance
Not suitable for on-chip interconnects
Extension to Random Nets [Xu-HE, GLSVLSI’01]
Nets with arbitrary locations, lengths, thickness, and etc. Nets with arbitrary locations, lengths, thickness, and etc. available as a web-based tool http://eda.ece.wisc.edu/WebHenryavailable as a web-based tool http://eda.ece.wisc.edu/WebHenry
Mutual inductance LMutual inductance Labab = =
+ - -
Mutual inductance
Lm1 Lm2 Lm3 Lm4
a
b
Accuracy
Table versus FastHenryTable versus FastHenry 400 random displaced parallel wires cases400 random displaced parallel wires cases
Error Distribution
5% most cases Bigger error only found in smaller inductance values
Full RLC Circuit Model
For n wire segments per netFor n wire segments per net RC elements: n RC elements: n self inductance: nself inductance: n mutual inductance: n*(n-1)mutual inductance: n*(n-1)
$$ Self inductance $$$$ Self inductance $$
L11 N11 N12 valL11 N11 N12 val
L12 N13 N14 valL12 N13 N14 val
L21 N21 N22 valL21 N21 N22 val
L22 N23 N24 valL22 N23 N24 val
$$ mutual inductance $$$$ mutual inductance $$
K1 L11 L21 valK1 L11 L21 val
K2 L12 L22 valK2 L12 L22 val
K3 L11 L12 valK3 L11 L12 val
K4 L21 L22 valK4 L21 L22 val
K5 L11 L22 valK5 L11 L22 val
K6 L21 L12 valK6 L21 L12 val
N11N11 N13N13N12N12 N14N14
N21N21 N23N23N22N22 N24N24
Ls(wire12)Ls(wire12)
Lm(wire21, wire12) / sqrt(L21 * L12)Lm(wire21, wire12) / sqrt(L21 * L12)
Normalized RLC Circuit Model
For n segments per wireFor n segments per wire RC elements: n RC elements: n Self inductance: n Self inductance: n Mutual inductance: nMutual inductance: n
$$ Self inductance $$$$ Self inductance $$
L11 N11 N12 valL11 N11 N12 val
L12 N13 N14 valL12 N13 N14 val
L21 N21 N22 valL21 N21 N22 val
L22 N23 N24 valL22 N23 N24 val
$$ mutual inductance $$$$ mutual inductance $$
K1 L11 L21 valK1 L11 L21 val
K2 L12 L22 valK2 L12 L22 val
N11N11 N13N13N12N12 N14N14
N21N21 N23N23N22N22 N24N24
Ls(net1)Ls(net1)
Lm(net1, net2) / sqrt(net1 * net2)Lm(net1, net2) / sqrt(net1 * net2)
Full Versus Normalized
Two waveforms are almost identicalTwo waveforms are almost identical Running time:Running time:
Full Full 99.099.0 seconds seconds NormalizedNormalized 9.19.1 seconds seconds
Application of RLC model:Shielding Insertion
To decide a uniform shielding structure for a given wide busTo decide a uniform shielding structure for a given wide bus Ns: number of signal traces between two shielding tracesNs: number of signal traces between two shielding traces Ws: width of shielding tracesWs: width of shielding traces
... ...
1 2 3 Ns 1 2 3 Ns
Ws Ws Ws
Trade-off between Area and Noise Total 18 signal tracesTotal 18 signal traces
2000um long, 0.8um wide2000um long, 0.8um wide separated by 0.8umseparated by 0.8um
Drivers --Drivers -- 130x; Receivers -- 40x 130x; Receivers -- 40x Power supply: 1.3VPower supply: 1.3V
Ns Ws Noise(v) Routing Area (um) Wire Area (um)
18 -- 0.71 61.1(0.0%) 46.4(0.0%)6 0.8 0.38 64.8 48.06 1.6 0.27 66.4 49.66 2.4 0.22 68.0 51.23 0.8 0.17 69.6(13%) 50.4(8.8%)
Conclusions Inductance is a long-range effectInductance is a long-range effect Inductance can be extracted efficiently use Inductance can be extracted efficiently use
PEEC modelPEEC model Normalized RLC circuit model with a much reduced Normalized RLC circuit model with a much reduced
complexity can be used for busescomplexity can be used for buses Full RLC circuit model should be used for random netsFull RLC circuit model should be used for random nets
Model reduction or sparse inductance model may reduce circuit Model reduction or sparse inductance model may reduce circuit complexitycomplexity
RLC circuit model may be simulated for interconnect RLC circuit model may be simulated for interconnect optimization optimization