Chapter 5 – Sequential Circuitshoangtrang/lecture note/ECE290... · • Combinational Logic:...

Computer Engineering 1 (ECE290)

Chapter 5 – Sequential CircuitsCircuits

Part 1 – Storage Elements and Sequential Circuit Analysis

HOANG Trang

Reference: © 2008 Pearson Education Inc

Circuit Analysis

Reference: © 2008 Pearson Education, Inc.

Overview

Part 1 - Storage Elements and Analysis• Introduction to sequential circuitsIntroduction to sequential circuits• Types of sequential circuits• Storage elements

L t h Latches Flip-flops

• Sequential circuit analysis State tables State diagrams Equivalent states Moore and Mealy Models

Part 2 - Sequential Circuit Design Part 3 – State Machine Design

HOANG TrangReference

Chapter 5 - Part 1 2

Part 3 State Machine Design

Introduction to Sequential Circuits

Combina-Inputs Outputs

A Sequential circuit contains:• Storage elements:

tionalLogicStorage

Elements• Storage elements:Latches or Flip-Flops

• Combinational Logic:State

NextState

Implements a multiple-output switching function

Inputs are signals from the outside.O t t i l t th t id Outputs are signals to the outside.

Other inputs, State or Present State, are signals from storage elements.

Th i i t t N t St t



The remaining outputs, Next State are inputs to storage elements.

Introduction to Sequential Circuits

Combina-Inputs Outputs

tionalLogicStorage

Elements Combinatorial Logic

• Next state functionNext State = f(Inputs, State)

StateNextState

Next State f(Inputs, State)• Output function (Mealy)

Outputs = g(Inputs, State)• Output function (Moore)• Output function (Moore)

Outputs = h(State) Output function type depends on specification and affects

th d i i ifi tl



the design significantly

Types of Sequential Circuits

Depends on the times at which:l b h i i d• storage elements observe their inputs, and

• storage elements change their state S h Synchronous• Behavior defined from knowledge of its

signals at discrete instances of timesignals at discrete instances of time• Storage elements observe inputs and can

change state only in relation to a timingchange state only in relation to a timing signal (clock pulses from a clock)

Asynchronous



y

Types of Sequential Circuits

Synchronous (clock)



Discrete Event Simulation=> to understand sequential circuitq

In order to understand the time behavior of a sequential circuit we use discrete eventsequential circuit we use discrete event simulation.

Rules:• Gates modeled by an ideal (instantaneous) function

and a fixed gate delay• Any change in input values is evaluated to see if it• Any change in input values is evaluated to see if it

causes a change in output value• Changes in output values are scheduled for the fixed

gate delay after the input change• At the time for a scheduled output change, the

output value is changed along with any inputs it



p g g y pdrives

Simulated NAND Gate

Example: A 2-Input NAND gate with a 0.5 ns. delay:F(Instantaneous)

Assume A and B have been 1 for a long time

FA

BDELAY 0.5 ns.

( )

Assume A and B have been 1 for a long time At time t=0, A changes to a 0 at t= 0.8 ns, back to 1.

t (ns) A B F(I) F Comment– 1 1 0 0 A=B=1 for a long time

0 1 0 1 1 0 0 F(I) changes to 10 1 0 1 1 0 0 F(I) changes to 10.5 0 1 1 1 0 F changes to 1 after a 0.5 ns delay0.8 1 0 1 1 0 1 F(Instantaneous) changes to 0



( ) g0.13 1 1 0 1 0 F changes to 0 after a 0.5 ns delay

Gate Delay Models

Suppose gates with delay n ns are represented for n = 0.2 ns, n = 0.4 ns,n = 0.5 ns, respectively:

0.2 0.50.4



Circuit Delay Model

Consider a simple 2-input multiplexer:

A0.4

With function:• Y = A for S = 1• Y = B for S = 0

0.5S

Y0.2

Y B for S 00.4B

AA

SB

YS



“Glitch” is due to delay of inverter

Storing State

What if A con-nected to Y? 0.4

With function:• Y = B for S = 1 and S Y

0.50.2

• Y = B for S = 1, andY(t) dependent onY(t – 0.9) for S = 0

B

BY

0.4

BSS

0.9 ns ? ns? ns

The simple combinational circuit has now become a sequential circuit because its output is a function of a time

Y



sequential circuit because its output is a function of a time sequence of input signals!

Y is stored value in shaded area

Storing State (Continued)

Simulation example as input signals change with time. Changes occur every 100 ns, so that the tenths of ns delaysChanges occur every 100 ns, so that the tenths of ns delays are negligible.

B S Y Comment1 0 0 “ ” 0

Time1 0 0 Y “remembers” 01 1 1 Y = B when S = 11 0 1 Now Y “remembers” B = 1 for S = 00 0 1 No change in Y when B changes0 0 1 No change in Y when B changes0 1 0 Y = B when S = 10 0 0 Y “remembers” B = 0 for S = 01 0 0 No change in Y when B changes

Y represent the state of the circuit, not just an output.

1 0 0 g g



Another example: create Sequential circuit from combinational circuit (nice QUIZ)( )

Design a circuit: inputs S and R that are never simultaneously 1, and output:f = 1 if S was 1 more recently than Ry

0 else



Another example: create Sequential circuit from combinational circuit

Solution? K-Map => how many variables?Tip: 3 variables.



Unstable: in Storing State (Continued)

Suppose we placean inverter in the“f db k th ” 0.4 2“feedback path.”

S Y

0.20.5

0.4

0.2

The following behavior results:

SB

Y0.4

The circuit is saidto be unstable.

For S = 0, the

B S Y Comment0 1 0 Y = B when S = 11 1 1For S 0, the

circuit has becomewhat is called anoscillator. Can be

1 0 1 Now Y “remembers” B 1 0 0 Y, 1.1 ns later1 0 1 Y, 1.1 ns later1 0 0 Y 1 1 ns later



oscillator. Can be used as crude clock.

1 0 0 Y, 1.1 ns later

Unstable: other example

NOR with feedback

X Y1 01 00 1-> 0 -> 1->0 (unstable, oscillator)



S – R Latch (NOR)

Cross-coupling twoNOR t i th

R (reset) QNOR gates gives theS – R Latch: Which has the time Q Which has the time

sequence behavior:

S (set) Q

R S Q Q Comment0 0 ? ? St d t t k

Timebehavior: 0 0 ? ? Stored state unknown0 1 1 0 “Set” Q to 10 0 1 0 Now Q “remembers” 11 0 0 1 “R t” Q t 01 0 0 1 “Reset” Q to 00 0 0 1 Now Q “remembers” 01 1 0 0 Both go low0 0 ? ? U bl !



0 0 ? ? Unstable!

Clocked S - R Latch

Adding two NANDgates to the basic

SQgates to the basic

S - R NAND latchgives the clockedS R l t h

Q

C

S – R latch:

Has a time sequence behavior similar to the basic S-R

RQ

Has a time sequence behavior similar to the basic S-R latch except that the S and R inputs are only observed when the line C is high.

C means “control” or “clock”.



Clocked S - R Latch (continued)

The Clocked S-R Latch can be described by a table: Q(t) S R Q(t+1) CommentS Q(t) S R Q(t+1) Comment

0 0 0 0 No change0 0 1 0 Clear Q0 1 0 1 S t Q

SQ

C

The table describes

0 1 0 1 Set Q0 1 1 ??? Indeterminate1 0 0 1 No change

RQ

The table describeswhat happens after theclock [at time (t+1)]

1 0 1 0 Clear Q1 1 0 1 Set Q1 1 1 ??? Indeterminate[ ( )]

based on:• current inputs (S,R) and

1 1 1 ??? Indeterminate



• current state Q(t).

D Latch

Adding an invertert th S R L t h

DQto the S-R Latch,

gives the D Latch: Note: there are

Q

C

Q Note: there areno “indeterminate”states! The graphic symbol for a

Q

states! Q D Q(t+1) Comment0 0 0 No change

The graphic symbol for aD Latch is:

D Q0 1 1 Set Q1 0 0 Clear Q1 1 1 No Change

C Q



1 1 1 No Change

Flip-Flops

The latch timing problemMaster-slave flip-flop Edge-triggered flip-flopg gg p p Standard symbols for storage elements Direct inputs to flip flops Direct inputs to flip-flops



The Latch Timing Problem

In a sequential circuit, paths may exist through bi ti l l icombinational logic:

• From one storage element to another• From a storage element back to the same storage• From a storage element back to the same storage

element

The combinational logic between a latch output g pand a latch input may be as simple as an interconnect For a clocked D-latch, the output Q depends on

the input D whenever the clock input C has l 1



value 1

The Latch Timing Problem (continued)

Consider the following circuit:

D Q Y

C

D Q

Q

Y

Clock Suppose that initially Y = 0.

ClockC QClock

As long as C = 1, the value of Y continues to change!Th h b d th d l t th l

Y

The changes are based on the delay present on the loop through the connection from Y back to Y.

This behavior is clearly unacceptable.



y p Desired behavior: Y changes only once per clock pulse

The Latch Timing Problem (continued)

A solution to the latch timing problem is to break the closed path from Y to Y within the storage element The commonly-used, path-breaking

solutions replace the clocked D-latch with: 2 solutions:• a master-slave flip-flop• an edge-triggered flip-flop



S-R Master-Slave Flip-Flop

Consists of two clockedS-R latches in series

C

S QC

QC

S QS

with the clock on the second latch inverted

Th i t i b d

C

R Q

CR Q

CR Q

The input is observedby the first latch with C = 1

The output is changed by the second latch with C = 0 p g y The path from input to output is broken by the

difference in clocking values (C = 1 and C = 0). The behavior demonstrated by the example with D

driven by Y given previously is prevented since the clock must change from 1 to 0 before a change in Y



g gbased on D can occur.

Flip-Flop Problem

The change in the flip-flop output is delayed by the pulse width which makes the circuit slower orthe pulse width which makes the circuit slower or S and/or R are permitted to change while C = 1

• Suppose Q = 0 and S goes to 1 and then back to 0 withSuppose Q 0 and S goes to 1 and then back to 0 with R remaining at 0 The master latch sets to 1

A 1 i t f d t th l A 1 is transferred to the slave

• Suppose Q = 0 and S goes to 1 and back to 0 and R goes to 1 and back to 0g The master latch sets and then resets A 0 is transferred to the slave

Thi b h i i ll d 1 t hi



• This behavior is called 1s catching

Flip-Flop Solution => edge-triggered

Use edge-triggering instead of master-slave An edge-triggered flip-flop ignores the pulse

while it is at a constant level and triggers only during a transition of the clock signalduring a transition of the clock signal Edge-triggered flip-flops can be built directly at

the electronic circuit level orthe electronic circuit level, or A master-slave D flip-flop which also exhibits

edge triggered behavior can be usededge-triggered behavior can be used.



Edge-Triggered D Flip-Flop

The edge-triggered D flip-flop is the

C

S QQD QD

same as the master-slave D flip-flop

C

R QC QC Q

It can be formed by:• Replacing the first clocked S-R latch with a clocked D latch or• Adding a D input and inverter to a master-slave S-R flip-flopAdding a D input and inverter to a master slave S R flip flop

The delay of the S-R master-slave flip-flop can be avoided since the 1s-catching behavior is not present

ith D l i S d R i twith D replacing S and R inputs The change of the D flip-flop output is associated with

the negative edge at the end of the pulse



the negative edge at the end of the pulse It is called a negative-edge triggered flip-flop

Positive-Edge Triggered D Flip-Flop

Formed byadding inverter C

S QQD QDadding inverterto clock input

C

R QC QC Q

Q changes to the value on D applied at theQ changes to the value on D applied at the positive clock edge within timing constraints to be specified Our choice as the standard flip-flop for most

sequential circuits



Review FF

Master-Slave FF

Positive-edge-triggered FF

Negative-edge-triggered FF



Review FF (continued): quiz



Standard Symbols for Storage Elements

S S DD

Master-Slave:D with 0 Control

(a) Latches

R

SR SR

R C

D with 1 Control

C

Master-Slave:Postponed outputindicators

DS

C

DS

C

Edge-Triggered:Triggered D

(b) Master-Slave Flip-Flops

C

Triggered DTriggered SR

R C

Triggered SR

R

Dynamicindicator

D

C

D

C


Chapter 5 - Part 1 32(c) Edge-Triggered Flip-Flops

Triggered D

C

Triggered D

C

Sequential Circuit Analysis

General Model• Current State C bi

Inputs Outputs• Current Stateat time (t) is stored in an

Combina-tionalLogic

p

Storage El tarray of

flip-flops.N t St t t ti (t+1)

StateNextState

Elements

• Next State at time (t+1) is a Boolean function of State and Inputs.

CLK

p• Outputs at time (t) are a Boolean function of

State (t) and (sometimes) Inputs (t).



Example 1

Input: x(t) x Output: y(t) State: (A(t) B(t))

AC

D Q

Q

x A

State: (A(t), B(t)) What is the Output

Function? D Q BFunction?C

D Q

Q

B

CP

What is the Next State Function?

y



Example 1 (continued)

Boolean equations f th f tifor the functions:• A(t+1) = A(t)x(t)

+ B(t) (t)C

D Q

Q

x A

A+ B(t)x(t)

• B(t+1) = A(t)x(t)Next State

• y(t) = x(t)(B(t) + A(t))C

D Q

Q'

B

CP

y

O t t



Output

State Table

State table –table with the following four sections:P t St t th l f th t t i bl f h• Present State – the values of the state variables for each allowed state.

• Input – the input combinations allowed.• Next-state – the value of the state at time (t+1) based on

the present state and the input.• Output – the value of the output as a function of the• Output – the value of the output as a function of the

present state and (sometimes) the input. From the viewpoint of a truth table:

• the inputs: Input, Present State• the outputs: Output, Next State



Example 1: State Table (from slide 35) By using the next state and output equations=> State TableA(t+1) = A(t)x(t) + B(t)x(t) ( ) ( ) ( ) ( ) ( )B(t+1) =A (t)x(t) y(t) =x (t)(B(t) + A(t)) Output

Input

Present State Input Next State OutputA(t) B(t) x(t) A(t+1) B(t+1) y(t)

Input

A(t) B(t) x(t) A(t+1) B(t+1) y(t)0 0 0 0 0 00 0 1 0 1 00 1 0 0 0 10 1 1 1 1 01 0 0 0 0 11 0 1 1 0 0



1 1 0 0 0 11 1 1 1 0 0

Example 1: Alternate State Table

2-dimensional table that matches well to a K-map. Present state rows and input columns in Gray code orderstate rows and input columns in Gray code order.

• A(t+1) = A(t)x(t) + B(t)x(t)• B(t+1) =A (t)x(t)

• y(t) = x (t)(B(t) + A(t))

P t N t St t O t tPresent State

Next Statex(t)=0 x(t)=1

Outputx(t)=0 x(t)=1

A(t) B(t) A(t+1)B(t+1) A(t+1)B(t+1) y(t) y(t)0 0 0 0 0 1 0 00 1 0 0 1 1 1 01 0 0 0 1 0 1 0



1 0 0 0 1 0 1 01 1 0 0 1 0 1 0

State Diagrams

The sequential circuit function can be represented in graphical form as a staterepresented in graphical form as a state diagram with the following components:• A circle with the state name in it for each state• A directed arc from the Present State to the Next

State for each state transition• A label on each directed arc with the Input valuesA label on each directed arc with the Input values

which causes the state transition, and• A label: On each circle with the output value produced,

or On each directed arc with the output value



pproduced.

State Diagrams

Label form:• On circle with output included: state/outputpMoore type output depends only on state

• On directed arc with the outputOn directed arc with the outputincluded: input/outputinput/outputMealy type output depends on state and

input



input

Example 1: State Diagram

Which type?x=0/y=1 x=1/y=0x=0/y=0

Which type? Diagram gets

confusing forA B0 0 1 0x=0/y=1

confusing forlarge circuits For small circuits,

x=1/y=0x=1/y=0

x=0/y=1o s a c cu ts,usually easier tounderstand thanth t t t bl

0 1 1 1

y

x=1/y=0the state table x=1/y=0



Equivalent State Definitions

Two states are equivalent:+ each possible input sequence an

identical output sequence.+ next states for each input symbol are the

same or equivalentq



Equivalent State Example

F t t S3 d S2

0 1

For states S3 and S2,• the output for input

0 is 1 and input 1 is 0 1/00/1

S0/0 S10/1

0 is 1 and input 1 is 0,and

• the next state for input S3

1/00/1

1/0

0/1

the next state for input0 is S0 and for input1 is S2.

S2 S31/0

• By the alternative definition, states S3 and S2 are equivalent.



Equivalent State Example

Replacing S3 and S2by a single state gives

0/0 1/0by a single state givesstate diagram:

Examining the new diagram,t t S1 d S2 i l t i 1/0

S0 S10/1

states S1 and S2 are equivalent since• their outputs for input

0 is 1 and input 1 is 0,and S2

1/00/1

and • their next state for input

0 is S0 and for input1 is S2,

S2

1/00/0,

Replacing S1 and S2 by asingle state gives statediagram:

0/0

S0 S10/1

1/0



diagram:1/0

0/

Moore and Mealy Models

Sequential Circuits or Sequential Machines are also called Finite State Machines (FSMs). Two formal models exist: Moore Model

N d ft E F M Mealy Model

• Named after G Mealy• Named after E.F. Moore • Outputs are a function

ONLY of states

• Named after G. Mealy• Outputs are a function

of inputs AND states

• Usually specified on the states.

• Usually specified on the state transition arcs.



Moore and Mealy Example Diagrams

Mealy Model State Diagrami t d t t t t t x=1/y=0maps inputs and state to outputs

0 1

x 1/y 0

x=0/y=0

Moore Model State Diagram maps states to outputs

x=1/y=1x=0/y=0x=0

x=00/0

x=1x=1x=0



1/0 2/1x=1

Moore and Mealy Example Tables

Moore Model state table maps state to outputs Present

StateNext Statex=0 x=1

Output

0 0 1 00 0 1 01 0 2 02 0 2 1

Mealy Model state table maps inputs and state to outputs Present Next State Output

State x=0 x=1 x=0 x=10 0 1 0 01 0 1 0 1



0 0

Mixed Moore and Mealy Outputs

In real designs, some outputs may be Moore t d th t t b M l ttype and other outputs may be Mealy type. Example: Figure 5-17(a) can be modified to

illustrate this 0illustrate this• State 00: Moore• States 01, 10,

0

00/0 010/1

1

States 01, 10,and 11: Mealy

Simplifies output 1/00/1

0/1

0/1p pspecification

10 111/0

1/0



1/0

Conclusion: part 1: analysis???

+ Output function+ Next-state func+ How to present?

. State table (Moore, Mealy)

. State diagram (useful for small circuit)+ Equivalent state (time: method to find out: 20-

30 hours)



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