Chapter 2 Fault Modeling - NCU

Chapter 2Chapter 2 Fault Modeling Fault Modeling

Jin-Fu LiAdvanced Reliable Systems (ARES) Lab.

Department of Electrical EngineeringNational Central University

Jungli, Taiwan

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

Why Model Faults?Fault Models (Faults)Test, Test Set, and TestingFault Collapsing & Test Compaction

Outline


Test Process

The testing problem Given a set of faults in the circuit under test (or device under test), how do we obtain a certain (small) number of test patterns which guarantees a certain (high) fault coverage?

Test processWhat faults to test? (fault modeling)How are test pattern obtained? (test pattern generation)How is test quality (fault coverage) measured? (fault simulation)?How are test vectors applied and results evaluated? (ATE/BIST)


Defect Categories

Defect categoriesRandom defects, which are independent of designs and processesSystematic defects, which depend on designs and processes used for manufacturing

For example, random defects might be caused by random particles scattered on a wafer during manufacturing

A resistive open defect [Source: Cadence]


Logical Fault Models

Systematic defects might be caused by process variations, signal integrity, and design integrity issues.It is possible both random and systematic defects could happen on a single dieWith the continuous shrinking of feature sizes, somewhere below the 180nm technology node, system defects have a larger impact on yield than random defectsLogical faults

Logical faults represent the physical defects on the behaviors of the systems


Why Model Faults

I/O function tests inadequate for manufacturing (functionality versus component and interconnection testing)Real defects (often mechanical) too numerous and often not analyzableA fault model identifies targets for testingA fault model makes analysis possibleEffectiveness measurable by experiments


Fault Nature

Logical faultOne that causes the logic function of a circuit element to be changed to some other function

Parametric faultOne that alters the magnitude of a circuit parameter, causing a change in some factor such as resistance, capacitance, current, etc.

Delay faultOne that relates to circuit delays such as slow gates, usually affecting the timing of the circuit, which may cause hazards, or performance degradation, etc.


Fault Duration Permanent fault

A lasting fault that is continuous and stable, whose nature does not change before, during, and after testing. E.g., a broken wire, an incorrect bonding, etc.A.k.a hard fault or solid fault

Temporary faultA fault that is present only part of the time, occurring at random moments and affecting the system for finite, but unknown, intervals of timeTransition fault

Caused by environmental conditions, e.g., cosmic rays, alpha-particle, etc. A.k.a. soft error in RAMs

Intermittent faultCaused by non-enviornmental conditions, e.g., marginal values of component parameters, wear-out, or critical timing


Single Stuck-At Fault

Single (line) stuck-at faultThe given line has a constant value (0/1) independent of other signal values in the circuit

Properties Only one line is faultyThe faulty line is permanently set to 0 or 1The fault can be at an input or output of a gateSimple logical model is independent of technologydetailsIt reduces the complexity of fault-detection algorithms

One stuck-at fault can model more than one kind of defect


A circuit with single stuck-at fault

Single Stuck-At Fault Example

OutputShorted

to 1

IN OUT

GROUND

POWER

s/1

1 1

1 0

0 (1)


Number of Single Stuck-At Faults

Number of fault sites in a Boolean gate circuit#PI + #gates + #(fanout branches)

Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults

a

b

c

d

e

f

10

g h i 1

s/0j

k

z

0(1)1(0)

1

Test pattern (vector) for h s/0 fault

Good circuit valueFaulty circuit value


Multiple Stuck-At Faults

Multiple stuck-at faultSeveral single stuck-at faults occur at the same time

Multiple stuck-at faults are usually not considered in practice because of two reasons

The number of multiple stuck-at faults in a circuit with k lines is 3K-1, which is too large a number even for circuits of moderate sizeTests for single stuck-at faults are known to cover a very high percentage (greater than 99.6%) of multiple stuck-at faults when the circuit is large and has several outputs


Bridging Faults

Bridging faultTwo or more normally distinct points (lines) are shorted together

Two types of bridging faultsInput bridging

Can form wired logic or voting model

Feedback (input-to-output) bridgingCan introduce feedbackCan cause oscillation or latching (additional memory)

F y

x1x2

xn

F y

x1x2

xnF y

x1x2

xn

Input bridging feedback bridging


Pattern-Sensitive Faults

Pattern-sensitive faultThe presence of a faulty signal depends on signal values of nearby points Most common in DRAM (dynamic random access memory)

Coupling faultPattern sensitivity between a pair of cells

00 00

0

00

0

00

00

0ab c

a=b=0, c=0a=b=1, c=1


Single Cell Fault

Cells can have any implementationAll possible (combinational) cell faults are allowed; truth table can change in any wayC-testability: constant number of test patterns, independent of circuit size (Ripple-carry adder needs only 8 test patterns for all single stuck-at faults)

Source: K. Chakrabarty

FA

x1 y1

z1

c0 FA

x2 y2

z2

FA

x3 y3

z3

FA

x4 y4

z4

c4


Transistor Faults

MOS transistor is considered an ideal switch and two types of faults are modeled

Stuck-open -- a single transistor is permanently stuck in the open state

Turn the circuit into a sequential oneNeed a sequence of at least 2 tests to detect a single faultUnique to CMOS circuits

Stuck-on -- a single transistor is permanently shorted irrespective of its gate voltage

Detection of a stuck-open fault requires two vectorsDetection of a stuck-short fault requires the measurement of quiescent current (IDDQ)


Transistor Stuck-Open Fault

Example:

Two-vector stuck-open testcan be constructed byordering two stuck-at testsA

B

VDD

C

pMOS

nMOS

Stuck-open1

0

0

0

0 1(Z)

Good circuit states

Faulty circuit states

Vector 1: test for A s/0(Initialization vector)

Vector 2 (test for A s/1)


Test Stuck-On Fault Using IDDQ

Example:

A

B

VDD

C

pMOS

nMOS

Stuck-on1

0

0 (X)

Good circuit state

Faulty circuit state

Test vector for A s/0

IDDQ path infaulty circuit


IDDQ Test in Nano-scale Era

Major problem: may results in unacceptable yield loss

IDDQ density function

Density

Mean of fault-free current

Mean of faultycurrent


Crosspoint Fault

A PLA has a device (diode or transistor) at every crosspoint in the AND and OR arrays. The connection of each transistor is programmed to realize the desired logicA crosspoint fault can be caused by an extraor a missing device

Z=X1X2+X1X2

X1

X1

X2X2

AND array

OR array

α

21xxZ =αβ

221 xxxZ +=β


Delay Fault

Delay faultPropagation delays along a path (gate) fall outside the desired limits.Two types of delay faults: path delay fault or gate delay fault

Example:

X1

X2

X3

0 0

1 0

1 1

Z=X1X2+X2X3


Transition Delay Fault

Transition delay faultA gate output may be slow-to-rise or slow-to-fall and that this time is longer than a predefined levelIf the delay fault is large enough, the transition delay fault behaves as a SAF and can be modeled using that method

The primary weakness of transition delay faultTwo pattern sequences for initialization and transition detection are neededThe minimum achievable delay fault size is difficult to determine because of timing hazards. Consequently, a whole mission clock cycle is usually used


Transition Delay Fault

For example,

A

B

C

E

D

Z

2

2

6

22

2

1

1

0

0

Slow-to-risefault

6 8 10 12


Crosstalk Defects

Wire aspect scaling with technology

Capacitive crosstalk noise results from parasitic coupling between two signal nets

[Source: S.-T. Zachariah, DATE03]


Maximal Aggressor Fault Model

Y1

Yi-1

Yi

Yi+1

YN

0 Victim

……

1 Victim

……

Victim

……

Victim

……

Y1

Yi-1

Yi

Yi+1

YN

Y1

Yi-1

Yi

Yi+1

YN

Y1

Yi-1

Yi

Yi+1

YN

Victim Victim Victim Victim

Positive glitch Negative glitch Slow to fall Slow to rise


Test & Test Set

A test for a fault in a circuit C is an input combination for which the output(s) of C is different when is present than when it is not.

A.k.a. test pattern or test vectorX detect then

A test set for a class of faults A is a set of tests T such that and detects

The test set for a fault is For example,

α

α 1)()( =⊕ XfXf α

αTtA ∈∃∈∀ ,α tα αα ffT ⊕=

X1X2

X3X4

f=X1X2+X3X4s/0

}1011,0111,0011{

)(

432431

214321

=+=

⊕+=⊕=

XXXXXX

XXXXXXffT αα

α


Testing & Diagnosis

Testing is a process which includes test pattern generation, test pattern application, and output evaluation.Fault detection tells whether a circuit is fault-free or notFault location provides the location of the detected faultFault diagnosis provides the location and the type of the detected fault

The input X distinguishes a fault from another fault iff , i.e.,

αβ 1)()( =⊕ XfXf βα)()( XfXf βα ≠


Testing & Diagnosis

Example:

Ca/0 and Cc/0 are detected by the test pattern (1,0)If we apply two test patterns: (1,0) & (0, 1)

Two corresponding outputs are faulty Cc/0

Only the output with respect to the input (1,0) is faulty Ca/0

ab c

ca/0a b c0 0 00 1 11 0 11 1 1

ca/1 cb/0 cb/1 cc/0 cc/1

0101

11

1

0

10

1

0

010

011

11

11

11


Fault Collapsing

To generate tests for digital circuits, the test tools are provided with a circuit description, a netlist. The tool then creates a list of all faults (fault list) to be detectedFor large circuits, the list can be quite long. It is thus beneficial to minimize the list whenever possibleSome faults may be detected by the same test patterns. Therefore, only one of these faults needs to be included in the fault listFault collapsing can reduce the size of fault list with two concepts: equivalence and dominance


Equivalent Fault Collapsing

Definition Two faults are called equivalent if every pattern that detects one of the faults also detects the other. That is, their test sets, T1 and T2, are identical: andExample:

SummaryAND gate: all s/0 faults are equivalentOR gate: all s/1 faults are equivalentFor an n-input gate, only n+2 faults need to be considered with equivalence fault collapsing

CA

B

Original fault list={A/0, A/1, B/0, B/1, C/0, C/1}

Therefore, reduced fault list={A/1, B/1, C/1, (C/0 or A/0 or B/0)}

But A/0, B/0, and C/0 are equivalent


Dominance Fault Collapsing

Definition A fault, f1, dominates another fault, f2, if the test set of the latter, T2, is a subset of the test set of the former, T1; that is, . Any test pattern that detects f2 will also detect f1. Therefore, f2 implies f1and it is sufficient to include f2 in the fault listConsider a two-input (A and B) AND gate, a test pattern for the S/1 fault on any of the inputs detects S/1 fault on the output (C). Then C/1 can be dropped from the fault list. Therefore, the fault list is reduced to {A/0,A/1,B/1}

SummaryFor an n-input AND gate, dominates For an n-input OR gate, dominates

12 TT ⊆

1/1+nl0/1+nl

ili ∀,1/ili ∀,0/


Collapsing by Fault Diagrams

Represent each line x by a pair of circles: the upper circle stands for x/1, and the lower circle for x/0Two circles are connected by an edge if they are equivalent

Each net on the diagram represents a single fault equivalence class

&ab

c

a/1a/0

b/1b/0

c/1c/0

{a/0,b/0,c/1}{a/1}{b/1}{c/0}



Fault equivalent diagrams for primitive logic gates

For example

a

c

e

&

AND OR NOR NOT

&

Ib

d

f

a

c

e

b

d

f

6 equivalent classes (6 tests)



Add directed arcs from the dominating faults toward the dominated faults

For fanouts, view the stem and branch as a separate line. Direction of dominance is opposite that of the gates

AND OR NORNAND

Equivalence network

Two tests


Example

a

b

c

&

&

|d

e

f

g

h

a

b

c

d

e

f

g

h

16 single faults10 equivalent classes6 tests


Test Compaction

Equivalence fault collapsing + dominance fault collapsing

Only n+1 faults on any n-input gate need be considered

DefinitionTest compaction refers to the process of reducing the number of test patterns in a test set without reducing its fault coverageEquivalence fault collapsing and dominance fault collapsing can be used to aid test compaction

TheoremIn a fanout-free combinational circuit, any test set which detects all stuck faults on primary inputs will detect all stuck at faults


Test Compaction

DefinitionThe set of all primary inputs and all fanout branches are called checkpoints of the circuitExample,

TheoremIn a combinational circuit, any test set which detects all single (multiple) stuck faults on checkpoints will detect all single (multiple) stuck faults.

Primary inputs Primary outputs

stem branches


Fault Masking

Let TX be the test that detects a fault X . We say that a fault Y functionally masks the fault X iff the multiple fault {Y, G} is not detected by any test in TX

E.g., as the following figure shows, the test 011 is the only test that detects the fault c/0. The same test does not detect the multiple fault {c/0, a/1}. Thus a/1 masks c/0

&

&

&

a

b

c

0

1

1/0

1

00/1


Basic fault models Single stuck-at faultBridging faultPattern-sensitive faultDelay fault…

Fault modeling can simplify the complexity of testingTest compaction is usually used to reduce the number of test patterns

Summary

Chapter 2 Fault Modeling - NCU

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