Cedric Pujol 2019.09

Cedric Pujol 2019.09.05

Product Planning Manager / Keysight

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“We used to consider packages as a painful way to go from our IC to the PCB.

With millimeter-waves, it is now an integral part of our design cycle and it opens possibilities we dreamt of years ago.”

Enabling 5G & Designing Wafer-Level Chip-Scale Packaging

- 5G Design Manager -

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Popular wafer-level and advanced

package types

High-frequency packaging

challenges and opportunities

Assembling the puzzle pieces

swiftly

Application to a mmWave

example

WLP Signal Conditioning ASIC of Keysight Infiniium UXR

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• Wafer Level Packaging (WLP) performs the packaging manufacturing steps at the wafer level

rather than on individual chips


Source: Lam Research

Source : NXP

https://semiengineering.com/whats-what-in-advanced-packaging/

https://www.nxp.com/docs/en/application-note/AN3846.pdf

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• What are the advantages of WLP vs traditional packages ?

• The package size is reduced to close to the die size.

• It removes the package substrate

• The thickness is also much lower

• The manufacturing steps are done by the foundry along with the IPs

• It enables on-wafer testing

Enabling 5G & Designing Wafer-Level Chip-Scale Packaging Source: Amkor

https://amkor.com/packaging/wafer-level-packaging/wlcsp/

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Source: Institute of

Microelectronics, A*STAR

eWLB, InFO, FOWLP, FOPLP, Swift, Slim are all fan-out types

Source: Brewer Science

FAN - I N AN D FAN - O U T


Fan-in pros vs Fan-out

• Die-size footprint

• Easier design flow

• Uncut wafer

Source: statsChipPak

Fan-out pros vs Fan-in

• Number of IOs not limited by the die

size (Fan-in limited to 500 IOs

~8x8mm2)

• More possibilities for SiP integration

• PCB-grade reliability

• Use of known good dies

• Several layers of RDL available

https://www.semanticscholar.org/paper/Molding-process-development-for-high-density-I/Os-Ding-Chong/dfa95a0d24eefd9600315e46f30a92bbd9e88051/figure/10

https://www.youtube.com/watch?v=pOBkSEOLqZ8

http://www.semiconwest.org/sites/semiconwest.org/files/data15/docs/3_Vinayak%20Pandey_STATS%20ChipPAC_PDF.pdf

7Enabling 5G & Designing Wafer-Level Chip-Scale Packaging

With substrateWithout substrate (WLP)

Embedded die InterposersFlip-ChipWLCSP FOWLP

Pictures from 3dic.org

For lower IOs (<~1600), FC-CSP can reach WLP thickness

http://www.3dic.org/

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• There’s no “best” technology. The

choice is depending on

• Electrical Performance

• Cost

• Die size

• Desired level of integration

• The key point is to be able to test early

in the design which one is the most

suited for your IP


Ho, C. et al. “A 77GHz Antenna-in-Package with Low-Cost Solution for

Automotive Radar Applications.” 2018 IEEE 68th Electronic Components and Technology Conference (ECTC) (2018): 191-196.

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I N S I D E K E Y S I G H T U X R


Bare die epoxy-attach on AlN shims

Thin-film routing

Wire-bond and mesh-wrap interconnect

Thermal path down into PCB

Internal assembly and test

• WLP-packaged signal conditioning ICs

• PCB routing

• SMT assembly & interconnect

• Thermal path up into heatsink (exposed-die WLP)

• External assembly and test with improved

yields/rework

WLP enabled a ~60% reduction in module cost without sacrificing performance!

Source: Keysight (B. Poe / International

Wafer-Level Packaging Conference 2018)

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• Wire-Bonds utilize a mechanical welding

process to establish electrical

connectivity. This assembly process

requires that the die pad be sufficiently

large to account for placement/alignment

tolerances and process repeatability.

• The larger the die pad, the higher the

shunt capacitance to ground seen by the

signal.

• WLP packages allow for smaller pads,

which is only bounded by the RDL

patterning accuracy and alignment. This

reduces the parasitic capacitance

associated with the die pads.

R E D U C E D PAD C APAC I T AN C E

Simulated Comparison of

Die Pad Parasitics

Keysight PathWave EM Design (EMPro) Structure

Model of Typical WLP Transition


Simulated vs. Measured UXR

ASIC Package Response (De-Embedded)

Source: Keysight (B. Poe / International


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• The impedance of supply and ground connections

through the WLP package can be reduced by

incorporating RDL planes and placing ball

connections throughout, including at the interior of

the die. This is not practical in alternative low-cost

packages such as QFN, which rely on wire-bond

connections and lead-frames with limited

patterning flexibility.

• In a mixed signal design, care must taken to isolate

simultaneous switching noise introduced by digital

supplies from sensitive analog functional blocks.

Establishing a ground ball ring around digital and

analog balls within the package improves signal

isolation by ~30 dB at 40 GHz.

P O W E R I N T E G R I T Y & I S O L AT I O N

Example RDL patterning of Keysight WLP ASIC

Enabling 5G & Designing Wafer-Level Chip-Scale PackagingSource: Keysight (B. Poe / International


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package types




swiftly


example


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• Maintaining these high bandwidths at high frequencies have a direct impact on the design on every

interconnection and then packages

H I G H F R E Q U E N C I E S AN D H I G H B AN D W I D T H


Source : Keysight (Top considerations for 5GNR device designers)

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• High frequencies have some direct consequences on the design:

• Air Attenuation (propagation loss)

• Interconnect attenuation and delays (conductive losses)

• Propagation problems could be compensated through beamforming and phased array antennas

• Antenna patch width is defined as follows for an operating frequency f0

𝑊𝑖𝑑𝑡ℎ =𝑐

2𝑓0𝜖𝑟+ 12

• Solution to challenge : Integrate antenna arrays inside the package


At 60 GHz, the width is within a few millimeters for common dielectrics

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• Just basic physics of wave

propagation

• Adjusting the time delay or

phase difference between

adjacent antennas results

in maximum radiation in a

specific direction


WLAN 802.11ad transceiver

(courtesy of Sivers IMA)

Source : Wikipedia

https://commons.wikimedia.org/w/index.php?curid=54005685

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• As this is phase-driven, the group delay or amplitude loss in the

package interconnection could be a bottleneck


No error Phase error Amplitude error

Not co-designing can lead

to several dBs of error in

Side Lobes Level and then

deteriorate the original

antenna performances

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D AT AB AS E S C O M E F R O M D I F F E R E N T S O U R C E S


Si Transceiver

Redist (Fan in)

Fanout

Package

Filter

Chip

Goal:

- Assemble all the technologies keeping traceability

- Co-design the interconnections at EM level

- Incorporate the results into circuit simulation


2%

8%

23%

46%

21%

0%

5%

10%

15%

20%

25%

30%

35%

40%

45%

50%

None Less than 1hour

1-2 hours 2-8 hours More than 8hours

spend 2+ hours each week

closing software integration gaps

Source: Removing Time-To-Market Barriers for Design and Test Engineers, Dimensional Research Survey, Dec. 2018

use more than 5 software

tools to design

http://literature.cdn.keysight.com/litweb/pdf/5992-3814EN.pdf

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package types




swiftly


example



• Goals:

• Build a multi-technology assembly and simulation flow which scales with the complexity of the products.

• Build a user friendly capability to EM simulate pieces of this complex multi-technology design without cutting or

modifying the original layout

PathWave ADS

EM Sim

(RFPro)

Layout

(SmartMount)Interoperable, OA based Layouts

Native IC designs

Imported Layouts(ODB++,SiP, BRD) Module-

Level DRC

and LVS

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• A new, unique, innovative way to assemble Multi-technology designs. • Simple: does not need layer mapping, does not require substrate modification

• Powerful: user can write macros to do all sorts of custom mount configurations

• Versatile: Supports read only and interoperable libraries, and scaled technologies (nm Si)

• Scalable: works well for large scale assemblies and stacked technology

Si Tranceiver

Redist (Fan in)

Fanout

Package

Filter

Chip


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AL L O W S U S E R S T O F O C U S O N D E S I G N R AT H E R T H AN S E T T I N G U P E M


• Integration

• 3D view

• Solution for RF PCB, RFIC, MMIC

and RF Modules

• Same user interface for ADS and

Cadence Virtuoso

• Same environment for FEM and

Momentum

• Solver

• No expert setup

• Be confident in the setup of the

simulation and accuracy of the

results

• Better automated defeaturing (via

merging/dummy removal/hatched

planes…)

• Layout

• No Cookie cutting

• No exporting

• No removing active devices and

placing pins & ports

• No reconnecting schematics to

s-parameter files

• Main customer requests for the EM flow

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D E M O


Si Tranceiver

Redist (Fan in)

Fanout

Package

Filter

Chip

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package types




swiftly


example



L1 Package

IC

22FDX

L2 Package

Presented at EuMW 2018

22FDX substrate

First package substrate

Second package substrate

Overall substrate

L1 and ICL2

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M M W PAT H F R O M I C T O PAT C H AN T E N N A



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F E E D - C I R C U I T - I N T E G R AT E D PAT C H AR R AY AN T E N N A


Return losses at antennas input Coupling between antennas


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R AD I AT I O N PAT T E R N O F 4 × 4 PAT C H AN T E N N A AR R AY


Gain : 9.7 dBi

Directivity : 12.4 dBi

Radiation Efficiency : 54%

0° phase at all inputs



• Wafer Level Packaging

performs FanIn or FanOut

packaging manufacturing

directly on the wafer

• Other technologies are

available (FlipChip)

• Choice is made upon electrical,

price and integration

performances

What is Wafer Level

Packaging? Why is 5G

a game changer?

Why is PathWave ADS a

solution for RF advanced

packaging?

• mmWave frequencies allow

antenna integration

• High frequencies make very

interconnect a potential

problem for the final IP

performance

• Co-designing the IC and the

package is then essential a

mandatory part of the design

• PathWave ADS allows to read

databases coming from

different tools

• The focus is made to swiftly

assemble all the pieces

• The EM tools have been

simplified to enable circuit,

antenna and package

designers to perform

simulations seamlessly

Cedric Pujol 2019.09

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