CADMIUM ZINC TELLURIDE (CZT) IMAGER

INTRODUCTION :

1. SCIENTIFIC REQUIRMENT

2. DETECTORS USED IN IMAGER

3. ELECTRICAL CIRCUITS (FRONT END ELECTRONICSUSED) IN THE IMAGER

4. FUNCTIONING NEW CZT DETECTOR MODULE

5. DATA ACCUMULATION FROM VARIOUS DETECTOR TO ENCODER

6. GROUNDING SCHEME.

7. COMPONENT LIST USED IN THESE CIRCUITS.

1) To achieve good spectroscopic capabilities in the range of 10 – 100 KeV with optimum background counts and spectral resolution, even in extended energy range up to 1MeV.

2) Since the detector construction and total area covered is such a way that With help of Coded Aperture Mass (CAM) a moderate image can be studied in 10 -100 KeV energy range.

3) CZT detector (pixilated form) has large energy bandwidth with fine

resolution within 10 -100 KeV energy range.

4) Reducing background counts using collimation and anti-coincidence

detector (Veto Detector) below the CZT detector plane.

SENSITIVITY OF CZT IMAGERSENSITIVITY OF CZT IMAGER

Minimum detectable intensity = 3 Nb / (A* T * * E)Photons /(cmPhotons /(cm22 Sec Sr KeV) Sec Sr KeV)

WHEREWHERE

NNbb is background is background

is detector efficiencyis detector efficiency

δEδE is the energy interval of observation is the energy interval of observation

TT is the integration time is the integration time

BACKGROUND (NBACKGROUND (Nbb) HAS TO BE ) HAS TO BE AS LOW AS POSSIBLE AS LOW AS POSSIBLE

flux

flux

EnergyEnergy

BackgroundBackground

SourceSource

- 500 V

DETECTOR MODULE

CSPA

XAIM3.2 CHIP

QUADRANT

4 x 4 MODULE

16 X 16 CZT PIXEL ARRAY

FUNCTIONAL BLOCK DIAGRAM OF ANLOG CIRCUITS IN XaIm3.2

BIASES USED: 1) Threshold 2) Shaper time 3) Reset width 4) Delay Trigger with help of programming. A

1. It is fully-driven charge signal acquisition chip.

3. Provision of programming for needed parameters of the chip like threshold, shaping time constant and various other parameter.

ClkIn and RegIn are Clock and Input for the Shift-resistor.

2. All Analog and Digital outputs are current driven for 1 micro second.

Each cell is addressable.

4. The chip requires +2 and -2 volts for operation.

FEATURES OF ASIC XaIm3.2

5. Daisy chaining of chips.

M1 M2 M3 Mn

ADDR BUS

DATA BUS

TRIG & MULTI HIT

DATA

CLOCK

ENERGY PULSE

SOXS payload on GSAT-II

CZT

DET

OPTO

+PROCS

ELCTR

BF

+V

-V HV

SCINTILATOR

AMPL. P.D. +ADC

HV 990V

CSPA+ POST AMPLIFIER

COMPARATOR

BIAS

FPGA

+5V

15V

XAIM_OUTP

XAIM_OUTM

R539K09

R52

1K

C22

47MF

D2

1N4150

R51

1K

R50

100E

R49

162E

Q2

2N2222

U13

HCPL4562

2

3

4

6

7

1

5

8

A

K

K2

C

B

NC

E

VCCR58

6K81

R57

14K7

R56

460E

R55750E

Q5

2N2222

Q4

2N2222

R54

100E

Q3

2N2222

R9

33E

1%

DIFF. AMPLIFIER

AMPL.WITH VARIABLE GAIN

ANALOG SWITCH

PEAK DETECTOR

12-BIT ADC

FPGA

SCHEMATIC BLOCK DIAGRAM OF CZT PROCESSING ELECTRONICS

WINDOW COUNTERS

To FPGA

AMPTEK

203

POST-AMPL.

BIAS VOLTAGE

LLD

TO COUNTER

M_CNTRL

ANALOG SWITCH

PEAK DETECTOR8-BIT

ADC

VETO-PMT O/P

POST AMPL MONO

COMPARATOR

BIAS VOLTAGE

CsI(Tl)

S 3590 Si PIN PHOTO DIODE

eV-5128

PRE-AMPL.

Schematic block diagram of Alpha –Tag electronics.

1 USF

F

M-Rst

AD 0

AD 15

CZT

TRIG.

LATCHOPTO

12-BIT ADC

8-BIT ADC

1. ANY EVENT MORE THAN LLD THRESHOLDE, TRIGERS THE CZT EVENT ANALYSIS.

2. NEXT CZT EVENT WILL ANALYSED ONLY AFTER 12-15 MICRO SEC

3- LINES OF COUNTERS

MULTI-HIT

ALPHA-TAG

FPGA

VCO

3-BIT GAIN CNTRL

3-BIT LLD CNTRL

3-BIT VETO LLD CNTRL

VCO CNTRL

CZT

VETO

MICRO-CONTROLER

PROGRAMMING OF CZT MODULES

CZT WAVEFORMS

VETO WAVEFORMS

Veto_Trig. Pulse (1 U Sec.)

Processing Time +ADC Con. Time (8 U Sec.)

Read_Out _Time (4 U Sec.)

Veto_Reset Pulse

CZT Trig Pulse (1 U Sec.)

Processing Time + ADC Conversion Time( 12 U Sec.)

CZT Read _Out Pulse (2 U Sec.)

Reset Pulse (1 U Sec.)

CZT TRIG. PULSE

PROCESSING TIME +ADC CONV. TIME

READ_OUT TIME

RESET

PROCESSING TIME + ADC CONV. TIME

READ_OUT TIME

VETO_RESET

VETO TRIG. TIME

LV DC/DC used for powering all detectors and supporting electronics.

Conventional High voltage supplies -500 volts for CZT biasing and +1000 volts for Veto PMT.

Internal biasing voltages are generated inside the package.

HV

Vf

Vr

POWER OSCI. + RECT.+ MULTI. SECTION

SERIES PASS REGULATOR

CURRENT SENSOR CKT.

COMMANDS

REFERENCE VOLTAGE CONTRL.

DIFFERNTIAL AMPL.

+ V

MUXVOLTAGE CONTROL OSCILLATOR

COMMANDS FROM FPGA

+ 5 V+ 10 VLLD CZTLLD VETO

THERMISTOREHV on-offHV RefHV Feedback

O/P Frequency

2 kHz TO 20 kHz

For Variation of 0-10 volts