Bruce Jacob ENEE 359a University of Digital VLSI Design ... · Lecture/s 20-22 DRAM Systems Bruce...
Transcript of Bruce Jacob ENEE 359a University of Digital VLSI Design ... · Lecture/s 20-22 DRAM Systems Bruce...
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 1
UNIVERSITY OF MARYLAND
ENEE 359a
Digital VLSI Design
CMOS Memories and Systems: Part I, DRAM Systems
Prof . Bruce Jacobblj@ece .umd.edu
Credit where credit is due:
Slides contain original artwork (© Jacob 1999–2004, Wang 2003/4).
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 2
UNIVERSITY OF MARYLAND
Overview
DRAM:
•
DRAM systems
•
DRAM cir cuits
SRAM:
•
SRAM systems
•
SRAM cir cuits
•
Register fi les
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 3
UNIVERSITY OF MARYLAND
DRAM
Dual In-line Memor y Module (DIMM)
(printed cir cuit boar d w/ DRAM c hips on it)
Switching element
StorageBit Line
Word Line(transistor)
element(capacitor)
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 4
UNIVERSITY OF MARYLAND
The Memor y System
… and DRAM’ s place within it.
(typical PC-style desktop system)
DRAMArrayDRAM
ArrayDRAMArray
SecondaryCache
CPU
SecondaryCache
MemoryController
Memory modules
CPU
GraphicsCo-Processor
PrimaryCache
I/OController
HardDrive/s
NetworkInterface
SCSIController
Backside bus
Frontside busDRAM busAGP bus
PCI bus
Other Low-BWI/O Devices
Keyboard
Mouse
DR
AM
DR
AM
DR
AM
DR
AM
SCSI bus
North BridgeChipset
South BridgeChipset
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 5
UNIVERSITY OF MARYLAND
DRAM-System Closeup
Traditional “JEDEC-Style” DRAM system
DRAM
DRAM
DRAM
DRAM
DIMM
1
MemoryController
Address &
Data Bus
Chip Select
1
DRAM
DRAM
DRAM
DRAM
DIMM
2
Address &
Data Bus
Chip Select
2
Command Busses
Command Busses
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 6
UNIVERSITY OF MARYLAND
Memor y Request Over view
Fetch Decode WBMemExec
virtual to physical address translation(DTLB access) [A
1
]
[A
2
] L1 D-Cacheaccess. If missthen proceed to
[A
3
] L2 Cacheaccess. If missthen send to BIU
Bus Interface Unit (BIU)obtains data from mainmemory [A
4
+ B]
[B
1
] BIU arbitrates [B
2
] requestsent to system controller
[B
8
] system controller returns data to CPU
Stages of instruction execution
Proceeding through
the memory hierarchy
in a modern processor
[B
3
]physical addr.
to memory addr.translation.
[B
4
] memory
L1cache
L2cache
DTLB
Processor Core
BIU (Bus Interface Unit)
RAM
for ownership ofaddress bus **
[B
5
] memoryaddr. Setup request
scheduling** (RAS/CAS)
[A
1
]
[B
8
]
[A
4
]
[A
2
] [A
3
]
** Steps not required for some processor/system controllers. protocol-dependent.
[B
4
]
[B
3
]
[B
2
]
[B
1
]
I/O to memory traffic memory request scheduling
physical to memory addrmapping [B
7
]
[B
5
]
readdatabuffer
system controller
processor
DRAM core
[B
6
]
[B
6
, B
7
] DRAM dev.obtains data and returns to controller
Part A: Searchingon-chip for data
Part B: Goingoff-chip for data
Progression of a Memory Read Transaction Request Through Memory System
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 7
UNIVERSITY OF MARYLAND
Access-Pr otocol Basics
DRAM ORGANIZATION
... Bit Lines...
Memor yArra y
Ro
w D
ecod
er
. .. W
ord
Line
s ...
DRAM
Storage element
Switching element
Bit Line
Word Line
Data In/OutBuff ers
Sense Amps
Column Decoder
(capacitor)
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 8
UNIVERSITY OF MARYLAND
Access-Pr otocol Basics
BUS TRANSMISSION
BUSMEMORY
CONTROLLERCPU
... Bit Lines...
Memor yArra y
Ro
w D
ecod
er
. .. W
ord
Line
s ...
DRAM
Data In/OutBuff ers
Sense Amps
Column Decoder
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 9
UNIVERSITY OF MARYLAND
Access-Pr otocol Basics
[PRECHARGE and] R OW ACCESS
AKA: OPEN a DRAM Page/Row
RAS (Row Ad dress Str obe)
or
orACT (Activ ate a DRAM Page/Row)
BUSMEMORY
CONTROLLERCPU
... Bit Lines...
Memor yArra y
Ro
w D
ecod
er
. .. W
ord
Line
s ...
DRAM
Data In/OutBuff ers
Sense Amps
Column Decoder
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 10
UNIVERSITY OF MARYLAND
Access-Pr otocol Basics
COLUMN ACCESS
READ Commandor
CAS: Column Ad dress Str obe
BUSMEMORY
CONTROLLERCPU
... Bit Lines...
Memor yArra y
Ro
w D
ecod
er
. .. W
ord
Line
s ...
DRAM
Data In/OutBuff ers
Sense Amps
Column Decoder
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 11
UNIVERSITY OF MARYLAND
Access-Pr otocol Basics
DATA TRANSFER
note: page mode enab les o verlap with CAS
BUSMEMORY
CONTROLLERCPU
... Bit Lines...
Memor yArra y
Ro
w D
ecod
er
. .. W
ord
Line
s ...
DRAM
Data In/OutBuff ers
Sense Amps
Column Decoder
... with optional ad ditionalCAS: Column Ad dress Str obe
Data Out
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 12
UNIVERSITY OF MARYLAND
Access-Pr otocol Basics
BUS TRANSMISSION
BUSMEMORY
CONTROLLERCPU
... Bit Lines...
Memor yArra y
Ro
w D
ecod
er
. .. W
ord
Line
s ...
DRAM
Data In/OutBuff ers
Sense Amps
Column Decoder
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 13
UNIVERSITY OF MARYLAND
Access-Pr otocol Basics
B
CD
DRAM
E
2
/E
3
E
1
F
A
CPU Mem
Controller
A: Transaction request may be delayed in QueueB: Transaction request sent to Memory ControllerC: Transaction converted to Command Sequences
(may be queued)D: Command/s Sent to DRAME
1
: Requires only a
CAS
orE
2
: Requires
RAS + CAS
or
F: Transaction sent back to CPU
“DRAM Latency” = A + B + C + D + E + F
E
3:
Requires
PRE + RAS + CAS
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 14
UNIVERSITY OF MARYLAND
Access-Pr otocol Basics
Read Timing f or Con ventional DRAM
RowAddress
ColumnAddress
ValidDataout
RAS
CAS
Address
DQ
RowAddress
ColumnAddress
ValidDataout
Data Transf er
Column Access
Row Access
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 15
UNIVERSITY OF MARYLAND
Access-Pr otocol Basics
Read Timing f or Sync hronous DRAM
(RAS + CAS + OE ... == Command Bus)
Command
Address
DQ
Cloc k
RowAddr
ColAddr
ValidData
ValidData
ValidData
ValidData
ACT READ
RAS
CAS
Data Transf er
Column Access
Transf er Overlap
Row Access
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 16
UNIVERSITY OF MARYLAND
DRAM Cir cuit Basics
“Ro w” Defined
Bit Lines
Word Line
ÒRowÓ of DRAM
Row Size: 8 Kb @ 256 Mb SDRAM node4 Kb @ 256 Mb RDRAM node
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 17
UNIVERSITY OF MARYLAND
DRAM Cir cuit Basics
Sense Amplifi er I:
6 rows shown
SenseandAmplify
1
2
3
4
5
6
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 18
UNIVERSITY OF MARYLAND
DRAM Cir cuit Basics
Sense Amplifi er I:
6 rows shown
V
cc
(logic 1) Gnd (logic 0)
SenseandAmplify
1
2
3
4
5
6
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 19
UNIVERSITY OF MARYLAND
DRAM Cir cuit Basics
Sense Amplifi er II : Precharged
V
cc
(logic 1) Gnd (logic 0) V
cc
/2
prec harged to V
cc
/2
SenseandAmplify
1
2
3
4
5
6
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 20
UNIVERSITY OF MARYLAND
DRAM Cir cuit Basics
Sense Amplifi er III : Destructive Read
SenseandAmplify
1
2
3
4
5
6
V
cc
(logic 1) Gnd (logic 0) V
cc
/2
WordlineDriven
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 21
UNIVERSITY OF MARYLAND
DRAM Cir cuit Basics
“Column” Defined
ÒOne RowÓ of DRAM
Column: Smallest addressable quantity of DRAM on chip
SDRAM*: column size == chip data bus width (4, 8,16, 32)RDRAM: column size != chip data bus width (128 bit fixed)
4 bit wide columns
SDRAM*: get ÒnÓ columns per access. n = (1, 2, 4, 8)RDRAM: get 1 column per access.
#2 #3 #4 #5#0 #1
* SDRAM means SDRAM and variants. i.e. DDR SDRAM
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 22
UNIVERSITY OF MARYLAND
DRAM Ar chitecture Basics
PHYSICAL ORGANIZATION
This is per bank …Typical DRAMs ha ve 2+ banks
x2 DRAM x4 DRAM x8 DRAM
... Bit Lines...
Sense Amps
. . .
.
DataBuff ers
x8 DRAM
Ro
w D
ecod
er
Memor yArra y
Column Decoder
... Bit Lines...
Sense Amps. .
. .
DataBuff ers
x2 DRAMR
ow
Dec
oder
Memor yArra y
Column Decoder
... Bit Lines...
Sense Amps
. . .
.
DataBuff ers
x4 DRAM
Ro
w D
ecod
er
Memor yArra y
Column Decoder
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 23
UNIVERSITY OF MARYLAND
DRAM “Speed” Part I
How fast can I mo ve data fr om DRAM cell to sense amp?
RCD (Row Command Dela y)
BUSMEMORY
CONTROLLERCPU
... Bit Lines...
Memor yArra y
Ro
w D
ecod
er
. .. W
ord
Line
s ...
DRAM
Data In/OutBuff ers
Sense Amps
Column Decoder
t
RCD
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 24
UNIVERSITY OF MARYLAND
DRAM “Speed” Part II
How fast can I g et data out of sense amps back into memor y contr oller?
BUSMEMORY
CONTROLLERCPU
... Bit Lines...
Memor yArra y
Ro
w D
ecod
er
. .. W
ord
Line
s ...
DRAM
Data In/OutBuff ers
Sense Amps
Column Decoder
CAS: Column Ad dress Str obe
t
CAS
aka
t
CL
t
CASL
aka
CASL: Column Ad dress Str obe Latenc y
CL: Column Ad dress Str obe Latenc y
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 25
UNIVERSITY OF MARYLAND
DRAM “Speed” Part III
How fast can I mo ve data fr om DRAM cell into memor y contr oller?
RAC (Random Access Dela y)
BUSMEMORY
CONTROLLERCPU
... Bit Lines...
Memor yArra y
Ro
w D
ecod
er
. .. W
ord
Line
s ...
DRAM
Data In/OutBuff ers
Sense Amps
Column Decoder
t
RAC
= t
RCD
+ t
CAS
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 26
UNIVERSITY OF MARYLAND
DRAM “Speed” Part IV
How fast can I prec harge DRAM arra y so I can enga ge another RAS?
RP (Row Prec harge Delay)
BUSMEMORY
CONTROLLERCPU
... Bit Lines...
Memor yArra y
Ro
w D
ecod
er
. .. W
ord
Line
s ...
DRAM
Data In/OutBuff ers
Sense Amps
Column Decoder
t
RP
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 27
UNIVERSITY OF MARYLAND
DRAM “Speed” Part V
How fast can I read data fr om tw o diff erent rows?
RC (Row Cyc le Time)
BUSMEMORY
CONTROLLERCPU
... Bit Lines...
Memor yArra y
Ro
w D
ecod
er
. .. W
ord
Line
s ...
DRAM
Data In/OutBuff ers
Sense Amps
Column Decoder
t
RC
= t
RAS
+ t
RP
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 28
UNIVERSITY OF MARYLAND
DRAM “Speed” Summar y I
What do I care about?
RC :Row Cyc le Time
t
RC
= t
RAS
+ t
RP
RP :Row Prec harge Delay
t
RP
RAC :Random Access Dela y
t
RAC
= t
RCD
+ t
CAS
CAS: Column Ad dress Str obe
t
CAS
RAS: Row Ad dress Str obe
t
RCD
Seen in ads.Easy to e xplain
Embed ded systems designer sDRAM man ufactuer s
Computer Ar chitect:Latenc y bound code i.e. linked list tra versal
Easy to sell
RCD: Row Command Dela y
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 29
UNIVERSITY OF MARYLAND
DRAM “Speed” Summar y II
DRAM Type Frequenc yData Bus Width (per c hip)
Peak Data Band width (per Chip)
Random Access Time (t
RAC
)
Row Cyc le Time (t
RC
)
PC133 SDRAM
133 16 200 MB/s 45 ns 60 ns
DDR 266 133 * 2 16 532 MB/s 45 ns 60 ns
PC800RDRAM
400 * 2 16 1.6 GB/s 60 ns 70 ns
FCRAM 200 * 2 16 0.8 GB/s 25 ns 25 ns
RLDRAM 300 * 2 32 2.4 GB/s 25 ns 25 ns
DRAM is “slo w”But doesn’t ha ve to bet
RC
< 10ns ac hievable
Higher die cost
Not commodity Expensive
Not adopted in standar d
data: Dec. 2002
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 30
UNIVERSITY OF MARYLAND
Signal Pr opagation
Ideal Transmission Line
A B
PC Boar d + Module Connector s + Varying Electrical Loads
= Rather non-Ideal Transmission Line
~ 0.66c = 20 cm/ns
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 31
UNIVERSITY OF MARYLAND
DRAM Interface: Protocol
The Digital F antasy
Row
r
0
d
0
d
0
d
0
d
0
Col
Data
a
0
r
1
d
1
d
1
d
1
d
1
RASlatenc y
CASlatenc y Pipelined Access
Pretend that the w orld looks like this
But...
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 32
UNIVERSITY OF MARYLAND
DRAM Interface: Signals
12
VDDQ(Pad)FCRAM side
Controller side
VSSQ(Pad)
DQS (Pin)DQ0-15 (Pin)
DQS (Pin)DQ0-15 (Pin)
skew=158psec skew=102psec
RReeaadd ffrroomm FFCCRRAAMMTTMM @@440000MMHHzz DDDDRR((NNoonn--tteerrmmiinnaattiioonn ccaassee))
*Toshiba Presentation, Denali MemCon 2002
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 33
UNIVERSITY OF MARYLAND
Interface: Cloc king Issues
0
th
N
th
0
th
N
th
ClkSRC
ClkSRC
What Kind of Cloc king System?
Figure 1:Sliding Time
Figure 2:H Tree?
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 34
UNIVERSITY OF MARYLAND
Path Length Diff erential
AController
Path #3Path #2
Path #1
Bus Signal 2Bus Signal 1
Intermodule Connectors
B
High Frequenc y AND Wide Parallel Busses are Difficult to Implement
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 35
UNIVERSITY OF MARYLAND
Timing Variations
Contr oller
Contr oller
4 Loads
1 Load
Cloc k
Cmd to 1 Load
Cmd to 4 Loads
How man y DIMMs in System?
How man y devices on eac h DIMM?
Infinite v ariations on timing!
Who b uilt the memor y module?
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 36
UNIVERSITY OF MARYLAND
Topology
Contr oller
DRAMChip
DRAMChip
DRAMChip
DRAMChip
DRAMChip
DRAMChip
DRAMChip
DRAMChip
DRAMChip
DRAMChip
DRAMChip
DRAMChip
DRAMChip
DRAMChip
DRAMChip
DRAMChip
?
DRAM System Topology Determines
and Signal Pr opagation LengthsElectrical Loading Conditions
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 37
UNIVERSITY OF MARYLAND
SDRAM Topology Example
Command &
Data bus
SingleChannelSDRAMContr oller
Address
(64 bits)(16 bits)
Loading Imbalance
x16DRAMChip
x16DRAMChip
x16DRAMChip
x16DRAMChip
x16DRAMChip
x16DRAMChip
x16DRAMChip
x16DRAMChip
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 38
UNIVERSITY OF MARYLAND
SDRAM Topology Example II
(Same topology , diff erent dra wing, a little more detail)
DRAM
DRAM
DRAM
DRAM
DIMM
1
MemoryController
Address &
Data Bus
Chip Select
1
DRAM
DRAM
DRAM
DRAM
DIMM
2
Address &
Data Bus
Chip Select
2
Command Busses
Command Busses
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 39
UNIVERSITY OF MARYLAND
RDRAM Topology Example
RDRAMContr oller
Controller
Chip
Packets tra veling do wnParallel P aths. Skew is minimal b y design.
cloc kturnsaround
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 40
UNIVERSITY OF MARYLAND
I/O - Diff erential P air
Differential Pair Transmission Line
Single Ended Transmission Line
Increase Rate of bits/s/pin ?
Cost Per Pin?
Pin Count?
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 41
UNIVERSITY OF MARYLAND
I/O - Multi Le vel Logic
time
logic 01 range
logic 00 range
volt
age
logic 10 range
logic 11 range
Increase Rate of bits/s/pin
V
ref_2
V
ref_0
V
ref_1
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 42
UNIVERSITY OF MARYLAND
Packaging
DIP
“good old da ys”
FBGA
LQFP
TSOP
SOJ
Small Outline J-lead
Thin Small Outline
Low Profile Quad
Fine Ball Grid Arra y
Flat Package
Package
Features Target Specifi cation
Package FBGA LQFP
Speed 800MBps 550Mbps
Vdd/Vddq 2.5V/2.5V (1.8V)
Interface SSTL_2
Row Cycle Time t
RC
35ns
Memor y Roadmap f orHynix NetDDR II
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 43
UNIVERSITY OF MARYLAND
Access Pr otocol
Single Cycle Cmd
Multiple Cycle Cmd
Cmd
Data
Cmd
Data
r
0
d
0
d
0
d
0
d
0
r
0
r
0
r
0
r
0
d
0
d
0
d
0
d
0
Single Cyc le Command
Multiple Cyc le Command
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 44
UNIVERSITY OF MARYLAND
Access Pr otocol (r/r)
Contr ol DRAMDRAMDRAMDRAM
Row
r
0
d
0
d
0
d
0
d
0
Col
Data
a
0
r
1
d
1
d
1
d
1
d
1
RASlatenc y
CASlatenc y Pipelined Access
Consecutive Cac he Line Read Requests to Same DRAM Ro w
a = Active (open pa ge)
r = Read (Column Read)
d = Data (Data c hunk)
Command
Data
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 45
UNIVERSITY OF MARYLAND
Access Pr otocol (r/w)
w
0
d
0
d
0
d
0
d
0
Col
Data
r
1
d
1
d
1
d
1
d
1Case 2: Read Follo wing a Write Command to Same DRAM De vice
w
0
d
0
d
0
d
0
d
0
Col
Data
r
1
d
1
d
1
d
1
d
1Case 1: Read Follo wing a Write Command to Diff erent DRAM De vices
Sense Amps
Column Decoder
Data In/OutBuff ers
DRAMOne Datapath - Two Commands
w
0
d
0
d
0
d
0
d
0
Col
Data
r
1
d
1
d
1
d
1
d
1Soln: Delay Data of Write Command to matc h Read Latenc y
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 46
UNIVERSITY OF MARYLAND
Address Mapping
Access Distrib ution f or Temp Contr olAvoid Bank Confl ictsAccess Reor dering f or perf ormance
Physical Address
Row Ad dr Bank IdCol Ad drDevice Id
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 47
UNIVERSITY OF MARYLAND
Example: Bank Confl icts
... Bit Lines...
Memor yArra y
Sense Amps
Ro
w D
ecod
er
Column Decoder
. . .
.
... Bit Lines...
Memor yArra y
Sense Amps
Ro
w D
ecod
er
Column Decoder
. . .
.
... Bit Lines...
Memor yArra y
Sense Amps
Ro
w D
ecod
er
Column Decoder
. . .
.
... Bit Lines...
Memor yArra y
Sense Amps
Ro
w D
ecod
er
Column Decoder
. . .
.Multiple Banksto Reduce Access Conflicts
Read 05AE5700Read 023BB880
Read 00CBA2C0
Device id 3, Row id 266, Bank id 0Device id 3, Row id 1B A, Bank id 0
Device id 3, Row id 052, Bank id 1Read 05AE5780 Device id 3, Row id 266, Bank id 0
More Banks per Chip == P erformance == Logic Overhead
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 48
UNIVERSITY OF MARYLAND
Example: Access Reor dering
Read 05AE5700Read 023BB880
Read 00CBA2C0
Device id 3, Row id 266, Bank id 0Device id 3, Row id 1B A, Bank id 0
Device id 1, Row id 052, Bank id 1Read 05AE5780 Device id 3, Row id 266, Bank id 0
Read
Act
Data
Prec
Act = Activ ate Page (Data mo ved fr om DRAM cells to r ow buff er)Read = Read Data (Data mo ved fr om r ow buff er to memor y contr oller)Prec = Prec harge (close pa ge/evict data in r ow buff er/sense amp)
Read
Act
Data
Prec
1234
Read
Act
Data
Read
Act
Data
Prec
Strict Or dering
Read
Act
Data
Prec4 2
Read
Act
Data
Prec
3
1
1 2 3
Memor y Access Re-or dered
t
RC
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 49
UNIVERSITY OF MARYLAND
Technology Roadmap (ITRS)
2004 2007 2010 2013 2016
Semi Generation (nm) 90 65 45 32 22
CPU MHz 3990 6740 12000 19000 29000
MLogicT ransistor s/cm^2 77.2 154.3 309 617 1235
High Perf c hip pin count 2263 3012 4009 5335 7100
High Performance c hipcost (cents/pin)
1.88 1.61 1.68 1.44 1.22
Memor y pin cost (cents/pin)
0.34 -1.39
0.27 - 0.84
0.22 - 0.34
0.19 - 0.39
0.19 - 0.33
Memor y pin count 48-160 48-160 62-208 81-270 105-351
Free Transistor s &Costl y Inter connects
Trend:
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 50
UNIVERSITY OF MARYLAND
Choices f or Future
DR
AM
CPU
DR
AM
DR
AM
DR
AM
DR
AM
CPU
CPU
CPU
DRAM
DR
AM
DR
AM
DR
AM
DRAM
DRAM DRAM
Memor y Contr oller
Direct ConnectCustom DRAM:Highest Band width +Low Latenc y
Direct ConnectCommodity DRAMLow Band width +Low Latenc y
Direct Connectsemi-comm. DRAM:High Band width +Low/Moderate Latenc y
Indirect Connection
Inexpensive DRAM
Highest Band width
Highest Latenc y
DRAM DRAM
DRAM DRAM
DRAM DRAM
DRAM DRAM
DRAM DRAM
DRAM DRAMDRAM DRAM
DRAM DRAM
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 51
UNIVERSITY OF MARYLAND
DRAM Evolution ary Tree
(Mostly) Structural Modifications
Interface Modifications
Structural
Conventional
FPM EDO ESDRAM
Rambus, DDR/2 Future Trends
. . .
. . .
. .
. . . . . .
MOSYS
FCRAM
VCDRAM
$
ModificationsTargetingLatency
Targeting Throughput
Targeting Throughput
DRAM
SDRAMP/BEDO
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 52
UNIVERSITY OF MARYLAND
DRAM Evolution
Read Timing f or Con ventional DRAM
RowAddress
ColumnAddress
ValidDataout
RAS
CAS
Address
DQ
RowAddress
ColumnAddress
ValidDataout
Data Transf er
Column Access
Transf er Overlap
Row Access
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 53
UNIVERSITY OF MARYLAND
DRAM Evolution
Read Timing f or Fast Page Mode
RowAddress
ColumnAddress
ValidDataout
ColumnAddress
ColumnAddress
ValidDataout
ValidDataout
RAS
CAS
Address
DQ
Data Transf er
Column Access
Transf er Overlap
Row Access
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 54
UNIVERSITY OF MARYLAND
DRAM Evolution
Read Timing f or Extended Data Out
RowAddress
ColumnAddress
ValidDataout
RAS
CAS
Address
DQ
ColumnAddress
ColumnAddress
ValidDataout
ValidDataout
Data Transf er
Column Access
Transf er Overlap
Row Access
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 55
UNIVERSITY OF MARYLAND
DRAM Evolution
Read Timing f or Bur st EDO
RowAddress
ColumnAddress
RAS
CAS
Address
DQ
Data Transf er
Column Access
Transf er Overlap
Row Access
ValidData
ValidData
ValidData
ValidData
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 56
UNIVERSITY OF MARYLAND
DRAM Evolution
Read Timing f or Pipeline Bur st EDO
RowAddress
ColumnAddress
RAS
CAS
Address
DQ
Data Transf er
Column Access
Transf er Overlap
Row Access
ValidData
ValidData
ValidData
ValidData
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 57
UNIVERSITY OF MARYLAND
DRAM Evolution
Read Timing f or Sync hronous DRAM
(RAS + CAS + OE ... == Command Bus)
Command
Address
DQ
Cloc k
RowAddr
ColAddr
ValidData
ValidData
ValidData
ValidData
ACT READ
RAS
CAS
Data Transf er
Column Access
Transf er Overlap
Row Access
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 58
UNIVERSITY OF MARYLAND
DRAM Evolution
Inter -Row Read Timing f or ESDRAM
Command
Address
DQ
Cloc k
RowAddr
ColAddr
ValidData
ValidData
ValidData
ValidData
ACT READ
RowAddr
ColAddr
ValidData
ValidData
ValidData
ValidData
ACT READPRE
ÒRegularÓ CAS-2 SDRAM, R/R to same bank
Command
Address
DQ
Cloc k
RowAddr
ColAddr
ValidData
ValidData
ValidData
ValidData
ACT READ
RowAddr
ColAddr
ValidData
ValidData
ValidData
ValidData
ACT READ
ESDRAM, R/R to same bank
PRE
Bank
Bank
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 59
UNIVERSITY OF MARYLAND
DRAM Evolution
Write-Ar ound in ESDRAM
(can second READ be this a ggressive?)
Command
Address
DQ
Cloc k
RowAddr
ColAddr
ValidData
ValidData
ValidData
ValidData
ACT READ
RowAddr
ColAddr
ValidData
ValidData
ValidData
ValidData
ACT WRITEPRE
ÒRegularÓ CAS-2 SDRAM, R/W/R to same bank, rows 0/1/0
Command
Address
DQ
Cloc k
RowAddr
ColAddr
ValidData
ValidData
ValidData
ValidData
ACT READ
RowAddr
ColAddr
ValidData
ValidData
ValidData
ValidData
ACT WRITE
ESDRAM, R/W/R to same bank, rows 0/1/0
PRE
Bank
Bank
RowAddr
ColAddr
ValidData
ValidData
ValidData
ACT READPRE
Bank
ColAddr
ValidData
ValidData
ValidData
ValidData
READ
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 60
UNIVERSITY OF MARYLAND
DRAM Evolution
Internal Structure of Vir tual Channel
Segment cac he is software-mana ged, reduces ener gy
$
Row Decoder
2Kb Segment
2Kb Segment
2Kb Segment
2Kb Segment
Bank A
Bank B16 ÒChannelsÓ
Input/OutputBuffer
DQs
Sel/Dec
(segments)
SenseAmps
2Kbit # DQs
Activate PrefetchRestore
ReadWrite
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 61
UNIVERSITY OF MARYLAND
DRAM Evolution
Internal Structure of F ast Cyc le RAM
Reduces access time and ener gy/access
t
RCD
= 15ns t
RCD
= 5ns
8M Array
13 bits
Sense Amps
8M Array
15 bits
Sense Amps
SDRAM FCRAM
(one clock)(two clocks)
Ro
w D
eco
der
Ro
w D
eco
der
(8Kr x 1Kb) (?)
ENEE 359aLecture/s 20-22
DRAM Systems
Bruce Jacob
University ofMaryland
ECE Dept.
SLIDE 62
UNIVERSITY OF MARYLAND
DRAM Evolution
Internal Structure of MoSys 1T -SRAM
. . .
. . .
. .
. . . . . .
addr
BankSelect
DQs
$
AutoRefresh