BLM FOR THE INJECTORS PROJECT LINAC4 PSB Linac4 Beam Coordination Committee - Meeting 33...
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BLM FOR THE INJECTORS PROJECT LINAC4 & PSB Linac4 Beam Coordination Committee - Meeting 33 (31/05/2012) Christos Zamantzas ([email protected])
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Outline System overview Installation overview Budget estimations Specifications Development planning BCC – 31/05/2012
Transcript of BLM FOR THE INJECTORS PROJECT LINAC4 PSB Linac4 Beam Coordination Committee - Meeting 33...
BLM FOR THE INJECTORS PROJECT LINAC4 & PSB
Linac4 Beam Coordination Committee - Meeting 33 (31/05/2012)
Christos Zamantzas ([email protected])
2
IntroductionThis project has undertaken the task to develop up-to-date
Beam Loss Monitoring Systems for the Injectors.
Mainly,
Build a generic, highly configurable and high-performing system Acquisition part to accept several detector types Use reprogrammable parts to target all injectors’ requirements
Team members:
BI/BL: M. Alsdorf, B. Dehning, W. Vigano, M. Kwiatkowski, C. Zamantzas
and support from: E. Effinger, J. Emery, G. Venturini, E. Nebot Del Busto
BI/SW: E. Angelogiannopoulos, S. Jackson, L. Jensen
[email protected] L4 BCC – 31/05/2012
3
Outline
System overview Installation overviewBudget estimationsSpecificationsDevelopment planning
[email protected] L4 BCC – 31/05/2012
SYSTEM OVERVIEW
6
Acquisition Crate
Acquisition module (BLEDP)Up to 8 modules with
8 channel each
Main panel • Ref. current Input• LEDs• Power switch
Control UnitLater version w/
advanced remote functions
[email protected] L4 BCC – 31/05/2012
Custom BackplaneSupport 64
connectors and relays for the input
channels and distribute signals
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Acquisition module (BLEDP)
Backplane connectionAnalogue inputs, power
and control SFP connectorsGigabit optical and/or
Ethernet links
FPGA Altera Cyclone IVJTAG connection
Local programming and diagnostics
Acquisition digitisation of 8
channels
Currently verifying version 2 of the printed circuit board
DPFC principle A status signal selects in
which branch of a fully deferential stage the input current is integrated.
Two comparators check the deferential output voltage against a threshold, whenever is exceeded, the status signal changes to the complementary value (0 ! 1 or 1 ! 0) and the input current is integrated in the other branch.
[email protected] 8L4 BCC – 31/05/2012
DPFC data processing
0 Time
counts
2 μs 2 μs 2 μs
ADC values
thhigh
thLow
The number of accumulated counts are combined with the ΔADC values to calculate the integrated loss over a 2 μs period.
Most of the operations are handled by the FPGA. That is, Defines start and stop of the acquisition period Keeps a count of the number of pulses occurred in the acquisition period, Clocks the ADC circuitries and makes differences of the recorded ADC values Finally, processes the data and provides the 2 μs integral per channel
L4 BCC – 31/05/2012
10
Acquisition principle (DPFC & DADC)The input channel circuit is able to measure current input from 10pA to 200mA.
The measurement of the current input is performed by two different techniques: 1) Dual Polarity Current to Frequency Converter (DPFC) used in the range 10pA to 30mA2) Direct ADC acquisition (DADC) used in the range 20.3µA to 200mA
No gain change required:The switch between the 2 ranges is managed by the FPGA.
• If the maximum DPFC counts is reached, the FPGA switches the circuit to the DADC mode.
• When the value of the DADC falls below a threshold, the FPGA switches the circuit to the DPFC mode.
• The sum of all parts is calculated in the FPGA and transmitted as a 2 us sample.
[email protected] L4 BCC – 31/05/2012
DPFC
DPFC
L4 BCC – 31/05/2012
Processing Electronics
Processing Mezzanine New design to match the acquisition modules 2 SFP modules (gigabit Optical links and Ethernet) Cyclone IV (150K logic elements) FPGA
Processing and triggering modules Standard BI card, i.e. VME64x
VME crates with BI custom backplane Broadcast of timing events to the modules Daisy-chain of beam permit signals Same as LHC system
L4 BCC – 31/05/2012
Processing Mezzanine (BLEPM)
2 SFP modules gigabit Optical links
and Ethernet
FPGA Cyclone IV 150K logic elements
Connectorsto the mainboard
JTAG connectionLocal programming
and diagnostics
INSTALLATION OVERVIEW
Cable choices overview Signal: Coaxial (double shielded) CKB50 HV cable: CBH50 Connectors/Plugs: custom-made triaxial
Prototypes should arrive in a couple of weeks
Machine # ch Signal cable HV cable Cable tray spare cables Comments
LINAC4 25 Coaxial (double shielded) single yes yes installation completed except connectors
PSB 116 Coaxial (double shielded) single no yes (ring) new cables requested for LS1
L4 BCC – 31/05/2012
was 48
Ionization Chamber
LINAC4 cabling
Screen of HV BNC is open on the IC side to assure there is no ground loop. Internal screen to shield low frequency noise (GND only on electronics side, IC is floating). External screen to shield high frequency noise.
enclosed in cable tray tube
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~ 200 m ~ 5 m~ 1 m
BNC
SMA
TRIAX
Connector Types:
CKB 50 BNCSMA
AcquisitionCard
(BLEDP) External Screen 2
Internal Screen 1
Signal
HV PowerSupply(~1500 V)
HV BNC
L4 BCC – 31/05/2012
Pictures of the installation
Rack will include: Acquisition crate Processing (VME) crate HV Power supply for the detectors User Interface to BIS (i.e. CIBU)
Separated enclosed cable tray
Metallic cable tube for the last few meters
Enclosed and extended front for cables and fibres
Fans on the rack top
Standard and Uninterrupted Power Supply connections
BUDGET ESTIMATIONS
Summary of budget needed
Estimate Budget * diffLINAC4 BLM 156,100 133,000 -23,100
PSBBLM 371,220 0 -371,220BLO 134,524 77,000 -57,524
TOTAL 661,844 210,000 -451,844
* Budget values for LINAC4 and PSB-BLO are from last EVMs* Budget values for PSB in the Injector Consolidation document is shared with PS and does not include cabling
Note: Latest version of the calculations can be found at: https://espace.cern.ch/project-blm-inj/Shared%20Documents/Budget.xlsx
LINAC4 calculation still close on estimate PSB calculation is estimated with new cables - average of 60m
BLM system: detectors assumed Ionisation Chambers and taken from the LHC spares BLO system: detectors are diamonds
L4 BCC – 31/05/2012
SPECIFICATIONS
Acquisition & Processing Synchronisation is required with the start of the cycle to
Perform calculation of integration periods and Schedule comparisons with their corresponding threshold values Record high frequency observation data Schedule the data readout and publish by the CPU
Synchronisation to be achieved by Use the Start of Cycle event received through the timing system. Dedicated timing card with broadcast in the backplane. Sync will be done at the processing level (i.e. 2 samples jitter between cards).
[email protected] 20L4 BCC – 31/05/2012
L4 BCC – 31/05/2012
Integration Periods
Continuously the processing electronics will calculate 4 integration period values for each channel: 2 s, 400 s, 1 ms and 1.2 s (full cycle)
implemented as moving sum windows in the hardware calculation refreshed at acquisition frequency
Compare with predefined thresholds Machine protection with hardware implementation
comparisons on each refresh Limit radiation levels with software implementation
comparisons at end of cycle See also next slide.
Calculate for each channel the maximum values recorded on each integration period during the cycle Publish them for the online displays and the long-term logging
Threshold ComparisonsHardware implementation part: All calculated integration period values, i.e from 2 s to 1.2 s, will be constantly checked against their
threshold values: 4 threshold values, one for each of the integration periods. Comparisons happen at the refresh period – that is, every 2 s In the case the measured values exceed those the beam permit signal will be removed for all users The blocked beam permit signal will be latched until an operator acknowledges.
The threshold values will be need to be set unique per channel: Each card will process 8 channels
Software implementation part: All maximum integration period values recorded on the cycle will be checked against a second set of
threshold values. The outputs will be used for repeated over threshold function Additional threshold values for the same integration periods will also be required. In the case found to be over threshold repeatedly n times it will be required to block that user’s injections. The blocked beam permit signal will be latched until an operator acknowledges. The repeat value n will be settable per monitor in the range of 1 to 16.
The threshold values will need to be unique per user and per channel: Each CPU will process 8 cards x 8 channels The information of the current user has to be obtained from the telegram per cycle -> dedicated timing card Memory for 32 users will be reserved.
[email protected] 22L4 BCC – 31/05/2012
Beam Permit Logic System [HW and/or SW] will block injections
i.e. “remove permit” if losses over threshold
System [SW] will remember if the user is allowed to have beam i.e. “give permit” if previous cycle for the user was ok (or previous interlocks were cleared)
The Beam Interlock Controller will be configured in the “Non-latch” mode. i.e. the system will need to follow timing and notify in advance.
Aiming to keep the maximum latency (from measurement to output) small HW: The target for the fast integration periods is ~ 5 μs SW: Block on next cycle
Only data from the current cycle need to be considered. Timing in the electronics essential (i.e. possible failure mode)
[email protected] 23L4 BCC – 31/05/2012
L4 BCC – 31/05/2012
Ambient Radiation MeasurementCalculate and log the ambient radiation measured at each cycle Processing electronics will provide two values:
total accumulated in the cycle (already described) and total accumulated with beam present
Subtraction of the two values in CPU Additional timing events to be used for the recording Values will come together with number of samples used in the recording to
allow accurate conversion to user-friendly units, i.e. Gy, Gy/s, … Publish values for the online displays and the long-term logging
L4 BCC – 31/05/2012
Evolution Over Time buffer Record detailed observation data
Publish on the online displays Log on demand
LINAC4: 2 s samples for 1 ms during beam presence
PSB: 1 ms samples for 600 ms during beam presence 2 s samples for 1 ms with adjustable start (aka Capture)
Readout and transmission window by CPU during beam-out period
Evolution & Capture functions
274
875
1200
0 Time [ms]
SoC SoC
Cycle n
275
LINAC4
2 μs integral x 500 samples
274
Cycle n+1
transmission windowrecording window
PSB
1 ms integral x 600 samples
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2μs integral x 500 samples [adjustable 1 ms window]
DEVELOPMENT PLANNING
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Documentation and Tracking Information and documents (SharePoint)
http://cern.ch/blm-inj Drawings, PCB schematics and Code (SVN)
https://svnweb.cern.ch/cern/wsvn/be-bi-bl/electronics/blminj/ Development tracking (JIRA)
http://issues.cern.ch/browse/BIBMJ
L4 BCC – 31/05/2012
PCB Development Acquisition module (BLEDP)
Prototype (ver. 2) currently under verification Adjustment of input filters Improvement of power-up sequence Ver. 3 planned for end of the year – after measurements completed
Acquisition Backplane (BLEBP) Prototype (ver. 1) completed verification Ver. 2 planned for November Better separation of signal and power lines
Processing mezzanine (BLEPM) Prototype (ver. 1) completed verification Ver. 2 next year – no major changes expected
Processing & Triggering module (BLEPT) Complete and produced
Production of (all remaining) PCBs expected Q3 2013 After validation of all parts and their interoperability
L4 BCC – 31/05/2012
Code development All interfaces developed and tested
High speed ADCs Digital potentiometers Gigabit optical links Power supply monitoring and controls Temperature and humidity sensors Unique module serial number etc …
Firmware can be loaded and stored on the on-board flash memories of all FPGAs
First version of the VME interface for the Intel CPU 64bit Multiplexed BLock Transfer [MBLT]
L4 BCC – 31/05/2012
First results with prototype
Logic analyser running in the FPGA, i.e. SignalTap
Records the “positive” and “negative” pulses Records the ADC values Next step: add the combination algorithm, etc.
Developing the DPFC data processing algorithm:
L4 BCC – 31/05/2012
System for Beam Measurements
Add a gigabit Ethernet module and connect to the network Develop the TCP/IP and UDP stacks in the FPGA firmware -> NIOSII softcore Develop a server to be included in the FPGA -> compiled C++
accept commands, prepare data requested and transmit Develop a client application in Java
send commands, store and display data
• First versions ready.• atm, one channel
processed data only.
• Expected for measurements in PS end of September
FPGA & FESA Real-Time software Definition of the memory map
CPU in readout simulation mode Start development of driver, RT software, etc. Updated version of memory map (LINAC4)
Develop VME block transfer Needed for extracting all data requested First version of (M)BLT - end of September
Test-bench: VME crate with bare carrier boards Intel CPU Firmware with dummy vectors Timing First version of RT could start being implemented
[email protected] 33L4 BCC – 31/05/2012
SUMMARY
Summarising Reliable tunnel installation
Monitors will be Ionisation Chambers High immunity to EMI with special cables, connectors and enclosed cabletrays
High performance acquisition electronics Automatic range selection Dynamic range = 1011
In-system calibration mode (will have remote execution in the future) Modular processing electronics
High availability of resources (~350’000 Logic Elements) Embedded bidirectional gigabit links Additional gigabit Ethernet link (for dedicated measurements)
Production and planning well defined and on schedule Six new printed circuit boards under design
Second iteration of the PCBs currently under validation – no blockers found Five FPGAs under design
All interfaces implemented Working currently on the processing parts and on adding speed improvements Main processing and VME server to start on September
Test-benches for verification, software development and measurements All parts available in the lab Beam measurements in October
[email protected] 35L4 BCC – 31/05/2012
THANK YOU
RESERVED SLIDES
General InformationUseful information on the LINAC4 and PSB requirements can be found in the
following links:
Beam Interlock Specifications for LINAC4, Transfer Lines and PS Booster with LINAC4 [https://edms.cern.ch/document/1016233/0.3]
Notes on the Beam Loss Monitoring System for LINAC4 and PSB [link] Description of all important info, specific implementations, etc Documents under preparation. Meeting notes
Summary table of requirements [link] Result from discussions the BL and SW sections had with OP
[email protected] 38L4 BCC – 31/05/2012
Prices used for the estimation
Monitor
IC 1500 SEM 0
ACEM 0 LIC 0
Module
Mezzanine (prototype) 50000 new development; will be split between projectsCarrier (production) 2500 VME64x re-production
Mezzanine (production) 400 Processing 2900 not including protyping costs
prototype 100000 new development; will be splitted between projects
production 1500 price per card to produceMezzanine 300 assuming gigabit link
Acquisition 1800 not including protyping costs
Combiner & Survey 2000 needs re-production
Acquisition crate
chassis 500 backplane 1000
power supply 300 Complete crate 1800
Processing crate
Complete crate (renovation) 10000 In the renovations the CPU is paid by CO
cpu 3000
Complete crate (new construction) 13000 In a new construction need to add the CPU cost
Rack 12400 Value estimated from LINAC4 request by JCG
Installation
signal cable 20 price per metre for double shielded coaxialHV cable 5 price per metre
HV power supply 1100 (730 Euro) should add as many as possible for better measurements
Cable patch & Signal boxes 208
Cabling and boxes for 1 BLM:HV cabling: Plug 2 * 33.0CHF/p ; cable 1CHF/m * 10 m -> total = 76CHF/ cableBNC cabling: Plug 2 * 16CHF/p ; cable 1CHF/m * 10 m -> total = 42CHF/ cable Box: 45 CHF/p; HV Socket 3 * 11.0CHF/p ; BNC Socket 2*6CHF/p -> 90CHF/P208CHF/BLM
L4 BCC – 31/05/2012
