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    A Novel Genetic Algorithm for the Automated Design of

    Performance Driven Digital Circuits: A Critical Appraisal

    Olla A. Ashour

    Department of Mathematics, Faculty of Science, Alexandria University, Alexandria, Egypt

    Email: olla.ashour@gmail.com

    Abstract

    [Critical abstract of] Ben. I Hounsell and Tughrul Arslan. Novel genetic algorithm for the automateddesign of performance driven digital circuits. Proceedings of the 2000 Congress on EvolutionaryComputation, 1(1), 601-608, July 2000.

    This research describes the design of complex circuit design using genetic algorithms by takingconsideration important constraints mainly area (or number of circuit components) and timing whichaffect the performance of the circuit while directly evolving and evolving circuits in a hardwaredescription language (HDL) that allows for easy circuit synthesis and simulation. The results of this studyallow for the design of any complex circuits by only providing to the genetic algorithm a Boolean tablewhile easily simulating the structure of the complex circuit designed and in addition providing efficientand high-performance circuits.

    The paper will interest circuit designers and those developing sub-micron technologies as todays silicontechnologies take in consideration performance as a factor more than other any other factor. The papercould be a reading material for courses related to machine learning, circuit designs, and artificial

    intelligence.The paper is informative and organized in an overall well structure. In order to improve the paperspresentation, purpose and justification further figures especially of the circuit structures, citations ofclaims, and additional criteria in the performance factors and the development of the genetic algorithmcould have been taken in consideration during the research. In addition a more detailed explanation of theresults with more statistics and figures. The bibliography could be extended slightly, to include a fewmore old and recent references.

    1 Introduction1.1 About the Authors

    The paper Novel Genetic Algorithm for the Automated Design of Performance Driven DigitalCircuits is co-written by Ben. I Hounsell and Tughrul Arslan of the Department of Electronics andElectrical Engineering, University of Edinburgh, Mayfield Rd, Edinburg, Scotland and was presented inthe Proceedings of the 2000 Congress on Evolutionary Computation in 16-19 July 2000 at La Jolla, CA,USA.

    As of the year 2000, the author Tughrul Arslan published more than 50 articles in the fields ofAnalogue and Digital Circuit Design using traditional CAD tools and evolutionary algorithms in order to

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    produce high performance circuits which were mostly published in either the IEEE Journal or presentedin many International conferences/proceedings.

    Professor Arslan was an Associate Editor for the IEEE Transactions on Circuits and systems I andIEEE Transactions on Circuits and Systems II. He is a member of the IEEE CAS Committee on VLSISystems and Applications and is involved in the organization of numerous conferences. Recently he was

    the general chair for the IEEE NASA/ESA conference on Adaptive Hardware and Systems (AHS) and theECSIS Bio-inspired, Learning, and Intelligent Systems for security Symposium (BLISS). He has beeninvited as a keynote speaker to a number of international conferences [5].

    On the other hand, little information is available on Ben. I Hounsell, but as of 2000, only twoknown papers [1, 7] have been found published based on search results from IEEE, Springer and GoogleScholar in which one of the papers is the paper under critical appraisal here.

    1.2 Purpose and Significance of WorkDue to advances in silicon technology, new methods of circuits design have to be researched in

    order to design circuits with optimal performance. Traditionally in order to design a digital circuit, itrequires that designers know large collections of domain-specific rules in order to design circuits based ona Boolean logic table to implement certain functionality.

    Generally, in order to implement a digital circuit, a 3 step process is involved. Logicalspecification transformation of circuit onto a form suitable for the target technology, optimization ofdesign with respect to a number of user defined constraints and finally to map the circuit design ontotarget technology in order to test it.

    But the process requires that designers know large collection of domain-specific rule whichhinders the design process as it depends on the training and experience of the designer and the amount of

    domain-specific knowledge known to the designer so hence restricting the design. So an alternative has tobe found.

    Also traditionally for designers during optimization of designs, the circuits evolved beforeoptimization must be each tested against a fitness function and it is not feasible to transfer the circuitdirectly onto silicon for evaluation( intrinsic evaluation) every time a design is improved (evolved) beforeit reaches optimal level, hence, it is time consuming and wastes resources.

    So an alternative approach was found namely Evolvable Hardware (EHW) which unliketraditional techniques which employ top down design methodology in which complex systems are brokendown into small sub-systems and assigned to a number of design groups, evolvable hardware on the other

    hand approaches the design problem as a whole system generating a black box of the completed circuit,i.e. Bottom up design methodology. The only information that is presented to the design engineer is aBoolean logic table and the evolutionary algorithm can produce a set of possible circuit designs for thespecified functionality of the Boolean logic table which is later evolved until the constraints imposed onthe algorithm are met.

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    In addition, circuit evaluation can be done through software simulation (extrinsic evaluation) asopposed to intrinsic evaluation which allows evolved circuits to be easily examined and tested once asolution has been found.

    Hence, evolvable hardware considers the automated design of digital systems using both software

    simulation and programmable hardware technologies (which implements the optimized circuit onto thespecific silicon technology) [1].

    The paper presented describes the above technologies in the utilization of circuit design i.e.evolvable hardware and extrinsic evaluation as due to the increased growth of computing devices it hasbecome inevitable to design complex circuit designs which cannotbe limited by the designers knowledgeof domain specific rules.

    The above methodologies will help create very complex circuits that were not possible before andto evolve circuits larger than those detailed with only having the knowledge of a Boolean table and toprovide the optimal circuits based on the constraints imposed by the design. So hence a new advancement

    in circuit design specifically in designing computing devices that was not possible before is introduced intheir work.

    Fig 1 Provides a Summary of the Process [4].

    The paper is mainly targeted for DSP (Digital Signal Processing) applications and VLSI (VeryLarge Scale Integrated) circuit designers. In addition other audiences interested in Genetic Programmingand its various utilizations in many scientific fields can benefit from the use of GA in a specific researchas circuit design.

    In the design of VLSI (Very Large Scale Integrated) circuits, there are many concerns for whichVLSI designers take in consideration such as area, performance, cost, reliability and power [2]. So, one ofthe most important significance of this paper is that with compared to other research papers in the samefield [6, 8, 9] which used evolvable hardware or specifically evolutionary algorithms in designing circuits,the authors incorporated performance constraints that were not utilized in previous research during theoptimization (the fitness of a circuit undergoing evaluation) process in namely i.e. timing and areaconstraints.

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    Additionally, the authors created a novel environment for which to simulate and test evolvedcircuits and later only implement the optimized circuit directly onto the hardware using a hardwareprogrammable language thus effectively designing novel complex circuits and reducing time andresources in the design process optimization.

    Compared to [10] in which the novel environment used is a Java-based tool using FPGAs (FieldProgrammable Gate Array) to implement legal configurable circuits which are neither temperature,voltage, nor silicon dependent , Arslan and Hounsell created a novel environment in which theenvironment termed Virtual chip is a combination of C routines and VHDL (Very High Speed IntegratedHardware Description Language) which based on their citied work is one of the two dominant languagesused in describing digital electronic systems.

    Furthermore, this paper compared with previous work of author Tughrul Arslan concentrates onthe timing and area constraints where notably he previously worked more on power as a more importantconstraint in circuit design in both traditional methods such as Circuit Aided Design(CAD) and in themore innovative evolutionary algorithms methods specifically Genetic Algorithms.

    However, Both Tughrul Arslan and Ben.I Hounsell worked together on the paper NovelEvolvable Hardware Framework for the Evolution of High Performance Digital Circuits [7] presentedduring the duration of 8-12 July 2000 in a different proceeding in which they developed the novelenvironment i.e. Virtual Chip and used the Genetic Algorithm in exactly the same way, the onlydifference is that in [7] they used only a 3-b