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Transcript of BBCOM_SDH
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Lars Dittmann, [email protected]
Synchronization problem
Multiplexing of N channels must adopt to
highest rate (N x highest rate - rather thansum)
Clock distribution depending on local
oscillators and network structure
Must incorporate case of failure
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Multiplexing
f1f2f3
f4
f5f6
f8
f7
f9f10
f11
f12f13f14f15
f16
4 x maxf
4 x maxf
4 x maxf
4 x maxf
4 x maxf
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Net synchronization
1 2 3n 1 2 3 n 1 2 3 n1 2 3 n
core network
node
access
node
????
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Framing in circuit switching
11 121097 865 19 20181715 161413 27 28262523 2422213 42131 03029 3 42131 03029
125 sec
Basic PDHframingstructure
Destination determined by frame possition
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Lars Dittmann, [email protected]
PDH Multiplex hierarchy
Multiplex hierarchy, European standard
System Data speed, Mbit/s Number of channels
DS-1E 2,048 30
DS-2E 8,448 120
DS-3E 34,368 480
DS-4E 139,264 1920DS-5E 564.992 7680
(4)
DS-1E
(4)
DS-2E
(4)
DS-3E
M34E
(4)
DS-4E
M45E
DS-5EM23E
M12E
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Plesiochronous add and drop
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Lars Dittmann, [email protected]
The history of SONET/SDH
SONET proposed standard by BELLCORE at thetime when ITU/CCITT was working on global
standard
A (simplified) version adopted by ITUG.707/708/709 now one standard G.707
Still minor differences in SDH and SONET - NOTjust plug and play.
Now a general accepted standard - even non-SDHnetworks are using SDH-framing
Simplified (not all function fields supported)
versions in datacom e.g. 10GE, DPT/SRP etc.
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Lars Dittmann, [email protected]
SDH in brief
SDH is synchronous, i.e. all elements use one clock as reference.
SDH provide simpel multiplexing and allow direct access
to lower level signals.
SDH defines optical standards => midspan meet possible
SDH can be introduced into existing systems
SDH is prepared for carrying many signal types such as:
ETSI-PDH, ANSI-PDH and ATM.
SDH include management channels embedded in the signal.
SDH enable the possibility of a centralized network control.
SDH advantages
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SDH network structure
S D H le v e l D a t a s p e e d
S T M -1 1 5 5 5 2 0 k b /s
S T M -4 6 2 2 0 8 0 k b /s
S T M -1 6 2 4 8 8 3 2 0 k b /s
S T M -6 4 9 9 5 3 2 8 0 k b /s
Regionalnetwork
Regional
network
Regional
network
Localnetwork
Localnetwork
Localnetwork
Localnetwork
Localnetwork
Localnetwork
STM-1
STM-1
STM-1
STM-1STM-1
STM-1
STM-4/STM-16
STM-16/STM-64
core network STM-4/STM-16
STM-4/STM-16
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SONET vs. SDH
SONET = ANSI (American standard)
SDH = International Standard SDH basic unit = STM-1 = 155 Mbit/s
SONET basic unit STS-1 = OC-1 = 51 Mbit/s
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SDH og PDH
Customer
SDH-island
PDHnetwork
PDHnetwork
High speedSDH-line
Customer
SDH-island
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Network element 1
SDXCsynchronous digital cross connect
SDXC STM - n
(m
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Network element 2
ADMadd / drop multiplexer
ADM STM - n
(m
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Network element 3
Muxmultiplexer
Multiplexer STM - n
STM - m
(m
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Network element 4
Regregenerator
Regenerator STM - nSTM - n
Regenerate the signalSignal supervision
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Layered structure
T1816750-92/d11
Circuit layer networks
VC-11 VC-12 VC-2 VC-3
VC-3 VC-4
Multiplex section layer
Regenerator section layer
Physical media layer
Circuit
layer
Lower
order
pathlayer
Path
layer
SDH
transport
layers
Higher
orderpath
layer
Section
layerTransmission
media
layer
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SDH structure
Path layer:low-order pathhigh-order path
Transmission medium layer:Multiplexer sectionRegenerator sectionPhysical medium (e.g. fiber)
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Overhead
Overhead is generated at:
Regenerator section
Multiplekser section End-to-end high-order path
End-to-end low-order path
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SDH
frame structure
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Lars Dittmann, [email protected]
Multiplexing structure
European multiplexing of low-order signals into a SDH signal
Multiplexed TUs
Pointer added
Overhead added
Input container
Overhead added
Pointer added
Multiplexed AUs
Overhead added
F t i 1 t STM N
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From container 1 to STM-N
T1819910-93/D03
VC-1
TU-1
TUG-2
TUG-3
VC-4
AU-4
AUG
STM-N
Container-1
VC-1 POH Container-1
VC-1
VC-1VC-1
TU-1 PTR
TU-1 PTRTU-1 PTR
TUG-2 TUG-2
VC-4 POH TUG-3 TUG-3
AU-4 PTR VC-4
VC-4AU-4 PTR
SOH AUG AUG
Logical association
Physical association
PointerPTR
BIP 8 l l i
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BIP-8 calculationCalculation of a BIP-8
Bit-stream : 1011 0010 0100 1101 1011 0011 1110 0101
BIP-8 => In a group of bits:
Number of 1 even => parity bit 0Number of 1 odd => parity bit 1
T i i
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Transmission system
TX
Site A
RX
RX
Site C
TX
RX TX
Site B
TX RX
If site B have problems with a signal from site A
Upstream to A
Remote Defect Indication (RDI)former (Far End Receive Failure (FERF))
Remote Error Indication (REI)former (Far End Block Error (FEBE))
Downstream to C Alarm Indication Signal (AIS) of appropriate type
O h d
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Overhead
European multiplexing of low-order signals into a SDH signal
Multiplexed TUs
Pointer added
Overhead added
Input container
Overhead added
Pointer added
Multiplexed AUs
Overhead added
Multiplexed AUGs
STM N f
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STM-N frame
T1819950-93/D07
4
3
1
9
5
270 Ncolumns (bytes)
9 N 261 N
STM-N payload 9 rows
Section overheadSOH
Section overheadSOH
Administrative unit pointer(s)
Transmission From upper left corner to lower right corner. One row at a time
Each byte is transmitted with most significant bit first
Frame Repeated every 125 s => frame rate 8 kHz Each byte correspond to 64 kbit/s
STM 1 S ti h d (SOH)
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STM-1 Section overhead (SOH)
Regenerator Section Overhead (RSOH) terminated at regenerators
Multiplexer Section Overhead (MSOH) terminated at multiplexers
Regerator section overhead
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Regerator section overhead
A1, A2 Framing bytes. A1=hex F6, A2=hex 28.C1/J0
STM-1 Identifier / Section trace.(16-byte frame)B1 8-bit byte interleaved parity (BIP-8)
check sum on entire STM-1 (after scrambling)and stored in the next frame (before scrambling).
E1 Order wire-64 kbit/s voice channel.F1 User channel, not yet defined.D1-D3
Data communication channel (192 kbit/s)for operation and management of regene-rators.
Multiplexer section overhead
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Multiplexer section overhead
B2 3 bytes (BIP-24)check sum. Calculated onthe entire STM-1 (except RSOH) and inser-ted in the next frame.
K1,K2
Mainly for signaling related to multiplexsection protection and maintenance.
D4-D12 Data Communication Channel (576 kbit/s)
for operation and management of multi-
plexers.S1 Synchronization state.M1 Section REI (FEBE). Number of B2
bit errors detected by far end in the lastframe. Range [0-24*N] for STM-N, buttruncated at 255.
E2 Order wire for multiplex section.
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Low-order path overhead
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Low order path overhead
VC-11, VC-12, VC-2 pathoverhead : V5, J2, N2 and K4.BIP-2 2-bit interleaved check sum calculated on
the total VC-n, stored and inserted intothe next VC-n.
REI (former FEBE) Remote Error Indication. Bit which shows
if any BIP-2 errors was found in the lastreceived frame in the far end.RFI Remote Failure Indication. A failure is a
defect which persists beyond the timeallocated for protection mechanisms.
RDI (former FERF)
Remote Defect Indication. Bit which showif the far end has detected a large problem.
J2 : Low-order path Access Point Identifier.
N2 : Tandem Connection MonitorK4 : (b1-b4) Automatic Protection Switching.
(b5-b7) Reserved.(b8) Spare
BIP-2 REI RFI Signal Label RDI
1 2 3 4 5 6 7 8
Virtual Container path REI coding: 0 = 0 errors
1 = 1 or more errors
Virtual Container path Signal Label coding :
b5 b6 b7 Meaning
0 0 0 Unequipped or supervisory-unequipped
0 0 1 Equipped - non-specific (Note 1)
0 1 0 Asynchronous
0 1 1 Bit synchronous (Note 2)
1 0 0 Byte synchronous
1 0 1 Reserved for future use
1 1 0 Test signal, O.181 specific mapping (Note 3)
1 1 1 VC-AIS (Note 4)
NOTES
1 Value "1" is only to be used in cases where a mapping code is not defined in the above table. For
interworking with old equipment (i.e. designated to transmit only the values "0" and "1"), the following
conditions apply:
For backward compatibility, old equipment shall interpret any value received other than "0" as an
equipped condition.
For forward compatibility, when receiving value "1" from old equipment, new equipment shall not
generate a Signal Label Mismatch alarm.
2 In the case of a VC-12, the code "3" shall, for backward compatibility purposes, continue to be
interpreted as previously defined even if the bit synchronous mapping of 2048 kbit/s signal is not
defined anymore.
3 Any mapping defined in Recommendation O.181 which does not correspond to a mapping defined in
Recommendation G.707 falls in this category.
4 Only for networks supporting the transport of Tandem Connection signals.
V5=>
FIGURE 9-7/G.707 (03/96)
VC-2/VC-1 POH V5 byte
Overhead summary
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Overhead summary
Regenerator section Multiplekser section
End-to-end high-order path
End-to-end low-order path
TU-pointer
AU-pointer
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SDH
pointers
Pointers
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Pointers
European multiplexing of low-order signals into a SDH signal
Multiplexed TUs
Pointer added
Overhead added
Input container
Overhead added
Pointer added
Multiplexed AUs
Overhead added
Multiplexed AUGs
Pointers
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Pointers
Pointers are used to allow a flexible and dynamic alignment of VC-nswhich include compensation for phase and frequency differences betweentwo SDH net.
There are two pointer levels for 2Mb/s signals in a VC-4.
AU-4 pointer
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AU 4 pointer
1
2
3
4 H1
5
6
7
8
9
H3 H3 H3 0 - - 1
87
- -- 86
1
2
3
4
5
6
7
8
9
-
- -521
- -782
- -860
522 -
. . . .
. . . .
. . . .
. . . .
. . . .
. . . .
H2Y
1 2 3 4 5 6 7 8 9 10 270
125 s
250 s
H1 H3 H3 H3H2YY
Y 1* 1*
1* 1*
T1819190-92/d12
AUG
Negative justificationopportunity (3 bytes)
Positive justification
opportunity (3 bytes)
All 1s byte
1001SS11 (S bits are unspecified)
1*
Y
AU-4 pointer offset numbering
261*9/3 = 783 = 0 to 782
N N N N S S I D I D I D I D I D
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
H1 H2 H3
T1518180-95
10 AU-4, AU-3, TU-3
ID
N
IncrementDecrement
New data flag
Negative
justificationopportunity
Positive
justificationopportunity
Negative justification
Invert 5 D-bits
Accept majority vote
SS bits AU-n/TU-ntype
Concatenation indication
1001SS1111111111 (SS bits are unspecified)
Positive justification
Invert 5 I-bits
Accept majority vote
NOTE The pointer is set to all "1"s when AIS occurs.
10 bit pointer value
New data flag
Enabled when at least 3 out of 4 bits match "1001"
Disabled when at least 3 out of 4 bits match "0110"
Invalid with other codes
Pointer value(b7-b16)
Normal range is:
for AU-4, AU-3: 0-782 decimal
for TU-3: 0-764 decimal
FIGURE 8-3/G.707 (03/96)
AU-n/TU-3 pointer (H1, H2, H3) coding
AU-4 pointers
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AU 4 pointers
1
2
3
4 H1
5
67
8
9
H3 H3 H3 0 - - 1
87
- -- 86
1
2
3
4
5
6
7
8
9
-
- -521
- -782
- -860
522 -
. . . .
. . . .
. . . .
. . . .
. . . .
. . . .
H2Y
1 2 3 4 5 6 7 8 9 10 270
125 s
250 s
H1 H3 H3 H3H2YY
Y 1* 1*
1* 1*
T1819190-92/d12
AUG
Negative justificationopportunity (3 bytes)
Positive justificationopportunity (3 bytes)
All 1s byte
1001SS11 (S bits are unspecified)
1*
Y
AU-4 pointers
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AU 4 pointers
N N N N S S I D I D I D I D I D
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
H1 H2 H3
T1518180-95
10 AU-4, AU-3, TU-3
I
DN
Increment
DecrementNew data flag
Negative
justification
opportunity
Positive
justification
opportunity
Negative justification
Invert 5 D-bits
Accept majority vote
SS bits AU-n/TU-ntype
Concatenation indication
1001SS1111111111 (SS bits are unspecified)
Positive justification Invert 5 I-bits
Accept majority vote
NOTE The pointer is set to all "1"s when AIS occurs.
10 bit pointer value
New data flag
Enabled when at least 3 out of 4 bits match "1001"
Disabled when at least 3 out of 4 bits match "0110"
Invalid with other codes
Pointer value(b7-b16)
Normal range is:
for AU-4, AU-3: 0-782 decimal
for TU-3: 0-764 decimal
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Possitive adjustment
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Possitive adjustment
43
1
5
9
500 s
375 s
250 s
125 s
H3H3H3H2H1
43
1
5
9
H3H3H3H2H1
4
3
1
5
9
H3H3H3H2H1
43
1
5
9
H3H3H3H2H1
1 2 3 4 5 6 7 8 9 10 270
Y Y 1* 1*
Y Y 1* 1*
Y Y 1* 1*
Y Y 1* 1*
n 1
n 1
n 1
n 1
n n n n+ 1, n+ 1
n n n n+ 1, n+ 1
n n n n+ 1, n+ 1
T1819220-92/d15
AUG
n n n n+ 1, n+ 1
Pointer value (n+ 1)
Pointer value (I-bits inverted)
Pointer value (n)
Positive justification bytes (3 bytes)
All 1s byte
1001SS11 (S bits are unspecified)
Start of VC-4
Frame 1
Frame 2
Frame 3
Frame 4
1*
Y
Negative justification
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g j
43
1
5
500 s
375 s
250 s
125 s
H3H3H3H1
43
1
5
9
H3H3H3H1
43
1
5
9
H1
43
1
5
9
H3H3H3H1
1 2 3 4 5 6 7 8 9 10 270
9
Y Y 1*1*
Y Y 1*1*
Y Y 1*1*
Y Y 1*1*
AUG
H2
H2
H2
H2
n n n n+ 1, n+ 1n 1
n n n n+ 1, n+ 1n 2, n 1, n 1, n 1
n n n n+ 1, n+ 1n 2 n 1, n 1, n 1
n n n n
+ 1,n
+ 1
T1819240-92/d17
n
2n
1,n
1,n
1Frame 4
Frame 3
Frame 2
Frame 1
Pointer value (n 1)
Pointer value (D-bits inverted)
Pointer value (n)
Negative justification bytes (data)
All 1s byte1001SS11 (S bits are unspecified)
Start of VC-4
1*Y
TU-12 Pointer-1
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XXXXXX00
XXXXXX01
XXXXXX10
XXXXXX11
V1
V2
V3
V4
V5
500 s
375 s
250 s
125 s
26 35 107
26 35 107
26 35 107
26 35 107
104 140 428
T1518250-95
J2
N2
K4
TU-n VC-n
VC-11 VC-12 VC-2
State ofH4 byte
VC capacity (byte/500 ms)
TUVCV1V2V3V4
Tributary unitVirtual containerVC Pointer 1VC Pointer 2VC Pointer 3 (action)Reserved
NOTE V1, V2, V3 and V4 bytes are part of the TU-n and are terminated at the
pointer processor.
FIGURE 8-10/G.707 (03/96) Virtual Container mapping in multiframed Tributary Unit
N N N N S S I D I D I D I D I D
00
01
11
V1 V2
V1
V2
V3
V4
T1518260-95
PTR1
PTR2
TU-11
TU-2
TU-12
Zero pointer offset location
Negative justification opportunity
Positive justification opportunity
PTR3 (action)
Reserved
(S bits specify size)
10-bit pointer value
10-bit pointer value
10-bit pointer value
Negative justification
Invert 5 D-bits
Accept majority vote
Positive justification
Invert 5 I-bits
Accept majority vote
Concatenation indication
1001SS11111111 (SS bits are unspecified)
NDF
I IncrementD DecrementN New Data Flag
New Data Flag Enabled when at least 3 out of 4 bits match "1001" Disabled when at least 3 out of 4 bits match "0110" Invalid with other codes
Pointer value
Normal range is:
for TU-2: 0-427 decimal
for TU-12: 0-139 decimal
for TU-11: 0-103 decimal
NDF
NDF
FIGURE 8-11/G.709 (03/96) TU-2/TU-1 pointer coding
V1
105
....
139
V2
0
....
34
V3
35
....
69
V4
70
104
....
TU-12
TU-12 Pointer-2
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H4(00)
H4(01)
H4(10)
H4(11)
H4(00)
T1518280-95
(V4)
PTR (V2)
PTR (V3)
(V4)
PTR (V1)
VC-3/VC-4 POH
VC-3/VC-4 payload
VC-3/VC-4 payload
VC-3/VC-4 payload
VC-3/VC-4 payload
VC-3/VC-4 payload
9row
In H4 (XY), XY represent bits 7 and 8 of H4
FIGURE 8-13/G.707 TU-1/2 500 s multiframe indication using H4 byte
H4 bits1 2 3 4 5 6 7 8 Frame N Time-------------------------------------------------------------
X X X X X X 0 0 0 0
X X X X X X 0 1 1
X X X X X X 1 0 2
X X X X X X 1 1 3 500 s TU-n multiframe
X undefined content
FIGURE 8-14/G.707
Tributary Unit multiframe indicator byte (H4) coding sequence
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SDH
mapping and multiplexing
Multiplexing
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p g
European multiplexing of low-order signals into a SDH signal
Multiplexed TUs
Pointer added
Overhead added
Input container
Overhead added
Pointer added
Multiplexed AUs
Overhead added
Multiplexed AUGs
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STM-N pointers
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1 9
1 261
1 9
1 261
N 9 N 261
123...N123...N
T1518050-95
123 ... N
123...N123...N
AUG AUG
RSOH
MSOH
STM-N
#1 #N
STM-n Section Overhead (SOH)
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STM-4 overhead
Some bytes are repeated 4 times (for STM-4) and others only show once.
And in the latter case the byte from the first STM-1 is used.
The overhead is 36 bytes long for STM-4, but 1 byte is still 64 kbit/s.
Multiplexing of TUs 1
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TUG-3 VC-4
AA B CA B C A B CA B C
74 5 61 2 3 108 9 261
. . . .
1 86 1 86 1 86
TUG-3(A)
TUG-3(B)
TUG-3(C)
T1819120-92/d05
FIGURE 2-4/G.709
Multiplexing of three TUG-3s into a VC-4
Fixed stuff
VC-4 POH
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Mapping
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European multiplexing of low-order signals into a SDH signal
Multiplexed TUs
Pointer added
Overhead added
Input container
Overhead added
Pointer added
Multiplexed AUs
Overhead added
Multiplexed AUGs
Mapping
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In the SDH note following mappings are described :
140 Mbit/s PDH => C-4 => VC-434 Mbit/s PDH => C-3 => VC-3 => TU-3 => TUG-32 Mbit/s
2 Mbit/s can be mapped into C-12 using 3 metods:
Asynchronous (eg. PDH signals)
Bit-synchronous (not framesynchronous) (not in 03/96)Byte- synchronous (frame and speed synchronous)
2 ways of operation are defined:
Floating mode (pointers are used)Locked mode (no pointers) (not in 03/96)
Multiframed TU-12
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VC-12 mapped into
a multi-frame TU-12
TU-12 multiframe indikation
H4(00)
H4(01)
H4(10)
H4(11)
H4(00)
T1819300-92/d24
VC-3/VC-4 POH
VC-3/VC-4 payload
VC-3/VC-4 payload
VC-3/VC-4 payload
VC-3/VC-4 payload
VC-3/VC-4 payload
9row
FIGURE 3-13/G.709
An example of TU-1/2 multiframe indication using H4 byte
(the case of 500 s multiframe)
TU PTR (V1)
TU PTR (V2)
TU PTR (V3)
TU PTR (V4)
TU PTR Tributary unit pointer
TU PTR (V4)XXXXXX00
XXXXXX01
XXXXXX10
XXXXXX11
V1
V2
V3
V4
V5
500 s
375 s
250 s
125 s
26 35 107
26 35 107
26 35 107
26 35 107
104 140 428
T1518250-95
J2
N2
K4
TU-n VC-n
VC-11 VC-12 VC-2
State ofH4 byte
VC capacity (byte/500 ms)
TU
VCV1V2V3V4
Tributary unit
Virtual containerVC Pointer 1VC Pointer 2VC Pointer 3 (action)Reserved
NOTE V1, V2, V3 and V4 bytes are part of the TU-n and are terminated at the
pointer processor.
FIGURE 8-10/G.707 (03/96) Virtual Container mapping in multiframed Tributary Unit
Asynchronous
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D Data bitO Overhead (8 bit)C Justification control (6 bit)S Justification possibility (2 bit)
R Fixed stuff J2 * Low order path traceN2 * Tandem Connection MonitoringK4 * Automatic Protection Switching
Additional RDI information
1023 databit / 500 s
Used e.g. for PDH signals
* From ITU-T G707 (03/96)
2 Mbit/s mapping - asynchronous
T1523020-96
V 5
R R R R R R R R
R R R R R R R R
J 2
C1 C2 O O O O R R
R R R R R R R R
N 2
R R R R R R R R
K 4
C1 C2 R R R R R S1
S2 D D D D D D D
C1 C2 O O O O R R
R R R R R R R R
32 bytes
32 bytes
32 bytes
31 bytes
140bytes
Data bit
Fixed stuff bit
Overhead bit
Justification opportunity bit
Justification control bit
D
R
O
S
C
FIGURE 10-8/G.707 Asynchronous mapping of 2048 kbit/s tributary
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Asynchronous 140 Mbit/s
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T1518350-95
J1
B3
C2
G1
F2
H4
F3
K3N1
5
1
3
20 blocks of 13 bytes
270 bytes
261 bytes
VC-4
AU-413 bytes1 byte
SOH
SOH
AU-4 PTR
STM-1
VC-4POH
PTR Pointer
FIGURE 10-2/G.707 (03/96)
Multiplexing of VC-4 into STM-1 and
block structure of VC-4 for
asynchronous mapping of 139 264 kbit/s
W X Y Y Y
Y YX Y X
YY
YY
W
X
Y
Z
Z
YX
X
Y
Y
T1522990-96
1
96 D 96 D 96 D 96 D 96 D
96 D 96 D 96 D 96 D 96 D
96 D 96 D 96 D 96 D 96 D
96 D 96 D 96 D 96 D 96 D
DDDDDDDD
CRRRRROO
RRRRRRRR
DDDDDDSR
12 bytes
POH
Data bit
Fixed stuff bit
Overhead bit
Justification opportunity bit
Justification control bit
NOTE This figure shows one row of the nine-row VC-4 container structure.
D
R
O
S
C
FIGURE 10-3/G.707 (03/96)
Asynchronous mapping of 139 264
kbit/s tributary into VC-4
Mapping of ATM cells
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J1
B3
C2
G1
F2
H4
F3
K3
N1
ATM Cell
53 octets
....
....
VC-4/VC-3
VC-4/VC-3 POH
J1
B3
C2
G1
F2
H4
F3
K3
N1
ATM Cell
53 octets
....
VC-4-Xc
VC-4-Xc POH
FixedStuff
X-1 X x 260 bytes
....
Mapping ATM cellsinto a VC-4
Mapping ATM cells intoa concatinated VC-4
(VC-4-Xc)
ATM bytes are alignedCells may cross frames
Optical standards 1
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Application Intra-Inter-office
officeShort-haul Long-haul
Source nominalwavelength (nm)
1310 1310 1550 1310 1550
Type of fibre Rec. G.652 Rec. G.652 Rec. G.652 Rec. G.652 Rec. G.652Rec. G.654
Rec. G.653
Distance (km)a) 20 15 40 80
STM-1 I-10 S-1.10 S-1.20 L-1.10 L-1.20 L-1.30
STM level STM-4 I-40 S-4.10 S-4.20 L-4.10 L-4.20 L-4.30
STM-16 I-16 S-16.1 S-16.2 L-16.1 L-16.2 L-16.3
a) These are target distances to be used for classification and not for specification.
TABLE 1/G.957
Classification of optical interfaces based on applicationand showing application codes
Parameters for STM-16 interface
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Unit Values
Digital signalNominal bit rate kbit/s
STM-16 according to Recommendations G.707 and G.9582 488 320
Application code (Table 1) I-16 S-16.1 S-16.2 L-16.1 L-16.2 L-16.3
Operating wavelength range nm 1266a)-1360 1260a)-1360 1430-1580 1280-1335 1500-1580 1500-1580
Transmitter at reference point S
Source type MLM SLM SLM SLM SLM SLM
Spectral characteristics
maximum RMS width () nm 4
maximum 20 dB width nm 1 < 1b) 1 < 1
b) < 1b)
minimum side mode suppression ratio
dB 30 30 30 30 30
Mean launched power
maximum dBm 30 00 00 +3 +3 +3
minimum dBm 10 50 50 2 2 2
Minimum extinction ratio dB 8.2 8.2 8.2 8.2 8.2 8.2
Optical path between S and R
Attenuation rangec) dB 0-7 0-12 0-12 10-24e) 10-24e) 10-24e)
Maximum dispersion ps/nm 12 NA b) NA 1200-1600b),d) b)
Minimum optical return loss ofcable plant at S, including anyconnectors
dB 24 24 24 24 24 24
Maximum discrete reflectance
between S and R
dB 27 27 27 27 27 27
Receiver at reference point R
Minimum sensitivityc) dBm 18 18 18 27 28 27
Minimum overload dBm 30 00 00 9 90 9
Maximum optical path penalty dB 1 1 1 1 2 1
Maximum reflectance ofreceiver, measured at R
dB 27 27 27 27 27 27
Multiplex-Section Protection
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A number of MSP architectures exists of which two is shown:
T1508790-92/d33
0
1Workingchannel 1
Permanent
bridgeSelector
Working
section 1
FIGURE A.1/G.783
MSP Switch 1 + 1 architecture example(shown in released position)
Protectionsection (0)
T1508800-92/d34
0
1
2
15
15
0
1
2
Working
channel 1
Protectionsection (0)
Selector
Workingsection 1
Working
section 2Working
channel 2
Extra
traffic
channel
(15)
Null
channel (0)
Bridge
FIGURE A.2/G.783
MSP Switch 1 : n architecture example(shown in released position)
1+ 1 protection
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T1508790-92/d33
0
1Workingchannel 1
Permanentbridge
Selector
Workingsection 1
FIGURE A.1/G.783
MSP Switch 1 + 1 architecture example(shown in released position)
Protectionsection (0)
1:n protection
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T1508800-92/d34
0
1
2
15
15
0
1
2
Workingchannel 1
Protectionsection (0)
Selector
Workingsection 1
Workingsection 2Working
channel 2
Extratrafficchannel(15)
Nullchannel (0)
Bridge
FIGURE A.2/G.783
MSP Switch 1 : n architecture example(shown in released position)
STM-n Signal Composition
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Composition of an STM-n signal carrying a 140 Mbit/s PDH signal
C-4 => VC-4 => STM-n
Clock 1Clock hierarchy:
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T1816900-92/d26
PRC Primary reference clock
G.811
PRC
G.812
node
clock
G.812
node
clock
G.812
node
clock
G.812
node
clock
G.812
node
clock
G.812
node
clock
FIGURE 6-2/G.803
Synchronisation network architecture inter-node distribution
T1816890-92/d25
Synchronisationlink(s)
Node
boundary
SDH
network
element
clock
SDH
network
element
clock
Nodeclock
SDH
network
element
clock
SDH
network
element
clock
Distribution to other
G.81s clocks
outside the node
a)
a)
a)
a)
FIGURE 6-1/G.803
Synchronisation network architecture intra-node distribution
Timing only.a)
Clock hierarchy:
Primary reference clock (PRC)Slave (transit)Slave (local)SDH element clock
Clock 2
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The clock of a SDH Network Elementcan be synchronized in two ways:
a) Synchronization to an incoming STM-N line.
b) Synchronization to a Node clock which is synchronized to a STM-N signal,a 2048 kbit/s signal or a 2048 kHz signal.