Async2002 Tutorial: - 1 Balsa – Description to Layout A Hands-on Tutorial Session Doug Edwards &...

Async2002 Tutorial: - 1

Balsa – Description to Layout

A Hands-on Tutorial SessionDoug Edwards & Andrew Bardsley


Other Balsa Tutorials

Async 2000 (Eilat)• concentrated on language aspects• small design examples• Xilinx implementation of calculator

ACiD summer school, July 2002• probably in-depth use of language for

design examples• buy the book - ISBN 0-792-37613-7


Aims of Async 2002 Tutorial

To explore parts of the system not demonstrated previously • GUI front-end

– balsa-mgr

• back-end alternatives– “how do I produce silicon”?– “what are the trade-offs”?

To gain some exposure to the language• but, language learning by osmosis!


Session Schedule

Brief overview of the Balsa system Language introduction

• hands-on examples To synthesise the original Manchester

Small-Scale Experimental Machine• experiment with different back-ends

A replica of the original SSEM is on display at the conference dinner


Session Schedule

Coffee Break Advanced Design

• Spamulet0 – write your own ARM-like processor description


The Balsa TeamDoug EdwardsDoug EdwardsTeam LeaderTeam Leader

Luis PlanaLuis PlanaDual RailDual RailBack-endBack-end

Andrew BardsleyAndrew BardsleyChief Architect/ImplementerChief Architect/Implementer

Will TomsWill Toms1-of-4 Back-end1-of-4 Back-end

Lilian JaninLilian Janinbalsa-mgr/LARDbalsa-mgr/LARD


Balsa Requirements

Freely available• ftp://ftp.cs.man.ac.uk/pub/amulet/balsa/• not all back-ends available

OS requirements:• Linux• Sun Solaris 7-8• MacOS X (+ X11R6 …)


Front EndFront End


Compass DACompass DARouteRoute


xilinxxilinxrouteroute


top level relies ontop level relies onpowerviewpowerview


CadenceCadencerouteroute


Other Balsa Work

Burst-mode resynthesis• Tibi Chelcea & Steve Nowick

Faster LARD simulation• Lilian Janin (x50 speed up)

Datapath compilation optimisation• Andrew Bardsley

Complete Amulet implementation• Peter Riocreux et al.


Proven Balsa Synthesis- DMA Controller for DRACO

Balsa SynthesisedBalsa SynthesisedDMA ControllerDMA Controller


DMA Controller Layout


What is Balsa?

Language for synthesising large async circuits & systems

CSP/OCCAM background Tangram-like

• based on Tangram compilation function• compiles to a small, parameterisable, set

of handshake components• origins: ESPRIT 6143 EXACT project


Handshake circuits – 1

Components communicate along handshake channels

Channels connect to ports on components

Ports have:• Type• Direction• Sense


Handshake Circuits – 2

Port type determines the number of data wires• no data wires == control only port!

Port direction is input, output or control only (called sync)

Port sense• Active: initiate transfers (source the req)• Passive: respond to requests (… the ack)


Balsa Language Features

Data types based on sequence of bits• Arrays and records are bit-based• Element extraction is by array slicing• Strict data typing

Structural iteration Arrayed channels Parameterised, recursively expanded

procedures


Balsa Language Features

Enclosed selection semantics• Allows passive ported circuits• Allows push (micropipeline-style) circuits• Allows unbuffered (latch-free) circuits


Example: Single Place Buffer

import [balsa.types.basic]

type word is 16 bits

procedure buffer (input i : word; output o : word) is

variable x : word

begin

loop

i -> x ; -- Input communication

o <- x -- Output communication

end

end


Example: Single Place Buffer



procedure buffer (input i : word; output o : word) is

variable x : word

begin

loop

i -> x ; -- Input communication

o <- x -- Output communication

end

end

librarymechanismtype declaration

channel declarationsprocedure

definitionimplies latch

repeat forever

output local variable xto output channel

read input channel intolocal variable x

sequential operation


Buffer Handshake Circuit

Single-place buffer

#

x T

;

Ti o

activationchannel

repeater

sequencer

variable

transferrer


#


Single-place buffer

Repeater is activated

x T

;

Ti o


;

#


Single-place buffer

Sequencer handshakes to left transferrer

x TTi o


;

#


Single-place buffer

Transferrer requests data from environment

x TTi o


x

;

#


Single-place buffer

Data transferred to variable x

TTi o


x

;

#


Single-place buffer

Variable handshake completes

TTi o


x

;

#


Single-place buffer

Transferrer handshake completes to environment

TTi o


x

;

#


Single-place buffer

Transferrer handshake completes

TTi o


x

;

#


Single-place buffer

Sequencer handshakes to right transferrer

TTi o


x

;

#


Single-place buffer

Transferrer reads variable

TTi o


x

;

#


Single-place buffer

Transferrer outputs to environment

TTi o


x

;

#


Single-place buffer

Sequencer initiated handshakes complete

TTi o


x

;

#


Single-place buffer

Sequencer completes its activation handshake

TTi o



Single-place buffer

Repeater initiates another transfer, repeat

x

;

#

TTi o


Example Handshake Component

Handshake definition of repeater (Loop)Loop(a,b) = (a: #[b])

= (a: #[b;b])

= (ar: #[br ; ba ; br ; ba])

ba

brar

aa


Example Handshake Component

Case component (single-rail)

data “n” bits wide

true/complement lines:dual-rail expansion

1 hot encoding


Compilation Tools

balsa-c• compiles Balsa programs to Breeze• includes other Breeze definition files

– Breeze is a handshake -circuit netlist format– acts as a library format for within Balsa

balsa-netlist• produces an appropriate netlist from a

compiled Balsa program– technology specific options


Simulation Tools

breeze2lard• produces a LARD simulation file

various LARD utilities• mainly hidden within the Makefile by

balsa-md


Utilitity Tools

breeze2ps• creates a PostScript HC graph

breeze-cost• enumerates the handshake circuits used

and gives an approximate area cost balsa-md

• automatic Makefile maker balsa-mgr

• GUI interface to balsa-md


Exercise: Single Stage Shift Register

Objective: introduction to balsa-mgr

cd ~/Balsa/shift-reg balsa-mgr &

• create new project: Project -> New

• add SRA1.balsa to project


create new projectcreate new project

Creating a Project


set nameset name

Set Project Name


Add FilesAdd Files

Adding Files


pick file(s)pick file(s)

Choosing Files


File list paneFile list pane edit paneedit pane

usual iconsusual icons

Project Window


Project Manager

tool-tip help pop-ups for icons editor icon opens the editor defined in: Project -> Environment dialogue• syntax modes for xemacs, elvis, nedit

right-mouse clicking on panes brings up context sensitive menus

Browse the various menus (& pop-ups)


Single Stage Shift-Register

-- Single Stage Shift Register SRA1.balsaimport [balsa.types.basic]

procedure SRA1 (input i : byte ; output o : byte) is

variable x : byte

begin

loop

o <- x ;

i -> x

end

end

read before writeread before write


Examining the Handshake Circuits

Switch to Makefile pane in balsa-mgr list handshake circuits & their area cost

• click on cost run button view handshake circuit graph

• click on SRA1.ps view button


Viewing Cost

click on tabclick on tab


make commandsmake commandsidentifiesidentifiesoutput paneoutput pane

list of HCslist of HCs

total costtotal cost

Execution Window

standard error panestandard error pane

standard out panestandard out pane


Making Handshake Circuit Graph


repeaterrepeater

sequencersequencer

transferrerstransferrers

registerregister

internalinternalchannel nameschannel names

I/O portsI/O ports


Exercise:n-place Shift Register

Objective: illustration of composition, structural iteration and simulation.

specify an 8-place shift register• add SRA8.balsa to project• ensure SRA8.balsa is selected• click on breeze compile button in

Makefile pane• select add test fixture from right-click

pop-up

See KvB: “Handshake Circuits”See KvB: “Handshake Circuits”


Adding SRA8


SRA8 Code

-- Multistage Shift Register SRA8balsaimport [balsa.types.basic]import [SRA1]

procedure SRA8 (input i : byte; output o : byte) is constant n = 8 array 1..n-1 of channel c : bytebegin SRA1 (i, c[1]) || SRA1 (c[n-1], o) || for || j in 1 .. n-2 then SRA1 (c[j], c[j+1]) endend


SRA8 Code



define a constantdefine a constant

internalinternalchannel arraychannel array

parallelparallelcompositioncomposition

structuralstructuraliterationiteration


Structure of Circuit

SRA8SRA8 SRA8SRA8 SRA8SRA8 SRA8SRA8……..

channel ichannel i channel ochannel o

channel c[1]channel c[1] channel c[n-1]channel c[n-1]

channel c[2]channel c[2] channel c[n-2]channel c[n-2]


SRA8 Code




Exercise:Hierarchical vs Flattened views

Check the cost of SRA8 and view the handshake circuit

Change to flattened compilation• Project -> Project Options -> Flattened Compilation

Recheck the cost of SRA8 and view the handshake circuit again• Flattened compilation gives “true” cost


AddingTest Fixture

right clickright clickpop-uppop-up


Test Options Pane

set inputset inputfilename to: datafilename to: data


Running LARD Simulations

text-onlytext-onlysimulationsimulation

channel-viewerchannel-viewersimulationsimulation


Simulation Results (Text)

empty values readempty values readthen input datathen input data


Lard Channel Viewer -1


Lard Channel Viewer -2

input & outputinput & outputchannelschannels

internalinternalchannelschannels

incompleteincompletehandshakeshandshakes

red = requestred = request

green = ackgreen = ack

data valuesdata valueson channelson channels

zoom buttonszoom buttons


Improved Shift-Register Stage

After 1st output last stage is ready for an input: it is vacant• The vacancy propagates backwards

towards the input stage Can not input a new value until vacancy

reaches input stage• poor throughput

Modify SRA1 to include an input and output register


Improved Shift-Register Stage

Input channel i to reg x in parallel with outputting y to channel o from reg y

Then assign y to x Register assignment

is: y := x

ii

oo

xx

SRC1SRC1

yy


Exercise:Language Level Trade-offs

Write your own SRC1 and SRC8• copy SRA1.balsa to SRC1.balsa and edit

Compare the cost of SRC8 with SRA8(must use flattened compilation)

Compare the behaviours of SRC8 and SRA8


Wagging Shift Register: SRW8

SRD1: demux i to o1, o2 alternately SRE1: mux i1, i2 into o alternately Middle SR can be either type A or C

SRA/C3SRA/C3

SRA/C3SRA/C3

xx

yy

xx

yy

ii ooo1o1

o2o2

i1i1

i2i2

SRD1SRD1 SRE1SRE1


Exercise:Build a Wagging Shift Register

SRD1• read channel i into register x while writing

register y to channel o1• read channel i into register y while writing

register x to channel o2• repeat

Middle Registers• compose 3 type A or type C register stages

in each half


Answers:SRD1

-- Single Stage Shift Register: SRD1.balsa-- DeMuxes data stream for Wagging Shift Registerimport [balsa.types.basic]

procedure SRD1 (input i : byte; output o1, o2 : byte)is variable x, y : bytebegin loop o1 <- x || i -> y; o2 <- y || i -> x endend


Answers:SRE1

-- Single Stage Shift Register: SRE1.balsa-- Muxes data streams for Wagging Shift Registerimport [balsa.types.basic]

procedure SRE1 (input i1, i2 : byte; output o : byte)is variable x, y : bytebegin loop o <- x || i1 -> y; o <- y || i2 -> x endend


Answers:SRW8

-- multi-Stage Wagging Shift Register SRW8.balsaimport [balsa.types.basic]import [SRD1] import [SRE1] import [SRC1]

procedure SRW8 (input i : byte; output o : byte) is constant n = 8 -- n must be even array 1 .. n/2 of channel c1, c2 : bytebegin SRD1 (i, c1[1], c2[1]) || SRE1 (c1[n/2], c2[n/2], o) || for || j in 1 .. n/2 -1 then SRC1 (c1[j], c1[j+1]) || SRC1 (c2[j], c2[j+1]) endend


The SSEM


SSEM (The Baby)

World’s 1st stored program machine• ran 21st June 1948 (GCD program)• 32 bit processor, 2’s complement• 7 instruction types• 32 word memory - (x 256 banks)• Single register accumulator (ACC)• program counter (PC)

http://www.computer50.org/


SSEM Instruction Set

JMP ; PC := M[Addr] indirect jump

JRP ; PC := PC + M[Addr] relative jump

LDN ; ACC:= - M[Addr] load negative

STO ; M[Addr] := ACC store result

SUB ; ACC := ACC - M[Addr] subtract

TEST ; if ACC<0 then PC := PC + 1 skip

STOP ; halt


SSEM Operation

Instruction execution sequence:• PC := PC + 1• IR := M[PC]• Decode and execute instruction

– memory operand fetch if required

Repeat until STOP instruction 1st instruction from address 1


SSEM Description: Types – 1

-- SSEM model in Balsa


type LineAddress is 5 bits

type CRTAddress is 8 bits

-- SSEM function types

type SSEMFunc is enumeration

JMP, JRP, -- Abs. and rel. jumps

LDN, STO, -- Load negative and store

SUB, SUB_alt, -- Two encodings for subtract

TEST, STOP -- Skip and stop

end

obvious typeobvious typedefinitionsdefinitions

enumerationenumerationkeywordkeyword


SSEM Description: Types – 2

-- Complete instruction encoding

type SSEMInst is record

LineNo : LineAddress;

CRTNo : CRTAddress;

Func : SSEMFunc

over word -- pad to 32 bits

recordrecordkeywordkeyword

overover keyword keywordrecord is paddedrecord is paddedto the width of wordto the width of word


SSEM Channel & Variable Declarations

-- SSEM: Top levelprocedure SSEM ( -- Memory interface, MemA,MemRNW,MemR,MemW output MemA : LineAddress; output MemRNW : bit; input MemR : word; output MemW : word; -- Signal halt state sync halted) is variable ACC, ACC_slave : word variable IR : word variable PC, PC_step : LineAddress variable MDR : word variable Stopped : bit

main proceduremain procedure

channelchanneldeclarationsdeclarations

data-less handshakedata-less handshake

instruction registerinstruction register

memorymemorydata regdata reg


SSEM: Function Use

-- Extract an address from a word

function ExtractAddress (wordVal : word) =

(wordVal as SSEMInst).LineNo

shared WriteExtractedAddress is begin

MemA <- ExtractAddress (IR) end


use functionuse function

SSEM: Function Use

-- Extract an address from a word

function ExtractAddress (wordVal : word) =

(wordVal as SSEMInst).LineNo

shared WriteExtractedAddress is begin

MemA <- ExtractAddress (IR) end

parameterparameter

cast into a recordcast into a record field selectorfield selectorcast 32 bit word into 32 bit recordcast 32 bit word into 32 bit recordthen extract bottom 5 bitsthen extract bottom 5 bits

shared proceduresshared proceduresreuse hardwarereuse hardware


SSEM: Auxillary Procedures – 1

-- Memory operations, shared procedures shared MemoryWrite is

begin MemRNW <- 0 || WriteExtractedAddress ()

|| MemW <- ACC_slave end

shared MemoryRead is

begin MemRNW <- 1 || WriteExtractedAddress ()

|| MemR -> MDR end

-- Fetch an instruction IR := M[PC]

procedure InstructionFetch is

begin MemRNW<-1 || MemA<-PC || MemR->IR end

copy of ACCcopy of ACC


SSEM: Auxillary Procedures – 2

shared ZeroACC is begin ACC := 0 end

shared ZeroPC is begin PC := 0 end

shared SUB is begin MemoryRead (); ACC_slave := (ACC - MDR as word) end

-- Modify the programme counter PC

shared IncrementPC is begin

PC := (PC + PC_step as LineAddress) end

shared AddMDRToPC is begin

PC_step:=ExtractAddress(MDR); IncrementPC() end


SSEM: Decode & Execute

procedure DecodeAndExecuteInstruction is begin case (IR as SSEMInst).Func of -- add JMP JRP LDN STO instructions SUB .. SUB_alt then SUB () | TEST then if (ACC as array 32 of bit)[31] then -- -ve? -- CI_step should already be 1 IncrementPC () end | STOP then Stopped := 1 end ; ACC := ACC_slave end


SSEM: Main Body

begin

ZeroACC () || ZeroPC () ||

Stopped := 0; -- reset initialisation

while not Stopped then

PC_step := 1;

IncrementPC ();

InstructionFetch ();

DecodeAndExecuteInstruction ()

end;

sync halted; halt -- STOP instruction effect

end


Exercise:Complete Instruction Decode

cd ~/Balsa/ssem create new project

• add ssem.balsa to project• complete DecodeAndExecute procedure or copy ssem.solution to ssem.balsa

• add LARD test file– options: LARD file: test-ssem.l– Sim Arguments: gcd.raw

• GCD source in gcd.s– assembler: ssem-asm


Adding LARD Test File

Picture here



Adding Lard Testfile Options


File Pane with Lard Test File


Running the Simulation

Click on Makefile tab Click on Run sim-<name> button

• channel viewer not too useful here Data:

• addresses 0x11 and 0x12 (0xC and 0x8) Result

• address 0x11 (4)

Beware, odd behaviourBeware, odd behaviourif the balsa file is ill-formedif the balsa file is ill-formed


Balsa Backend

A Balsa circuit may implemented in• Different technologies

– armlr7, ams035, (xilinx, st018, amust)– verilog - Example technology

• Each technology has different styles– Single rail– Dual Rail– One of Four

• Each style has various style options


Style Options

Datapath Logic• Standard DIMS• Balanced DIMS

– for “secure” applications

• NCL (Theseus style implementations)

Storage Elements• SR latches• Spacer latches: SR with enforced RTZ

– for “secure” applications

• NCL: pipelined NCL variables


Style Option Circuit Examples

Dual Rail Spacer LatchDual Rail Spacer Latch



1-of-4 RS Latch1-of-4 RS Latch



NCL Pipeline LatchNCL Pipeline Latch


Adding an Implementation



Choosing an Implementation


Generating a Netlist

Use balsa-mgr to generate an implementation• choose ams035• choose a different implementation / style

option from your neighbour.• make an implementation netlist


Generating a Netlist


Generating a Layout

Ensure you are in the correct directory• run_demo

A job is spawned on a remote machine to place/route the netlist and display a chip-plot

extract core area from report• core area: Total area (db units!)• report your result to the presenter• dismiss your chip-plot


Running a Back-Annotated Verilog Simulation

Ensure you are in the correct directory• run_demo -v gcd.raw

A job is spawned on a remote machine to run a verilog simulation• report simulation time to presenter• a waveform viewer (GTKWave) is spawned

– look at interesting signals !!

• dismiss the viewer.


LARD vs Verilog Simulation

LARD• no implementations required• test harnesses easy to write• integrated into Balsa system• source-level debugging• new improved system “real soon”

Verilog• standard language• was much faster (no longer)• initialisation issues


Compilation Process

balsa-c .breeze & .sbreeze files• .breeze reused by balsa-c• .sbreeze: lisp formatted version of breeze

balsa-netlist CAD system netlist• uses pameterised descriptions of

handshake components HCs described in abs language


position in fileposition in file

part add (

passive sync activate;

active input i : 4 bits;

active input j : 4 bits;

active output o : 4 bits) is

attributes ( isprocedure,isPermanent,noOfChannel=17,line=6,column=1)

local

sync “@9:4” #1

pull channel “i” #2 : 4 bits

pull channel “j” #3 : 4 bits

push channel “o” #4 : 4 bits

pull channel “x” #5 : 4 bits

sync “@12:11” #6

pull channel “b” #7 : 4 bits

Breeze Format

internal channel numberinternal channel number


Breeze Format Ctd

begin

$BrzVariable ( 4,1,”a[0..3]” : #14,{#8} )

$BrzLoop ( #1,#17 )

#BrzSequence ( 3:#17,{#16,#11,#6} )

#BrzConcur ( 2:#16,{#15,#13} )

#BrzFetch ( 4 : #15,#2,#14 )

#BrzBinaryFunc (4,4,4,Add,false,false,false:#9,#8,#7)

#BrzFetch (4:#6,#5,#4 )

end

widthwidth no of read portsno of read ports write portwrite port

read port listread port list


Abs Language

gate operators• expands descriptions to trees of gate• contains AND, OR-gates…, C-elements• places helper-cells

partitioning operators• manipulate vectors

small expression language


Creating New Libraries

Configuration File:• specifies netlist format to use• specifies cell description files• name mapping (long to short names)• maximum fan-in of gates

Gate Description File• list of gates in library with pin-mappings


Creating New Libraries

Gate Mappings File:• mappings from abs gates to cell library

gates and helper cells Helper Cells Descriptions

• descriptions of helper cells used in the abs descriptions

Component Descriptions File• technology specific abs components &

links to generic descriptions


Minimum Component Requirement

Technology must support Structural Verilog, EDIF 2 0 0, or Compass ntl netlists• or the originator could add a netlist format

to Balsa Inverter 2-input AND, NAND, OR, NOR Latch or Flip-flop


Recursive Definitions: An n-way multiplexer

Decompose multiplexer

inp0

inp 1

inp n-2

inp n-1out 1

out 0

inp 0

inp n-1

inp n/2

outout

Before Decomposition After Decomposition

inp n/2-1


An n-way multiplexer -1

-- Pmux1.balsa: A recursive parameterised MUX definition


public

procedure PMux ( parameter X : type;

parameter n : cardinal;

array n of input inp : X;

output out : X ) is

begin

-- procedure body

width of input

number of inputs

each input is a channeloutput

channel



if n = 0 then print error,”Parameter n should not be zero”

| n = 1 then

loop

select inp[0] then

out <- inp[0]

end

end

| n = 2 then

loop

select inp[0] then

out <- inp[0]

| inp[1] then

out <- inp[1]

end

end

when data arrives oneither input, pass it to output

base cases

selectselect keyword keywordencloses blockencloses block



else

local

channel out0, out1 : X

constant mid = n/2

begin

PMux (X,mid, inp[0..mid-1], out0) ||

PMux (X,n-mid, inp[mid..n-1], out1) ||

PMux (X,2, {out0, out1}, out)

end

end

2 internallocal channels

two half-size muxs& one 2:1 mux

local block withlocal definitions


Testing the MUX

cd ~/Balsa/pmux Open the project using balsa-mgr

• test_mux exercises the mux• Simulate test_mux


Spamulet0 - Prototype for SPA1

Subset of ARM instruction set ALU ops, LDR/STR, Branch, Branch

with link (procedure call) implemented Sequential, register based design like

the SSEM Your task is to add to this description Spamulet0 lacks LDM/STM, MUL, SWI,

Coprocessor I/F, Pipelining, Exceptions, Operating modes


The Project File cd ~/Balsa/spamulet0 4 Balsa files, LARD test harness

• types.balsa - type and instruction format records

• alu.balsa - ALU with CC handling• shift.balsa - parameterised shifter• spamulet.balsa - top-level, fetch-

decode-execute loop• test-spamulet.l - LARD test harness


Simulation Framework

LARD test harness provides simulated memory loaded from raw memory dump files

Small number of provided examples: hello.s, multiply.s, helloc.c

Memory dumps generated from:• Assembler: .s spamulet-asm .raw• C: .c spamulet-cc .raw


LDM/STM - Load/Store Multiple

Load and store any of the registers as a block - including the PC!

Commonly used for function arguments, entry register saves and return

ldmdir Rbase!opt, {Ri, Rj, …} stmdir Rbase!opt, {Ri, Rj …} Registers always appear in memory in

the same order with R0 at lowest address, R15 at highest


LDM/STM Directions

dir is one of:• ib - increment before• db - decrement before• ia - increment after• da - decrement after

Problems include loading PC last and avoiding overwriting the base register


LDM/STM Directions 2

LDM/STM can also be used with “stack addressing”• fa - full ascending (ldmda, stmib)• fd - full descending (ldmia, stmdb)• ea - empty ascending (ldmdb, stmia)• ed - empty descending (ldmib, stmda)

The C compiler generated LDM/STMs with the stack addressing names


Instruction Encoding


Instruction Encoding – 2

Look at instLdmStm in types.balsa Use: (ir as instLdmStm) to decode

instructions• e.g. (ir as instLdmStm).options.L

is the load(1)/store(0) select bit Option bits very similar to LDR and STR

instructions, read spamulet.balsa


Implementation Strategies

Edit spamulet.balsa Use a while loop and a variable to

iterate through the register select bits ((inst as instLdmStm).regs)

Perform memory access using MemoryRead and MemoryWrite

Don’t worry about PC or overwriting the base register yet


Some Important InformationInstruction L bit P bit U bit

ldmda/ldmfa 1 0 0

ldmia/ldmfd 1 0 1

ldmdb/ldmea 1 1 0

ldmib/ldmed 1 1 1

stmda/stmed 0 0 0

stmia/stmea 0 0 1

stmdb/stmfd 0 1 0

stmib/stmfa 0 1 1


Some Important Information 2

W bit specifies whether the base register is to be written back (W=1) or keep its pre-LDM/STM value (W=0)

The “!” in the mnemonic selects writeback

Ignore the S bit - it’s used for processor mode changes (e.g. ISR returns)


Some Important Information 3

To help with debugging, Balsa has the print command

Prints simulation values in LARD Example:

• b <- v1; print “Hello”; b <- v2• print “v1=“, v1, “v2=“, v2

Enjoy


Additional Exercises

A choice of advanced design exercises:• A general shifter• A bit population counter

Language Summary in handout + code listings


A Balsa Shifter

General shifters required for processors Write a description for a rotate right

function• solution in ror/solution

Alternatively extend the standard solution to other shift functions


Structure of a ROR shifter

a local procedure


Bit Population Counter

Counting the number of bits that are set to ‘1’ is necessary for ARM’s LDM/STM instructions

Write description for such a unit• solution in popcount/solution


Bit Population Counter


Acknowledgements

Thanks to:• Jeff Pepper our resident CAD Tools expert• Dave Bowden, our AV technician for

bringing AV to these laboratories• The rest of the Amulet group, most of

whom are now using (debugging) Balsa• System support staff for setting up the

demo accounts etc.

Async2002 Tutorial: - 1 Balsa – Description to Layout A Hands-on Tutorial Session Doug Edwards &...

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Transcript of Async2002 Tutorial: - 1 Balsa – Description to Layout A Hands-on Tutorial Session Doug Edwards &...