Analytical Calculation of the Conduction and Switching Losses of The

8/12/2019 Analytical Calculation of the Conduction and Switching Losses of The

1/7

Analytical Calculation of the Conduction and Switching Losses of theConventional Matrix Converter and the (Very) Sparse Matrix ConverterF. Schafmeis ter , C. Rytz a n d J.W. Kolar

ETH Zurich, Power Elect ronic Systems LaboratoIyETH Zentrum / ETL H17, Physikstr. 3, CH-8092 Zurich / SWITZERLANDemail: schamieister~~lzm.ee.ethz.cbTel.: +41-1-632 6493 Fax.: -41-1-6321212

Abstract. To dimension the power semiconductors of a ConventionalMatr ix Conver ter (CMC) o r a two-stage S par s e M at r ix Conver t e rSMC nd/or Very SMC) extensive simulations usually have to beperformed as the losses of each device ar e dependent o n severaloperat ing parameters , including the dimerent rat ios of input a nd outp utfrequency. In this paper analytical expressions with high accurac y areder ived for the switching and conduction losses o f the CMC, SMC a n dVSMC's power semiconductors . These exprcss ions direct ly show theparameter dependencies of the power semiconductor switching andconduction losses and therefore ean be used to determine the msxlmalloen1 or average thermal s tress and for the thermal des ign o f t he powercomponents . Fur thermore, the to tal conver ter losses and conversionefficiency can be de term ined with minim al calculation effort.

I INTRODUCTIONConventional Matrix Converters (CMC, f. Fig. l a ) and two-stageSparse- and/or Very Sparse Matrix Converters SMC nd/orVSMC, cf. Fig. Ib), which shows a reduced number of powersemiconductors, are functionally equivalent [ I ] .

P i

nFig. I: Topology of the a) Conventional Matrix Converter (CMC) and

(b) Very Sparse Matrix Converter (VSMC)

The modulation method applied to the SMC andor VSMC isillustrated in Fig. 2. Within each pulse half period two ine-to-linevoltages ate switched into the DC link of the W S M C by propercontrol of the input stage. The adjustment of the output voltageamplitude is realized by the output s t a g e only, which allows theinput stage to operate without a free-wheeling interval. Moreover,the input stage commutation occurs at zero current cf. i in Fig. 2)and t h i s avoids the use of a multi-step commutation scheme that isdependent on the sign of the commutating voltage or current as isrequired for the CMC. How ever, the pulse pattern depicted in Fig. 2can be directly transferred to the CMC resulting in thecorresponding virtual DC link quantities UCMC and icMc [6]. Thisallows a direct comparison of both topologies.

ITFig. 2: Time behaviour of the DC link quantities U .i and of thecorresponding pulse patiem for the SMC ndor VSMC within p, E [ -x/6,ni61;p~ [d6,d31 for a pulse half period. Switching state changes of therectifier stage occur at zero DC link current. The pulse pattem can bedireclly transferred to the CMC resulting in an analogous virtual DC linkvoltage and current [ 6 ] .For conventional modulation of a SMC (being equivalent to indirector virtual DC link modulation of a CMC), the relative turn-on t imesof the single switching states [1-3] e.g. for p, in -d6 ..+66 and p2in 0.. h / 3 (as given in Fig.2) are

d,, = cos(p/ w / 3 )

0-7803-8975-1/05/ 20.002005 IEEE. 875


2/7

11 SWITCHINGOSSESFor calculating the energy loss of one single switching action thathas dependency on the switched voltage and current a polynomialapproach, using ( lo) , is used.

w ( u , i )= K , u i + K p i ' +K , v Z +K 4 u 2 i +K,u2i2 (10)The parameters Ki are derived from a least square approximation ofmeasured data (cf. [9]) and are compiled in Tab. 1 for a specificpower transistor / power diode combination (IXYS FII50-12E).It should be m entioned that (IO) considers all physically reasonableterms of the switched voltage I and current i. It is also possible toneglect some of the terms while approximating the measured lossesin order to simplify the mathematical expression. This would alsosimplify the expressions describing the global powersemiconductors losses, which provide the dimensioning basis andwill be given in the following section.

(3)

The switching state of the (V)SMC rectifier stage is determined bythe two input phases, which are connected to the positive (p) andnegative (n)DC link bus. For example,is valid for the first rectifier state of the pu ke sequence shown inFig. 2. Thereby, the acrual rectifier switching state matrix

SRcer = ( p ; n )= (ac) (4)

1 0 0SRCEI = o 0

is represented by S R ~ ~ ~n a very compact way. Analogously, theswitching state of the (V)SMC inverter stage is described by theswitching states of the three transistors being conn ected to the p-busbar. For example, the first inverter switching state of the depictedpulse period can be represented bysin = ( S A S B S&(l 1 o ) ,

instead of the inverter switching state matrix1 1 0s, =(* (7)Considering ( 5 ) and 7 ) the output to input current transfer followsas

which fias to be equ.al to the single-stage CMC switching statematrix for the same connections between the output ( A , B , c ) andinput (n,b,c) erminals-. This yie ldsI-SCMC = S R e c , SI 9)

which directly provides the switching state correspondence of CMCand (V)SMC as shown in Fig. 4a.In this paper the basic considerations concerning the modelingof the time behavior of the switching and conduction loss

components of the CMC and the (V)SMC are proposed. In a firststep both loss components are calculated as an average over asingle pulse period and will be denominated as local tosses. Thoselocal losses are again averaged over a whole mains fundamentalperiod in a second step. Considering the converter system, as in astandard application feeding a synchronous or asynchronous motor,the maximum of the resulting loss term in becomes relevant foroperating points close to standstill. Finally, a last averaging over aentire load fundamental period yields the loss value that is relevantfor the dimensioning of the semiconductors when operating atoutput frequencies larger than 5Hz and for the heat sinkdimensioning in general. This last averaged value is the mostsignificant and will be referred to as the global loss in the paper.This approach leads to formulas that accurately describe the globalaverage losses and therefore provides a reliable basis for thethermal dimensioning of the power semiconductors and the heatsink.

In Section I1 the switching losses of CMC and (V)SMC areinvestigated. Th ere the analytical considerations focus on the CM Cand are proven by a digital simulation of a switched model. Section111 is dedicated to the analytical description of the conductionlosses. The main focus is on the CMC for which global averageconduction loss fomiulas of general validity can be derived withlow effort. In order to demonstrate the usage of the proposedequations in the design process a simple dimensioning example isgiven in Section Iv.

Tab. 1: CoeflicientsK,..K, erived by least-square approximations ofmeasured IGBT / free-wheeling diode (IXYS FII50-12) switching Iosses fora junction temperature of 1;-120C (cf. [9]).1I.A CONVENTIONALATRIX ONVERTERCMC)For a switching action of the CMC, two bidirectional switchesconnected to the same output terminal are subject to losses.Considering a particular switching sequence of a full pulse period,each switching action of a switch in the first pulse half period isfollowed by an inverse switching action under same conditionswithin the second half of the pulse period (assumingfp + 0, so thatthe ripple components of voltages and currents are neglected).Accordingly, the turn-on and tum-off energy of a certain switch canbe added as given byAs illustrated in Fig. 3a, he switching losses for the bidirectionalswitch S, are dependent on the output phase current iA nd theinput line-to-line voltage determined from the two input phasesinvolved in the switching actions (tid = uab or ud = U= . Theswitching losses of switch cell SPA only occur in one of the foursemiconductors, which is dependent on the signs of ud and iA (cf.Fig. 3b).

w o n o ~ ( ~ . i )w,,,(u.i)+ w,ffCu.i). (1 1)

U,

(4 (b)Fig. 3: (a) Schematic and notations of the bidirectional switch cell A. Thcsemiconductorbeing subjcct to switching losses s determined by thc signo fthe switched voltage ud and switched current i~ cf. (b)).For analyzing the switching actions of each bidirectional CMCswitch within a certain pulse half period, a switching table (given inFig, 4) is used that gives the CMC switching state matrix 9) far thedifferent intervals o f a pulse half period. This table corresponds tothe pulse pattem shown in Fig. 2and is valid for angles q, =w/ tf [-d 6 , d6] nd pZ = q E [x/6, 3]. t visualizes how often a certainswitch is changing its state within the pulse half period.Furthermore, it allows a direct determination of the switched

876


3/7

voltage ud . Analogous tables have to be crcatcd for three hrthcrcombinations of an gle intervals (p ,@),which allows thc bellaviorof each bidirectbnal switch within a full mains and load period(from symmetry considerations) to be determined.

\a ~ o : i o o l i o o 0o:ioolmio0 0 0 ~ 0 0 0 ~ 0 0 01 1 ' 0 1 1 0 0 10 0 1 ~ 0 1 1 I 1 I 0 0 0 ~ 0 0 0 ~ 0 0 0

Fig. 4: a) Schematic o f hc CMC with ideal switches. (b) Switching statesof the CMC and (V)SMC for a pulse half period with the relativc on-times(for q,E [-+/6, 6 ] ; p2E [ d 6 ,d31 .The local switching losses are finally calculated by adding up allenergy losses wow i ) for a pulse period and m ultiplying the sumwith the switching frequency& .This results, in combination with the aforementioned symmetryconsiderations, in the switching loss characteristic depicted in Fig. 5for the transistors Td and TA, (valid for 02 = 0). There, thecoordinate indicates a position within the output voltagefundamental period, while the p~coordinate indicates a positionwithin the input voltage period. The symmetry of the lossesoccurring in the fonvard Td)- nd reverse transistor (TAJ causedby the sinusoidal load current i A is obvious. It is important to notethat the switching loss characteristic consists of several differentsegments, therefore it is not a trivial cxercise to find a generalanalytic expression providing the global average of thatcharacteristic for varying output current and voltage displacementangles m2Unlike the (V)SMC where switching losses only occur in theinverter stage (the rectifier stage does not show switching losses,since it is switched at zero DC-link current), the CMC switchinglosses do occur during the switching of the virtual rectifier stage(e.g. all losses occurring for p2E [-7t/6,d 6 ] ; cf. Fig. 5 ) .

Depending on the ratio of output frequency f and inputfrequencyf, the (linear) trajectory o f the operating point ( ~ ~ 2 1 t h,p,=Zxfi I in the i -p/plane will show a characteristic slope andresults in a corresponding variation of the local losses (cf. [9]).

Psw = p w Z o n o f l (12)

Fig. 5: Local switching losses of transistors Ta and h forming witch S dof thc CMC or = 0. The diodes D A nd Dh also show a qualitativelysimilar characteristic hat is displaced by n rad in p, or @-direction.

Fig. 6 shows the switching losses rcsulting for such a characteristicslope for the operating point:,f, = 501Ix;f2 = 751Iz; m 2 0 within atime interval of 20ms. he depicted graph could be seen as profileresulting from cutting the 3D characteristic given in Fig.5 along ap,, q? = (0, 0) + 4d3,n) - 4x13, 0) + (2n, b) axis. Alsoincluded in Fig. 6 are the results from a numerical simulation(SIMPLORER) using a switching CMC model and it provides anidentical result and clearly verifies the analytical approach.

II.A.1 GLOBAL LOSSESThe global average switching loss for one semiconductor is mostrelevant for its dimensionmg and can be derived by averaging overthe whole -pz plane (13). Extensive simulations have proven thatthis value differs by less than 3% from the exact average valuesgained for an extremely wide variety of different operating points,each with a characteristic time behav ior, such as the one in Fig. 6 .

t2120 0

100 0

75 0

5 0

25 0

0 0 5 00 1000 15 00 20--t1 h l

F i g . 6 : Companson of the analytically calculated and the simulated(switchcd CMC model) swi tching losscs of hc CMC transistors T,, T of/ , = S O H Z ; ~ - ~ ~ H Z , M =,@2-0

+ 3x( 4 i z ( j2K2 + 1 0 K , U i ) + & ( 2 K , ~ , + j : f S K , + K 5 f i , ) ) ) -- Zj, (,xiK&5 +4lr)fi,case* --3ji[l2&K, + f i i K , ( 9 + '&f ] )C0 (?@2))

(13)This equation is valid for all semiconductors of the CMC (assumingQ2 E [-7d3, n/3] r O2E [2d3,4x/3]),here the substitutioncan be used for the transistors and

K i + K,,Ton + K#,Tof l (14)Ki + K,&f (15)

for the diodes. Since the polynomial (10) depends linearly on thecoefficients K,, the switching losses of the whole converter can becalculated by the sub stitutionKi 8 Ki,Ton + Kt,~onK , , h f ) . 1 6)As mentioned above, (13) could be simplified by considering areduced number of polynomial coefficients of (10) .ILA.2 M A X I M U MN pzBesides the global average value of the sw itching losses, their localmaxima are also relevant for the semiconductor dimensioning.Since there is a thermal transient impedance of the semiconductordevice (which physically can be characterized by a thermal time

877


4/7

constant r,hn=RaC,*) the areas of maximum switching losses in Fig.5should be averaged over q h . This yields relevant Local loss values,being directly responsible for the temperature rise of the junctionwith reference to the heat sink (dT=p R,*). As a consequence theconverter has to be designed in order to keep the local junctiontemperature below the tolerable maximum value at any time (i.e.for any p,,p2) nd for every operating point. Therefore, knowledgeof the value ~h is of special importance in order to determinephysically reasonable averaging intervals. First results fromextensive thermal simulations reveal an equivalent time constant ofrt,,= 60 ... 0ms for the IXYS FI150-12E / FI050-12BD modules.When considering a mains frequency of f i - 5 0 . . .60Hz, herelatively large value cif r,h clearly justifies averaging aver a wholemains period. As a result the losses depend, mathematically, onlyon @, This means for very low output frequencies, fi 5 5Hz,hemaximum loss value in pz becomes relevant. Graphically thisoperating point corresponds to a trajectory within the p~p2 planeof Fig.5 running approximately in parallel to the QII axis.The local loss maximum in p2 is relevant for dimensioning aconverter system operating with very low output frequencies( andor motor speed close to standstill) and is gained from

for Q1* E (0, /6]for m2 [d6,d2].I1.B (VERY) PARSE ATFUX ONVERTERVSMC)Due to the zero current switching of the (V)SMC input stage therelevant switching losses occur only in the output stage. Fig. 7shows the bridge leg A of the inverter stage.

Fig. 8: Semiconductors in bridge leg A of VSMC nverter-Stage.Within the intervals v2 E [-d6, ]U [5r/6, d6] he bridge legA is clamped either to the p-bus bar or to the n-bus bar andtherefore is not producing any switching losses. ForpzE [n/6 ,5n/6] he phase current iA is positive iA > 0) and thuscauses losses in transistor TpA nd the corresponding free-wheelingdiode DnA. For f i E [ 7 d 6 , l l x /6 ] the negative phase current(iA < 0) leads to switching losses in TA, nd DAp. oth transistorsTPAnd TA,,are switched on and off twice during one pulse period.The two DC link voltages that are switched during one pulse periodare given for the general case with up nd U, (and correspond to U,and u0b in Fig.2). Summing the turn-on- nd turn-off osses (11)results in the local losses which are given by

1 8), .Psw = f P b,,fP p IA 1+ WO,, U i.4 11with

With a conventional output stage clamping stracegy being applied.Applying an adapted strategy would lead to isw = J s / 2 f, or @ t [0, 6].

The resulting switching loss characteristic of the (V)SMC inverterstage is shown in Fig. 9.

Fig. 10: Local switching losses of bridge leg A of the VSMC inverter stagefor the four power semiconductors ( @ I = 0).

II.B.l GLOBAL OSSESAveraging over the whole qI q2plane of Fig.8 leads to the globalaverage value of the (V)SMC switching losses. For a single powersemiconductor the global average value isfSw,T/D 7 ( 4 B j : ( 6 K 1P 6 + ~ z i 2 - )i 4 u , ( 3 + 4 s ) ( 6 K 4 j l + 2 d ~ + 5ii))-

32n- 2 i 2 12K, K, 3 f i +4s)fiI OS Ut2 --3i:(12&Kz + C,K , (S+ 4 )Los(2@2))

(22)

(23)Again, the switching losses caused by the entire converter systemare obtained with the following substitution

K i + (Ki,Ton + Ki,rog + K i . h f

II.3.2 MAXIMUMN (p2Analogously to Section II.A.2 the local switching loss maximum inp2,which is relevant for very low output frequencies only, can bederived from he formula-P S W , T / D (P21=

for O2 E [0, d 6 ]for @z E [d6,2 ]

With a conventional output stage clamping strategy being applied.Applying n adapted strategy would lead to i s u / 2 j , for @ I E [O,d61.

878


5/7

111 CONDUCTIONOSSES1II.A CONVENTIONAL MATRIXO NVERTER (CMC)III.A.1 GLOBALOSSESAn analytical expression for the global conduction losses of theCMC semiconductors can also be derived with low calculationeffort. According to the system symmetries, the current stresses onthe three bidirectional switches S Sb, and S connected to theoutput A are equal and determined by output phase current iA. Thesign of the phase current determines the current conductingtransistor/diode pair of a switch. Therefo re, the output phase currenti A has to be split into a positive and a negative component (cf.Fig.7), where, for example, the semiconductors Td and Dd, reonly stressed by the positive component id' (cf. Fig. 3).

i A

Fig. 11: Il lustration of thepositive and negativecomponents in'and i~ ofthe output phase current iAfor an output displace-ment angle of @ =0.

Since all power semiconductors of the CMC show equal currentstresses the global average current and the rms current of thesemiconductors can be derived, as for the case of transistor TA

0Finally, the formula for the global conduction losses of onesemiconductor results as

Typical on-state parameters uF and r are given in Tab. 2. Since theglobal conduction losses are only determined by the convertertopology the result is independent of the modulation concept used,and is independent of the modulation index A4 and the output phasedisplacement angle D2,With the substitutions

29)1 8 u fTran. or -If . D i ~ d e--f 18(rTronsisfor r rDiade

the global conduction losses of the entire converter system can becalculated,Digital simulations again verify 28) showing an excellentcorrespondence. Analytically obtained values differ less than 5from he exact average values gained by a numerical simulation ofa switched CMC model for B wide variety of different operatingpoints.

Tab. 2: On-state parameters ofthe power transistor and diode ofthe power module lXYS FIlSO-

Diode

III.A.2 LO CAL LOSSES AND MAXIMUMN p 2For the calculation of the local power losses, an exact analysis ofthe semiconductor currents is required. The current stresses aredependent on the position within the input and output voltage periodp,, p2).Therefore, in a first step the relative turn-on-time dd of aswitch, e.g. S has to be determined.If the angle values p,, p2)are located in the interval p) E[ -7d6,d6] ; rpz E [ d 6 ,d3] cf. Fig. 4b), he rectifier states (ac), (ab)and the inverter states (] lo) , (IOO), (000) are switched within apulse period. Hence, the switch S is only blocking while the zerostate (000) is active. So, employing 1) the relative turn-on ime canbe calculated as follows

(30)n4 = d m ('4 IO + lOD + dab (4 O= M i 2 COS^ COS ^^ - 1 ~ 1 6 ) slOOBy analogous calculations the relative turn-on time of the switch Scan be derived for the entire plane 91E [O , 2711; p2E [O,Zn].Due tothe symmetry of the converter topology, the relative turn-on imefor the other switches can be obtained directly by introducingdisplacements of + 2 d 3 in rpl and/or p2 direction. The localconduction losses can be derived from the relative turn-on time

(31)pc = dd(uF iA + r i A )and are depicted in Fig. 12 for the power semiconductors of switchS with an operating point of M , 4 = 0.

v DAaT a A > b

Fig. Local conduct ion losses of switch Sd (CMC) for the operating pointM = 1, O2= 0. Dependent on the sign of the phase current i A ,the tossesoccur in the transistoddiode-pair T,/D, or TA,.After averaging pc over the entire mains period p ~ [0, 2151) theresulting conduction loss maximum in q2is gwen by

for any power semiconductor (independent of modulation and phasedisplacement Q2). This result i s also plausible with respect toFig.4a. Assuming a very low output frequency the output phasecurrent value will remain on an almost constant level. Tn the worstcase one of the three output terminals is loaded with the maximumvalue (current amplitude 12 ) . During one m ains period this current i sdistributed equally to a l l three switches being connected to thatoutput terminal. As a consequence the resulting conduction lossesare also shared by the three transistorddiodes.1II.B (VERY) P ARSE MATRIXCONVERTER(V)SMC)III.B.l INVERTER STAGEGlobal LossesAn exact analytical calculation [4] yields the global conductionlosses for the O S M C output stage transistors

879


6/7

and for the diodes

with the squared rms valuesI n v , f , m =I,

nd

2 . Zrr+6d>,+(8MI2 6)sin(2Q2-~)-16Mlzsin(@2 -f)24n

. 4 1 r -6 Q 2 -(8 M l 2 -6)sIn(ZQ,, -f)+16M,,sin(Q,2 -f)241r~ , n " , D . m = I Z 2

pC,lnv.(Y)SMC = 6 pC',Inv,T -I- C,Inv,D) .The conduction losse:; of the entire inverter stage can be directlycalculated by

I 3 )Local Losses and M ax im um in cptThe procedure to determine the local conduction losses of theinverter stage is similar to that described in Section III.A.2 for theCMC. The relative tum-on time of the transistors can be derivedand has to be weighted with the corresponding output phase currentvalue in order to get a local current average and rms value. With thegiven on-state parameters those values lead to the local conductionlosses. The results are visualized inFig.13.

Global Losses f o r Dl E O 661The global conduction losses of the rectifier stages can becalculated according to [4]. The results for the output phasedisplacement interval O2 E [O,n/6] which is the retevant one fordimensioning issues) are given as

(37)- -ITapa =-I , h f ( z . c o s 0 22xWith the defined current values (typical for transistor Tv,) he globalconduction loss formulas can be written in a more compact way.The generalized worst case to be considered for dimensioning therectifier stage is given byM 1 2=1,@2=0

The losses of the Very Sparse Matrix Converter are(38)

The losses for the additional components of the Sparse MatrixConverter are given as

Fig. 13: Local conduction losses of he inverter stage transistor TP* nddiode Dd(M,2= 1 ,4 3 2 == 0).The local conduction loss maximum in p2 that is relevant foroperation at very low output frequencies can be givenindependently from M,, nd as cf. 32))

(36)2F C J ~ ~ , T I DU F . I 2 + r * 1 2 .III.B.2 RECTIFIER STACEThe denomination of the power semiconductors is given in Fig. 14for the rectifier stage topologies of VSMC nd SMC.Pj

D,n

,...

....@)

Fig. 12: Diode and powersemiconductor structure of arectifier bridge leg for B VSMC(a)andSMCIbl.

Local Losses a n d Maximum in cplThe input stage conduction losses depend only on the DC linkcurrent, which comprises of positive and negative (if D2>d6)components. The DC link current components can be calculatedfrom the actual output phase currents being weighted with theappropriate relative turn-on times of the output stage transistors.The results are graphically shown in Fig.13 for transistor T-.For very low output frequencies applied to a motor in steady state(which has to be considered assuming a thermal time constant of= 60 ..80ms) almost no back EMF does occur. Therefore theconverter output voltage is also close to zero, which means themodulation index is about zero as well. Consequently this meansthat there will not be any rectifier stage losses at this operatingpoint:s2 <


7/7

Fig. 15: Local conduction losses of VSMC rectifier stage transistor T,paM= , @z = d3 . Remark: The characteristics of the other rectifier stagesemiconductors look qualimtively diCferent.

Iv DIMENSIONING EXAMPLE F A CMCTo show how the derived formulas are used for the dimensioningthe power semiconductors of a CMC, the following specificationsfor the CMC are used.Nominal output power:Input voltage amplitude PIN= 7.5kW01= 42 230VSwitching frequency j p 2 mzTherefore, the ou tput current amplitude is

1V.A SWITCHINGOSSCALCULATIONThe average junction temperature of the power semiconductors aredetermined by the global losses (13). Operating the CMC with anominal output current displacement angle of =O is considered inthis example, which represents the operation of a synchronousmachine in the motoring mode (steady state). From 1 3) using thecoef ic ients fiom Tab.1 the switching losses are calculated asTransistor Ps. r- 6.7WDiode Psw.D=3.3w.1V.B CONDUCTIONoss CALCULATIONThe global conduction losses do not depend on b. pplying (23)with the measured on-state parameters given in Tab.3 results inTransistor PCT=3 5wDiode Pc,o= 2.4W.1v.c TOTALOSSESThe total losses of a single semiconductor areyieldingTransistor P r = 10.2wDiode Po=5 7w

P T / D= P s ~ . T / RP c . T / o (42)

The total losses of the entire converter system can now be deriveddirectly usingPcMc =18- PT +PD (43)

Therefore the total loss of the CMC is Pcn(c=286W, or 3.8 of theoutput power.

In this context, it should be noted that the losses would rise toapproximately 4.7 if an output current displacement angle of4 1 2 4 3 was considered. Assuming a rather conservativedimensioning this value could be taken to represent the systemsworst case.

V CONCLUSIONSIn this paper the local switching and conduction losses of thedifferent power semiconductors of a single stage (CMC) and a twostage SMC n d o r VSMC) matrix converter have been investigatedin detail and visualized in 3D. The basic analytical approaches forderiving the local losses, which provide the foundation for theresulting dimensioning formulas, are given.Mathematical equations describing the global ave rage switchinglosses and the global average conduction losses are derived for bothtopologies. The global average values are accurate for all operatingpoints (alternative equations are provided for operation close tostandstill) of the converter systems and are of major relevance in thedimensioning of the semiconductor devices. Moreover, the globalloss equations can be applied universally. For calculating the lossesof different semiconductors of a given topology and even forobtaining the losses of the entire converter system the sameequations can be used, only the semiconductor specific coefficientshave to be substituted. Measured switching and conduction loss dataof a typical IGBTiDiode pair, operated at a junction temperature of1Z O T , are used as the basis for the presented numerical results. Thederived loss formulations for the matrix converters are o f highaccuracy to enable the dimensioning of power semiconductors andheat sinks.

References[ I ] Kolar, J.W., Bnumann, M. Schafmeister, F., and Ertl , H.: NovelThree-phaseAC-DC-,4CSparse Matrix Cunverter. Proceedings o f the 17thIEEE Applied Power Electronics Conference, March 10 - 14, Dallas, TX,[2] Wei, L., and Lipo, T.A.: A Novel Matrix Converter Topology withSiniple Commurarion. Record of the IEEE Industry Applications SocietyAnnual Meeting, Chicago, Sept. 30 -Oct. 4, Vol. 3, pp. 1749-1754 (2001).[31 Schafmeister, F., and Kolar, J.W.: Novel Modulation Schemes forConventional and Sparse Matru Converters Facilitating Reuctive PowerTransfer Independent ofA ctive Power Flow. Proceedings of the 3 AnnualIEEE Power Electronics Specialists Conference, Aschen, Germany, lune 21-24, Vol. 4, pp. 2917-2923 (2004).[4] Schafmeister, F., Baumann, M., and Kolar, J.W.: Analytically ClosedCulculafionof the C onduction and Switching Losses of Three-phase AC-ACSparse Mafrir Converters. CD-ROM of the 10th International PowerElectronics and Morion Control Conference, Sept. 9-11, Cavtat \Dubrovnik, Croatia 2002).[ 5 ] Kolar, J.W., Ertl, H., and Zsch, ,C.: Calcrtlution ofthe Pussive andActive Componenr Stresses of Three-phase PWM Converrzr Systems wiihHigh Puke Rare. Proceedings of the 3rd European Conference on PowerElectronics and Applicalions, Aachen, Germany, Oct. 9-12, Vol. 3, pp.[6] Huber, L., and Borojevic, D.: Spuce Vecror Modulated Three-phaseIo Three-Phme Matrix Conver fer wirh Input Power Facfor Correction.IEEE Transactions on lndustry Applications,Vol. 3 . No. 6, pp. 1234-1246(1995).[7] Wheeler, P.,Clare , J., Empringham, L., and Bland, M.: TechnalogVand Poienrial o Matrix Converters. Power Electronics Europe, No. 3, pp.[S] Holtz, J., and Boelkens, U,: Direct Frequency Converter wifhSinusoidal Line Currents for Speed-Variableac Motors. IEEE Transactionson Industrial Electronics, Vol. 36, No. 4, pp. 475-478 (1989).[9] Schafmeister, F., Herold, S.and Kolar, J.W.: Evaluation of l2UOV-Si-IGBTs and I3OOV-Sic-JFETs far Application in Three-phase VetySparse Molrir AC-dC CorrverferSyxrems. Proceedings of the I Bth AnnualIEEE Applied Power E lectronics Conference and Exposition, Miami Beach(Florida), USA, February9 - 13, Vol. I pp, 241 ~ 255 (2003).

Vol. 2, pp. 777 ~ 791 (2002).

1303-131 ( l989) .

2s-28 (2001).

88

Analytical Calculation of the Conduction and Switching Losses of The

Documents

Transcript of Analytical Calculation of the Conduction and Switching Losses of The