High Performance DrMOS – Integrated Power Stage performance by significantly reducing switching...

Vishay SiliconixSiC778A

Document Number: 63808S12-1132-Rev. B, 21-May-12

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This document is subject to change without notice.THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

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High Performance DrMOS – Integrated Power Stage

DESCRIPTIONThe SiC778 is an integrated power stage solution optimizedfor synchronous buck applications offering high current, highefficiency and high power density. Packaged in Vishay’sproprietary 6 mm x 6 mm MLP package, SiC778 enablesvoltage regulator designs to deliver in excess of 40 A perphase current with 91 % peak efficiency.The internal Power MOSFETs utilize Vishay’s state-of-the-artTrenchFET Gen III technology that delivers industrybench-mark performance by significantly reducing switchingand conduction losses.The SiC778 incorporates an advanced MOSFET gate driverIC that features high current driving capability, adaptivedead-time control, an integrated bootstrap Schottky diode,and a thermal warning (THDN) that alerts the system ofexcessive junction temperature. The driver is also compatiblewith a wide range of PWM controllers and supports tri-statePWM, 3.3 V (SiC778ACD) PWM logic, and skip mode(SMOD) to improve light load efficiency.

FEATURES • Thermally enhanced PowerPAK® MLP6x6-40L

package • Industry benchmark MOSFET with integrated

Schottky diode • Delivers in excess of 40 A continuous current • 91 % peak efficiency • High frequency operation up to 1 MHz • Power MOSFETs optimized for 12 V input stage • 3.3 V PWM logic with tri-state and hold-off • SMOD logic for light load efficiency boost • Low PWM propagation delay (< 20 ns) • Thermal monitor flag • Enable feature • VCIN UVLO • Compliant with Intel DrMOS 4.0 specification • Material categorization: For definitions of compliance

please see www.vishay.com/doc?99912

APPLICATIONS • Synchronous buck converters • Multi-phase VRDs for CPU, GPU, and memory • DC/DC POL modules

TYPICAL APPLICATION DIAGRAM

Figure 1: SiC778 Typical Application Diagram

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PIN CONFIGURATION

Figure 2 - SiC778 Pin Configuration (Bottom View)

PIN DESCRIPTION Pin Number Symbol Description

1 SMOD# LS FET turn-off logic. Active low

2 VCIN Supply voltage for internal logic circuitry

3 VDRV Supply voltage for internal gate driver

4 BOOT High side driver bootstrap voltage

5, 37, P1 CGND Analog ground for the driver IC

6 GH High side gate signal

7 PHASE Return path of HS gate driver

8 to 14, P2 VIN Power stage input voltage. Drain of high side MOSFET

15, 29 to 35, P3 VSWH Phase node of the power stage

16 to 28 PGND Power ground

36 GL Low side gate signal

38 THDN Thermal shutdown open drain output

39 DSBL# Disable pin. Active low

40 PWM PWM input logic


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Note: 1. Stresses beyond those listed under ’’Absolute Maximum Ratings’’ may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ORDERING INFORMATION Part Number Package Marking Code

SiC778ACD-T1-GE3 PowerPAK MLP66-40L SiC778A

SiC778DB Reference board

ABSOLUTE MAXIMUM RATINGS (1)

Electrical Parameter Symbol Limits Unit

Input Voltage VIN - 0.3 to 20

V

Control Input Voltage VCIN - 0.3 to 7

Drive Input Voltage VDRV - 0.3 to 7

Switch Node (DC) VSW - 0.3 to 20

Boot Voltage (DC Voltage) VBS - 0.3 to 27

Boot to Switching Node (DC Voltage) VBS_SW - 0.3 to 7

All Logic Inputs and Outputs (PWM, DSBL, SMOD and THDN) - 0.3 to VCIN + 0.3

Max. Operating Junction Temperature TJ 150

°CAmbient Temperature TA - 40 to 125

Storage Temperature - 65 to 150

RECOMMENDED OPERATING CONDITIONS Parameter Min. Typ. Max. Unit

Input Voltage (VIN) 4.5 18

V

Drive Input Voltage (VDRV) 4.5 5 5.5

Control Input Voltage (VCIN) 4.5 5 5.5

Switching Node (LX, DC Voltage) 19

BOOT-SW 4 4.5 5.5

THERMAL RESISTANCE RATINGS Parameter Min. Typ. Max. Unit

Thermal Resistance from Junction to Case (to P3 PAD VSWP signal) 2.5°C/W

Thermal Resistance from Junction to PCB 5

ELECTRICAL SPECIFICATIONS

Parameter Symbol

Test Conditions Unless Specified VDSBL# = 5 V, VSMOD = 5 V,

VIN = 12 V, VDRV = VCIN = 5 V, TA = 25 °C

Min.(2) Typ.(1) Max.(2) Unit

Power Supplies

Control Logic Input Current IVCIN

VDSBL# = 0 V, no switching 100

µAVDSBL# = 5 V, no switching 300

VDSBL# = 5 V, fs = 300 kHz, D = 0.1 300

Drive Input Current (Dynamic)

IVDRV

fs = 300 kHz, D = 0.1 16 25mA

fs = 1 MHz, D = 0.1 60

Drive Input Current (No Switching)VDSBL# = 0 V, no switching 30

µAVDSBL# = 5 V, no switching 60

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Notes:

1.Typical limits are established by characterization and are not production tested.

2.Min. and max. not 100 % production tested.

3.Guaranteed by design.

Bootstrap Supply

Bootstrap Switch Forward Voltage VF VCIN = 5 V, forward bias current 2 mA 0.4 V

PWM Control Input (SiC778ACD)

Rising Threshold Vth_pwm_r 2.1 2.4 2.8

V

Falling Threshold Vth_pwm_f 0.7 0.9 1.2

Tri-state Voltage Vtri PWM pin floating 1.8

Tri-state Rising Threshold Vth_tri_r 0.9 1.5

Tri-state Falling Threshold Vth_tri_f 1.9 2.2 2.6

Tri-state Rising Threshold Hysteresis Vhys_tri_r 225mV

Tri-state Falling Threshold Hysteresis Vhys_tri_f 275

PWM Input Current IPWMVPWM = 3.3 V 300

µAVPWM = 0 V - 300

Timing Specifications

Tri-State to GH/GL Rising Propagation Delay

TPD_R_Tri

No load, see fig. 4.

20

ns

Tri-state Hold-Off Time TTSHO 150

GH - Turn Off Propagation Delay TPD_OFF_GH 20

GH - Turn ON Propagation Delay(Dead Time Rising)

TPD_ON_GH 10

GL - Turn Off Propagation Delay TPD_OFF_GL 20

GL - Turn On Propagation Delay(Dead Time Falling)

TPD_ON_GL 10

DSBL# High to GH/GL Rising Propagation Delay

TPD_R_DSBL 22

DSBL# Low to GH/GL Falling Propagation Delay

TPD_F_DSBL 10

DSBL#, SMOD INPUT

DSBL# Logic Input Voltage VDSBLEnable 2

VDisenable 0.8

SMOD Logic Input Voltage VSMODHigh State 2

Low State 0.8

Protection

Under Voltage Lockout VUVLORising, On Threshold 3.7 4.3

VFalling, Off Threshold 2.7 3.2

Under Voltage Lockout Hysteresis

Note 3

550 mV

THDn Flag Set 160

°CTHDn Flag Clear 135

THDn Flag Hysteresis 25

THDn Output Low 0.02 V

ELECTRICAL SPECIFICATIONS

Parameter Symbol

Test Conditions Unless Specified VDSBL# = 5 V, VSMOD = 5 V,

VIN = 12 V, VDRV = VCIN = 5 V, TA = 25 °C

Min.(2) Typ.(1) Max.(2) Unit


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DETAILED OPERATIONAL DESCRIPTION PWM Input with Tri-state FunctionThe PWM input receives the PWM control signal from theVR controller IC. The PWM input is designed to becompatible with standard controllers using two state logic(H and L) and advanced controllers that incorporate tri-statelogic (H, L, and tri-state) on the PWM output. For two statelogic, the PWM input operates as follows. When PWM isdriven above Vth_pwm_r the low side is turned OFF and thehigh side is turned ON. When PWM input is driven belowVth_pwm_f the high side turns off and the low side turns on.For tri-state logic, the PWM input operates as above fordriving the MOSFETs. However, there is an third statethat is entered into as the PWM output of tri-statecompatible controller enters its high impedance state duringshut-down. The high impedance state of the controller'sPWM output allows the SiC778A to pull the PWM inputinto the tri-state region (see the tri-state VoltageThreshold diagram below). If the PWM input stays in thisregion for the tri-state hold-off period, tTSHO, both high sideand low side MOSFETs are turned off. This function allowsthe VR phase to be disabled without negative output voltageswing caused by inductor ringing and saves a schottky diodeclamp. The PWM and tri-state regions are separatedby hysteresis to prevent false triggering. The SiC778ACDincorporates PWM voltage thresholds that are compatiblewith 3.3 V logic.

Disable (DSBL#)In the low state, the DSBL# pin shuts down the driver ICand disables both high-side and low-side MOSFET. In thisstate, the standby current is minimized. If DSBL# isleft unconnected an internal pull-down resistor will pull thepin down to CGND and shut down the IC.

Diode Emulation Mode (SMOD) SkipWhen SMOD pin is low the diode emulation mode is enabledand GL is turned off. This is a non-synchronous conversionmode that improves light load efficiency byreducing switching losses. Conducted losses that occur insynchronous buck regulators when inductor currentis negative can also be reduced. Circuitry in the externalcontroller IC detects when inductor current crosses zero anddrive SMOD Lo turning the low side MOSFET off. See SMODoperation diagram for additional details. This function can bealso be used for a pre-biased output voltage. If SMOD is leftunconnected, an internal pull up resistor will pull the pin up toVCIN (logic high) to disable the SMOD function.

Thermal Shutdown Warning (THDN)The THDN pin is an open drain signal that flags thepresence of excessive junction temperature. Connect amaximum of 20 k to pull this pin up to VCIN. An internaltemperature sensor detects the junction temperature.The temperature threshold is 160 °C. When thisjunction temperature is exceeded the THDN flag is set.When the junction temperature drops below 135 °C thedevice will clear the THDN signal. The SiC778 does not stop

operation when the flag is set. The decision to shutdownmust be made by an external thermal control function.

Voltage Input (VIN)This is the power input to the drain of the high-sidepower MOSFET. This pin is connected to the highpower intermediate BUS rail.

Switch Node (VSWH and PHASE)The Switch node VSWH is the circuit PWM regulated output.This is the output applied to the filter circuit to deliverthe regulated high output for the buck converter. The PHASEpin is internally connected to the switch node VSWH. This pinis to be used exclusively as the return pin for the BOOTcapacitor. A 20.2 k resistor is connected between GH andPHASE to provide a discharge path for the HS MOSFET inthe event that VCIN goes to zero while VIN is still applied.

Ground Connections (CGND and PGND)PGND (power ground) should be externally connectedto CGND (control signal ground). The layout of theprinted circuit board should be such that the inductanceseparating the CGND and PGND should be a minimum.Transient differences due to inductance effects betweenthese two pins should not exceed 0.5 V.

Control and Drive Supply Voltage Input (VDRV, VCIN)VCIN is the bias supply for the gate drive control IC. VDRV isthe bias supply for the gate drivers. It is recommended toseparate these pins through a resistor. This creates a lowpass filtering effect to avoid coupling of high frequency gatedrive noise into the IC.

Bootstrap Circuit (BOOT)The internal bootstrap switch and an external bootstrapcapacitor form a charge pump that supplies voltage to theBOOT pin. An integrated bootstrap diode is incorporated sothat only an external capacitor is necessary to complete thebootstrap circuit. Connect a boot strap capacitor with one legtied to BOOT pin and the other tied to PHASE pin.shoot-through protection and adaptive dead time

Shoot-Through Protection and Adaptive Dead Time(AST)The SiC778A has an internal adaptive logic to avoid shootthrough and optimize dead time. The shootthrough protection ensures that both high-side and low-sideMOSFET are not turned on the same time. The adaptivedead time control operates as follows. The HS and LS gatevoltages are monitored to prevent the one turning on until theother’s gate voltage is sufficiently low (1 V), that and built indelays ensure the one power MOS is completely off, beforethe other can be turned on. This feature helps to adjust deadtime as gate transitions change with respect to output currentand temperature.

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Under Voltage Lockout (UVLO)During the start up cycle, the UVLO disables the gate driveholding high-side and low-side MOSFET gate low until theinput voltage rail has reached a point at which thelogic circuitry can be safely activated. The SiC778A also

incorporates logic to clamp the gate drive signals to zerowhen the UVLO falling edge triggers the shutdown ofthe device. As an added precaution, a 20.2 k resistoris connected between GH and PHASE to providea discharge path for the HS MOSFET.

FUNCTIONAL BLOCK DIAGRAM

Figure 3: SiC778 Functional Block Diagram

DEVICE TRUTH TABLE DSBL# SMOD PWM GH GL

Open X X L L

L X X L L

H L L L L

H L H H L

H H H H L

H H L L H

H L Tri-state L L

H H Tri-state L L



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DEFINITION OF PWM LOGIC AND TRI-STATE

SMOD OPERATION DIAGRAM

Figure 4: Definition of PWM Logic and Tri-state

Figure 5: CCM Operation with SMOD# = High

PWM

GH

IL

GL

0V

SMOD#

0A

Figure 6: DCM Operation with SMOD# = Active Toggle

PWM 0V

GH

IL

GL

0A

SMOD#

10nS

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ELECTRICAL CHARACTERISTICS

Start-up with VIN Ramping upVIN = 12 V, VOUT = 1.2 V, fSW = 500 kHz

Start-up with DSBL# Toggle HighVIN = 12 V, VOUT = 1.2 V, fSW = 500 kHz

Start-up with PWM existing Tri-stateVIN = 12 V, VOUT = 1.2 V, fSW = 500 kHz

Power Off with VIN Ramping downVIN = 12 V, VOUT = 1.2 V, fSW = 500 kHz

Shut-down with DSBL# Toggle LowVIN = 12 V, VOUT = 1.2 V, fSW = 500 kHz

Shut-down with PWM entreing Tri-stateVIN = 12 V, VOUT = 1.2 V, fSW = 500 kHz



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Start-up with VDRV/VCIN Ramping UpVIN = 12 V, VOUT = 1.2 V, fSW = 500 kHz

Switching waveform at PWM Rising Edge VIN = 12 V, VOUT = 1.2 V, fSW = 500 kHz, IOUT = 0 A

Switching Waveform at PWM Rising EdgeVIN = 12 V, VOUT = 1.2 V, fSW = 500 kHz, IOUT = 30 A

Power Off with VDRV/VCIN Ramping DownVIN = 12 V, VOUT = 1.2 V, fSW = 500 kHz, IOUT = 1.2 A

Switching Waveform at PWM Falling EdgeVIN = 12 V, VOUT = 1.2 V, fSW = 500 kHz

Switching Waveform at PWM Falling Edge VIN = 12 V, VOUT = 1.2 V, fSW = 500 kHz, IOUT = 30 A

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Typical EfficiencyVIN = 12 V, VOUT = 1.2 V, VDRV = VCIN; No Air Flow,

O/P Inductance = 0.33 µH

76

78

80

82

84

86

88

90

92

94

0 3 6 9 12 15 18 21 24 27 30 33

Effic

ienc

y (%

)

Output Load (A)

Fsw = 300KHz Fsw = 400KHz Fsw = 500KHz

Typical Power LossVIN = 12 V, VOUT = 1.2 V, VDRV = VCIN; No Air Flow,

O/P Inductance = 0.33 µH

0

2

4

6

8

10

0 3 6 9 12 15 18 21 24 27 30 33

Pow

er lo

ss (W

)

Output Load (A)

Fsw = 300KHz Fsw = 400KHz Fsw = 500KHz



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PACKAGE DIMENSIONS

Notes:1. Use millimeters as the primary measurement.

2. Dimensioning and tolerances conform to ASME Y14.5M-1994.

3. N is the number of terminals.Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction .

4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip.

5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body .

6. Exact shape and size of this feature is optional.

7. Package warpage max. 0.08 mm.

8. Applied only for terminals.

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

reliability data, see www.vishay.com/ppg?63808.

DIMMILLIMETERS INCHES

Min. Nom. Max. Min. Nom. Max.

A(8) 0.70 0.75 0.80 0.027 0.029 0.031

A1 0 - 0.05 0 - 0.002

A2 0.20 ref. 0.008 ref.

b(4) 0.20 0.25 0.30 0.078 0.098 0.011

D 6.00 BSC 0.236 BSC

e 0.50 BSC 0.019 BSC

E 6.00 BSC 0.236 BSC

L 0.35 0.40 0.45 0.013 0.015 0.017

N (3) 40 40

Nd (3) 10 10

Ne (3) 10 10

D2-1 1.45 1.50 1.55 0.057 0.059 0.061

D2-2 1.45 1.50 1.55 0.057 0.059 0.061

D2-3 2.35 2.40 2.45 0.095 0.094 0.096

E2-1 4.35 4.40 4.45 0.171 0.173 0.175

E2-2 1.95 2.00 2.05 0.076 0.078 0.080

E2-3 1.95 2.00 2.05 0.076 0.078 0.080

K1 0.73 BSC 0.028 BSC

K2 0.21 BSC 0.008 BSC

40

12 x

2 x

Pin 1 dotby marking

MLP66-40(6 mm x 6 mm)

10

1120

21

30

31

5 6

4

Top View Bottom ViewSide View

A

B

C

D

0.10 C B

E

0.10 C A A 0.08 C

A1

A20.41

K2

K1

D2-1 Pin #1 dent

E2-

1

e

D2-3 D2-2

E2-

3E

2-2

(Nd-

1)X

e

ref

.

(Nd-1)X e ref.

0.10

M

C A

B

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Package Informationwww.vishay.com Vishay Siliconix

Revision: 12-Jan-15 1 Document Number: 64846For technical questions, contact: [email protected]

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

PowerPAK® MLP66-40 Case Outline

Notes1. Use millimeters as the primary measurement

2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994

3. N is the number of terminals. Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction

4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip

5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body

6. Exact shape and size of this feature is optional

7. Package warpage max. 0.08 mm

8. Applied only for terminals

DIM.MILLIMETERS INCHES

MIN. NOM. MAX. MIN. NOM. MAX.

A (8) 0.70 0.75 0.80 0.027 0.029 0.031

A1 0.00 - 0.05 0.000 - 0.002

A2 0.20 ref. 0.008 ref.

b (4) 0.20 0.25 0.30 0.078 0.098 0.011

D 6.00 BSC 0.236 BSC

e 0.50 BSC 0.019 BSC

E 6.00 BSC 0.236 BSC

L 0.35 0.40 0.45 0.013 0.015 0.017

N (3) 40 40

Nd (3) 10 10

Ne (3) 10 10

D2-1 1.45 1.50 1.55 0.057 0.059 0.061

D2-2 1.45 1.50 1.55 0.057 0.059 0.061

D2-3 2.35 2.40 2.45 0.095 0.094 0.096

E2-1 4.35 4.40 4.45 0.171 0.173 0.175

E2-2 1.95 2.00 2.05 0.076 0.078 0.080

E2-3 1.95 2.00 2.05 0.076 0.078 0.080

K1 0.73 BSC 0.028 BSC

K2 0.21 BSC 0.008 BSC

ECN: T14-0826-Rev. B, 12-Jan-15DWG: 5986

40

12 x

2 x

Pin 1 dotby marking

MLP66-40(6 mm x 6 mm)

10

1120

21

30

31

5 6

4

Top View Bottom ViewSide View

A

B

C

D

0.10 C B

E

0.10 C A A 0.08 C

A1

A20.41

K2

K1

D2-1

E2-

1

e

D2-3 D2-2

E2-

3E

2-2

(Nd-

1)X

e

ref

.

(Nd-1)X e ref.

0.10

M

C A

B

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Revision: 08-Feb-17 1 Document Number: 91000

DisclaimerALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.

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High Performance DrMOS – Integrated Power Stage performance by significantly reducing switching...

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