Analysis of Intrinsic Charge Loss Mechanisms for Nanoscale NAND Flash...

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 15, NO. 3, SEPTEMBER 2015 319

Analysis of Intrinsic Charge Loss Mechanismsfor Nanoscale NAND Flash MemoryJun Yeong Lim, Student Member, IEEE, Pyung Moon, Student Member, IEEE,

Sang Myung Lee, Student Member, IEEE, Keum-Whan Noh, Tae-Un Youn,Jong-Wook Kim, and Ilgu Yun, Senior Member, IEEE

Abstract—In the current memory market, many researchershave analyzed the data retention characteristic and predictedthe related leakage mechanism. Most studies have shown thatthe dominant degradation of retention characteristics of Flashmemory occurs in the tunneling oxide after program/erase cycling.However, serious degradation of the retention characteristics isalso seen in the intrinsic situation before program/erase cycling ofdevices through the oxide–nitride–oxide (ONO) interpoly dielec-tric. In this paper, we analyze that degradation by examining thevarious charge loss mechanisms of the device before cycling andextract two appropriate charge loss mechanisms by comparingthe measured Vth data with the TCAD simulation data, and weverify the mechanisms by extracting the activation energy of eachmechanism. We also analyze the effects on those two mechanismsas the ONO thickness and temperature are changed. Based on theresults, we establish the intrinsic leakage mechanism through theONO layers and predict the change in leakage mechanism asthe thickness of the ONO layers is decreased.

Index Terms—Activation energy, charge loss, NAND flash,program/erase cycling, degradation, TCAD.

I. INTRODUCTION

A S nonvolatile NAND flash memory has been scaled down,retention has become a more serious problem due to

the charge loss of the floating gate due to interference withthe close cell and leakage through the tunneling oxide oroxide–nitride–oxide (ONO) inter-poly dielectric (IPD) [1], [2].This has long been a significant problem for memory devicesbecause it is impossible to determine the exact leakage mecha-nism of charge loss in the low-electric field region, which is theretention state, due to the limitations of instrument resolution ofmeasurement. Accordingly, active analyses of the degradation

Manuscript received December 1, 2014; revised May 7, 2015; acceptedMay 13, 2015. Date of publication May 25, 2015; date of current versionSeptember 1, 2015. This work was supported in part by SK Hynix, by IC DesignEducation Center, and by the Institute of BioMed IT, Energy IT and Smart ITTechnology (BEST), a Brain Korea 21 plus program, Yonsei University.

J. Y. Lim, P. Moon, S. M. Lee, and I. Yun are with the Department ofElectrical and Electronic Engineering, Yonsei University, Seoul 120-749, Korea(e-mail: [email protected]).

K.-W. Noh, T.-U. Youn, and J.-W. Kim are with the Research and Devel-opment Division, SK Hynix Semiconductor Inc., Chungcheongbuk 361-725,Korea.

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TDMR.2015.2437364

TABLE ISAMPLE THICKNESSES OF ONO LAYERS

of the retention characteristic through insulators have been per-formed for various stress conditions and using various methods,including the floating gate technique [3], fitting of the standardequation of Vth [4], and Arrhenius law [5].

Until now, researchers have generally given priority to thedegradation of tunneling oxide after baking and cycling, be-cause the basic principle of flash memory is using the tunnelingthrough the tunneling oxide [6]. However, it is also important toanalyze the generated charge loss through the ONO layers [7]before program/erase cycling, since it is continuously generatedat the operating device together with the charge loss through thetunneling oxide after program/erase cycling.

Therefore, in this paper, the conduction mechanisms at theretention state that induced the degradation of the charge lossof the device before cycling will be studied by comparing themeasured Vth data with the TCAD simulation data, which ismore reliable and exact than the methods described above. Inaddition, the variations in retention characteristics of devicesas changing thickness of ONO or temperature are also studiedusing the leakage mechanisms at TCAD.

II. EXPERIMENT

The test structure was fabricated on a 12-inch wafer using thenano-scale NAND Flash process by SK Hynix SemiconductorInc. The tunneling oxide was grown on a Si-substrate, and thetest structure of the IPD was constructed with an ONO stacksandwiched with two heavily doped poly-Si layers acting as thefloating gate and the control gate. The silicon oxide (bottom),silicon nitride, and silicon oxide (top) of the ONO stack weregrown sequentially by LPCVD [8]. Based on these processes, wefabricated three test samples with different equivalent–oxide–thickness (EOT) of the ONO, as shown in Table I. Here, the sam-ple S1 had the smallest EOT, sample S3 had the largest EOT,and the EOT of sample S2 was between those of S1 and S3.

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320 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 15, NO. 3, SEPTEMBER 2015

Fig. 1. Data retention characteristics at various charge’s state of the floatinggate at room temperature [8].

Based on this structure, we measured the intrinsic retentioncharacteristics of the multi-layer cell (MLC) NAND flash mem-ory at baking temperatures of 300 K, 365 K, 400 K, and 425 Kand various ONO thicknesses. These cells on wafer were equallyprogrammed at initial stage. Fig. 1 shows the charge loss of theMLC NAND flash cells of the device before cycling [8].

Among the MLC states, the PV3 state generated more tailbits after baking at room temperature than the PV1 and PV2states because of its larger internal electric field induced bythe large amount of stored charge. Therefore, we analyzed theintrinsic retention characteristic of the PV3 state, which has thelargest number of tail bits.

The average value of ΔVth of 4000 tail bits was extracted asthe baking temperature changed, and we measured the ΔVth atseveral retention times. The TCAD structure was designed tobe similar to a real cell using the sentaurus TCAD workbench[9], as shown in Fig. 2. We inserted charges to the floating gatebased on the measured data and modeled the intrinsic retentioncharacteristic by analyzing the degradation of Vth according totime for various leakage mechanisms.

III. RESULTS AND DISCUSSION

Fig. 3 shows the degradation of Vth of the intrinsic cells ofthe PV3 state versus bake time. It is generally known that thedegradation of Vth is due to defects in the tunneling oxide afterprogram/erase cycling [10], [11].

However, the charge loss of the device before cycling isdifferent with the device after cycling. Fig. 4 shows the averageand the standard deviation of ΔVth on tail bits when thethicknesses of the tunneling oxide and ONO are changed. It isobserved that the effect of charge loss by varying the thicknessof tunneling oxide is negligible as shown in Fig. 4(a). However,the effect of charge loss by varying the ONO thickness, it isfound that ΔVth increases as the EOT of ONO decreases asshown in Fig. 4(b). It indicates that the charge loss of the devicebefore cycling in retention mode is generated through the ONO

Fig. 2. The simulation structure of the FG NAND flash memory for TCAD.

Fig. 3. Intrinsic retention characteristic of sample S1 according to the baketime at various temperatures.

layer. Therefore, the degradation in Fig. 3 indicates leakagethrough the ONO layers [7].

In addition, the reason why leakage currents only take placethrough the IPD layers even though the thickness of the tun-neling oxide is thinner than IPD layers is due to the stackedstructure of IPD layer. In the measurement process of retentioncharacteristic of the floating gate (FG) flash memory devices,FG only has voltage corresponding to the stored charges. There-fore, in IPD layers between FG and the control gate (CG),it is found that almost no voltage applied to the CG, which

LIM et al.: CHARGE LOSS MECHANISMS FOR NANOSCALE NAND FLASH MEMORY 321

Fig. 4. The effect of (a) tunneling oxide and (b) inter-poly dielectric layers tothe charge loss of device.

correspondingly represented to the top oxide and mid nitridelayers altogether. Then, it indicates that the electric field isonly applied to the bottom oxide layer between FG and nitridelayer. Therefore, this electric field is larger than the electric fieldapplied to the tunneling oxide between FG and the substratebecause the thickness of bottom oxide alone in IPD layers isthinner than the tunneling oxide. Thus, it is concluded that thecharge loss is generated mainly through the IPD layers not thetunneling oxide.

The degradation of Vth can be divided into the rapid chargeloss at the initial transient time period and the consistent chargeloss for the steady-state time period [4]. The rapid charge lossat the initial time period is usually explained by the interface-states annealing or recovery [12], [13]. The generated electron-hole pairs during program/erase or native defects are detrappedat the trap sites, and then these make the rapid Vth shift atthe initial time period. However, it is shown that the shiftgradually saturates to the specific level because recovery ofinterface traps or native defects have the limitation when thetrap sites and defects are reached to the steady-state after aspecific time elapses. Therefore, it just affects the entire Vth

shift as much as a specific quantity. However, in case of the

Fig. 5. The retention characteristic of sample S3 modeled by the trap-assistedtunneling mechanism at 425 K.

consistent charge loss, the charge loss is gradually generatedalong the time through the leakage mechanisms. Therefore, itis more feasible to analyze the consistent retention character-istic of device than the rapid charge loss of interface traps.In addition, the Vth shift at the initial time period is easilyvaried due to the trap recovery, native defects, and gener-ated electron-hole pair during fabrication and program/erase.As shown in Fig. 3, we divide the total charge loss ΔVth intotwo phases based on the 12 hours. The 1st phase representsthe rapid charge loss of Vth and the 2nd phase represents theconsistent charge loss and we intensively analyzed the mech-anisms of the 2nd phase charge loss. Additionally, 12 hoursis enough time for interface traps and defects to become asteady state [14], so we can determine that the remainingVth shift which is second phase does not have the recoverycharacteristics.

Fig. 5 shows the adjusted floating gate voltage (Vfg) of thesecond phase shift with respect to bake time. The floating gatevoltage has a linear relation with threshold voltage, becauseboth terms are related to the stored charge in a device [15], [16].

Fowler–Nordheim (FN) tunneling, direct tunneling, ohmicemission, trap-assisted tunneling (TAT) and Poole–Frenkel (PF)mechanisms [17], which are conduction mechanisms throughan insulator, are selected as possible candidates to explain thecharge loss mechanism, and they were simulated using TCAD[9]. To date, the leakage mechanism for a low-electric field wasgenerally explained using one dominant mechanism [4], [10],[18]. In the case of sample S3, which has the thickest EOT ofONO, the ΔVth degradation at 425 K is sufficient to note thatthe dominant mechanism of the sample is TAT, as shown inFig. 5. This means that the stored charges of the device beforecycling also leak through the defect or the trap from the FG tothe ONO layers [4].

However, a single mechanism cannot completely explain thedegradation in sample S1 and sample S2, which had thinnerEOT of the ONO than sample S3. As illustrated in Fig. 6,when we model the retention characteristic using just the TATmechanism, it is difficult to model ΔVth due to the excessive


Fig. 6. Comparing the suggested mechanism and TAT on sample S2 at 425 K.

Fig. 7. The simulation results using the suggested mechanism on sample S1for the bake time of 300 K, 365 K, and 425 K.

charge loss of the FG. However, the charge loss for the thinnerEOT of the ONO can be explained by the combination of twomechanisms, TAT and PF, as presented in (1), and the combinedmechanisms agree with the measured data when the bakingtemperature is changed from 300 K to 425 K, as shown in Fig. 7.However, when we inserted mechanisms, except TAT and PFmechanisms, it is unable to fit Vth loss data. For example, incase of the Fowler–Nordheim mechanism, Vth loss induced isvery small because it has small current at the low electric fieldregion even if it has large current at high electric field region,so it is unsuitable to the measured data. In case of the ohmicemission and direct tunneling, it is also unsuitable because thegenerated Vth loss is too small

ΔVth,Total = ΔVth,TAT +ΔVth,PF (1)

where ΔVth,TAT is induced by the trap-assisted tunnelingmechanism, ΔVth,PF is induced by the Poole–Frenkel mecha-

Fig. 8. The variations in the portion of PF and TAT according to EOT at300 K, 365 K, 400 K, and 425 K.

nism [17]. We derive the results by adjusting the trap parameterof each mechanism in the simulation. The parameter of TATmechanism is empty trap density, and the parameter of PF isfilled trap density.

Fig. 8 shows that how much portion each mechanism occu-pies in the fixed quantity of ΔVth,Total according to the EOT ofONO layer and temperature.

At first, when the EOT of ONO layer changes, it is shownthat the portion of each mechanism is considerably changed.As shown in Fig. 8, the thickest sample S3 has a higher portionof TAT and a lower portion of PF. On the other hand, sampleS1 has a lower portion of TAT and a higher portion of PF thanthe others. The reason why the portion of each mechanism ischanged with varying the thickness is due to the change ofinside region of IPD. As the thickness of IPD is increased,both the empty trap and filled trap sites inside the region ofIPD are also increased due to the thicker IPD region than thinIPD region. Furthermore, in case of before cycling, the thickerIPD region has larger empty trap density than filled trap densitybecause the step of UV process before initial program or eraseemits all trapped charges from the intrinsically filled trap sites.Therefore, the portion of TAT mechanism which uses the emptytrap density grows when the thickness of IPD increases andit is the reason why the leakage mechanism of a low-electricfield was generally explained using one dominant mechanismin past devices [4], which had thicker ONO than currentdevices. Therefore, to reduce the EOT to satisfy the markettrends, the PF mechanism as well as TAT mechanism becomesinfluential mechanism with regard to the charge loss of thefloating gate.

Secondly, the effect of temperature to the charge loss isexamined. Fig. 9 shows the normalized ratio of ΔVth for bothmechanisms at each temperature for samples S1 and S2. The ra-tio indicates the induction of ΔVth compared with that at 300 Kfor each mechanism. As shown in Fig. 9, the ratio of the TATmechanism increases only slightly as temperature increases,while the ratio of the PF mechanism has a larger variation thanTAT mechanism. In other words, as the temperature increases,


Fig. 9. The ratio of TAT and PF mechanisms according to temperature for samples (a) S1 and (b) S2.

Fig. 10. Arrhenius plots of samples (a) S1 and (b) S2 with Ea values of TAT and PF mechanisms using the simulation results.

the portion of the PF mechanism increases, but the portion ofthe TAT mechanism relatively decreases. The reason why theportion of each mechanism is changed with varying tempera-ture is related with the temperature parameter of PF mechanism.Current density of PF mechanism exponentially depend onthe temperature parameter and it is related with time constant(τ) of trap sites. The time constant of PF decreases whentemperature goes up and it makes easier for charges to emitthe filled trap sites. However, the time constant of TAT has onlydependency with not temperature but the distance between twointerfaces [19]. Accordingly, the PF portion increases relativelythat of TAT. This indicates that PF, which uses the thermalexcitation gradually, becomes an important factor with TAT astemperature increases in the intrinsic characteristic of NAND

flash memory. Of course, in TAT, the current density alsoincreases due to the shallow trap sites add to the mechanism.However, it is relatively low because the effect of temperatureto the PF is exponential function.

Based on these simulation results, we have drawn Arrheniusplots, as shown in Fig. 10. The activation energy values of PFusing 1/T model are very similar to the standard value [20].However, in case of TAT, it is a little impractical extractionof activation energy by just using a single line because theArrhenius plot represents the curved line which has differentactivation energy at low and high temperature since the activa-tion energy increases with temperature. It is generally explainedusing deep and shallow traps. In general, the deep traps whichalign with the average energy level of the electrons in theFG contribute to loss of stored charges [12]. As temperatureincreases, shallow traps which have strong temperature accel-eration gradually attend to the leakage characteristic and moretraps can be used for the conductive traps to TAT mechanism[7], [19]. Therefore, the Vth degradation is generated faster thanat the situation of low temperature due to the characteristic ofTAT mechanism. Finally, the roll-off Ea is generated at hightemperature like a T model [5], [7].


IV. CONCLUSION

In this paper, we proposed the intrinsic charge loss mecha-nisms for the nano-scale FG NAND flash memory. We foundthat the degradation characteristic of the nano-scale devicescannot be sufficiently explained by only one mechanism as thescaling down was progressed. The combination of the TAT andPF mechanisms satisfactorily explained the charge loss of thefloating gate according to the bake time at various temperaturesand thicknesses. The portion of each mechanism changed inaccordance with the temperature and the EOT of the ONO. Asthe temperature increased, the portion of PF increased basedon the time constant characteristic of each mechanism. As theEOT of the ONO decreased, the PF mechanism also becamean important leakage factor of the retention characteristic withthe TAT mechanism. Therefore, for the nano-scale FG NAND

flash memory or even modern 3D NAND flash memory, thesedata trends allow more accurate prediction of the retentioncharacteristic of memory cells.

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Jun Yeong Lim (S’11) received the B.S. degreein electrical and electronic engineering from YonseiUniversity, Seoul, Korea, where he is currently work-ing toward the joint M.S./Ph.D. degree in electricaland electronic engineering.

His research interests include characterization,modeling, and simulation of semiconductor devicesand statistical modeling of semiconductor devicesusing technology computer-aided design.

Pyung Moon (S’07) received the B.S. and M.S.degrees in electrical and electronic engineering in2007 and 2009, respectively, from Yonsei University,Seoul, Korea, where he is currently working towardthe Ph.D. degree with the Department of Electricaland Electronic Engineering.

His research interests include nonlinear modelingand statistical variations of semiconductor processesand characterization of high-k dielectrics.

Sang Myung Lee (S’13) received the B.S. degree inelectronic communication engineering in 2013 fromHanyang University, Seoul, Korea, where he is cur-rently working toward the joint M.S./Ph.D. degree inelectrical and electronic engineering.

His research interests include characterization,modeling, and simulation of semiconductor devicesand statistical modeling of semiconductor devicesusing technology computer-aided design.

Keum-Whan Noh received the Ph.D. degree fromSeoul National University, Seoul, Korea, in 1999.

He joined SK Hynix Semiconductor Inc.,Chungcheongbuk, Korea, in 2000. His main researchactivities focus on the reliability of Flash memorycell.


Tae-Un Youn received the B.S. degree from InhaUniversity, Incheon, Korea, in 1998.

He joined SK Hynix Semiconductor Inc.,Chungcheongbuk, Korea, in 1998. He is currentlyparticipating in the Flash memory reliability.

Jong-Wook Kim received the M.S. degree fromSeoul National University, Seoul, Korea, in 2010.

He joined SK Hynix Semiconductor Inc.,Chungcheongbuk, Korea, in 2010. He is currentlyparticipating in the Flash memory reliability.

Ilgu Yun (SM’03) received the B.S. degree in elec-trical engineering from Yonsei University, Seoul,Korea, in 1990 and the M.S. and Ph.D. degreesin electrical and computer engineering from theGeorgia Institute of Technology, Atlanta, GA, USA,in 1995 and 1997, respectively.

He was previously a Research Fellow at the Mi-croelectronics Research Center, Georgia Institute ofTechnology, during 1997–1999; a Senior ResearchStaff at the Electronics and Telecommunications Re-search Institute, Daejeon, Korea, during 1999–2000;

and a Visiting Scholar at the Department of Industrial and ManufacturingEngineering, University of Wisconsin-Milwaukee, Milwaukee, WI, USA, dur-ing 2006–2007. He is currently a Professor of electrical and electronic en-gineering at Yonsei University. He was an Associate Dean of InternationalAffairs for the College of Engineering, Yonsei University. He is currentlywith the Department Head of Electrical and Electronic Engineering, YonseiUniversity. His research interests include material characterization, statistical(and nonlinear) modeling and variations of semiconductor processes, devices,and IC modules and process modeling, control, and simulation applied tocomputer-aided manufacturing of integrated circuits.

Prof. Yun is currently an Educational Activity Chair in the IEEE SSCSSeoul Chapter and an Editor of the Korean Electrical and Electronic MaterialEngineers (KIEEME) and the Institute of Electronics Engineers in Korea(IEEK).

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