Analog Integrated Circuits - iczhiku.com

Analog Integrated Circuits

Jieh-Tsorng Wu

6 de febrero de 2003

1. Introduction

2. PN Junctions and Bipolar Junction Transis-tors

PN Junctions

Small-Signal Junction Capacitance

Large-Signal Junction Capacitance

PN Junction in Forward Bias

PN Junction Avalanche Breakdown

PN Junction Breakdown

Bipolar Junction Transistor (BJT)

Minority Carrier Current in the Base Region

Gummel Number (G)

Base Transport Current

Forward Current Gain

BJT DC Large-Signal Model in Forward-Active Region

Dependence of BF on Operating Condition

Collector Voltage Effects

Base Transport Model

Ebers-Moll Model

Leakage Current

Common-Base Transistor Breakdown

Common-Emitter Transistor Breakdown

Small-Signal Model of Forward-Biased BJT

Charge Storage

Complete Small-Signal Model with ExtrinsicComponents

Typical values of Extrinsic Components

3. MOS Transistors

MOS Transistors

Strong Inversion

Channel Charge Transfer Characteristics

Simplified Channel Charge Transfer Charac-teristics

MOST I-V Characteristics

Threshold Voltage

Square-Law I-V Characteristics

Channel-Length Modulation

MOST Small-Signal Model in Saturation Re-gion

OST Small-Signal Model in Saturation Re-gion

MOST Small-Signal Capacitances in Satura-tion Region

Channel Capacitance in Saturation Region

Complete MOST Small-Signal Model in Sat-uration Region

MOST Small-Signal Model in Triode Region

MOST Small-Signal Model in Cutoff Region

Carrier Velocity Saturation

Effects of Carrier Velocity Saturation

1

Hot Carriers

Short-Channel Effects

Subthreshold Conduction in MOST

4. Integrated Circuit Technologies

Integrated-Circuit NPN Transistor

Lateral PNP Transistor

Vertical PNP Transistors

Advanced-Technology NPN Transistor

Base and Emitter Diffused Resistors

Base Pinch Resistor

Epitaxial Resistor

Properties of IC Resistor

Capacitors

Diodes

CMOS Integrated-Circuit Technologies

MOS Transistors

Parasitic BJTs in CMOS Technologies

Resistors in CMOS Technologies

Capacitors in CMOS Technologies

Matching Issues

Guidelines for Better Device Matching

Transistor Pair Layout Example

Resistor Pair Layout Example

Capacitor Pair Layout Example

Capacitor Errors

Capacitor Layout Design

Analog Section Floor Plan Example

Noise-Coupling Layout Considerations

Latch-Up in CMOS Technologies

5. Single-Transistor Gain Stages

Unilateral Two-Port Network

Common-Emitter Configuration

Common-Emitter Configuration - Bias Analy-sis

Common-Emitter Configuration - Small-Signal Analysis

Common-Source Amplifier

Common-Source Configuration - Small-Signal Analysis

Common-Emitter Configuration Small-SignalAC Analysis

Common-Source Configuration Small-SignalAC Analysis

Miller Approximation

Miller Approximation Equivalent Circuit

Short-Circuit Current Gain

BJT Transition Frequency

MOST Transition Frequency

MOST Transition Frequency - Weak Inversion

Complete AC Analysis of Common-Emitter(Source) Amplifier


Common-Emitter Amplifier with Emitter De-generation

Common-Emitter Amplifier with Emitter De-generation

Common-Source Amplifier with Source De-generation

Common-Base Configuration

Common-Base Configuration AC Analysis

Common-Gate Configuration

Common-Gate Configuration AC Analysis

Common-Collector Configuration (EmitterFollower)

Emitter Follower’s Voltage Gain

Emitter Follower’s Input Impedance

Emitter Follower’s Output Impedance

Common-Drain Configuration (Source Fol-lower)

Source Follower’s Gate Voltage Gain

Source Follower’s Gate Input Impedance

Source Follower’s Output Impedance

Source Follower’s Complete Frequency Re-sponse

Compensated Source Follower

Floating-Well Source Follower

6. Multiple-Transistor Gain Stages

Dominant-Pole Approximation

Zero-Value Time Constants

Zero-Value Time Constant Example

Darlington Configuration

BJT Cascode Configuration

BJT Cascode Characteristics

MOST Cascode Configuration

MOST Cascode Low-Frequency Characteris-tics

MOST Cascode Zero-Value Time ConstantAnalysis

MOST Cascode AC Characteristics

Active Cascode Configuration

Active Cascode Characteristics

Super Source Follower Configuration

7. Differential Gain Stages

Emitter-Coupled Pair

Emitter-Coupled Pair Large-Signal Behavior

Emitter-Coupled Pair with Emitter Degenera-tion

Source-Coupled Pair

Source-Coupled Pair Large-Signal Behavior

Small-Signal Analysis of Differential Ampli-fiers

Emitter-Coupled Pair Differential-Mode HalfCircuit

Emitter-Coupled Pair Common-Mode HalfCircuit

Emitter-Coupled Pair Input Resistances

Emitter-Coupled Pair Frequency Response

Emitter-Coupled Pair Input Offset Voltage andCurrent

Emitter-Coupled Pair Input Offset Voltage

Source-Coupled Pair Input Offset Voltage

Unbalanced Resistor Circuit Analysis

Unbalanced gm Circuit Analysis

Unbalanced Differential Amplifier

Simplified Analysis for Unbalanced Differen-tial Amplifier

8. Current Mirrors and Active Loads

Simple BJT Current Mirror

Simple BJT Current Mirror with Beta Helper

Simple BJT Current Mirror with Emitter De-generation

Matching Consideration in BJT Current Mir-rors

Simple MOST Current Mirror

Matching Consideration in Simple MOSTCurrent Mirror

Layout Considerations

BJT Cascode Current Mirror

MOST Cascode Current Mirror

MOST High-Swing Cascode Current Mirror

MOST Sooch Cascode Current Mirror

MOST Low-Voltage High-Swing CascodeCurrent Mirror

S¨ackinger Current Mirror

Gatti Current Mirror

BJT Wilson Current Mirror

MOST Wilson Current Mirror

Complementary Current Source Load

Current Mirror Load

Diode-Connected Load

9. Voltage and Current References

Sensitivity and Temperature Coefficient

Simple Current Sources

BJT Widlar Current Source

MOST Widlar Current Source

BJT Peaking Current Source

MOST Peaking Current Source

BJT VBE Referenced Current Source

MOST Vt Referenced Current Source

Self-Biasing BJT VBE Reference

Self-Biasing BJT VBE Reference with Start-Up Circuit

Self-Biasing BJT UT Reference

Self-Biasing MOST Vt Referenced CurrentSource

Self-Biasing MOST gm Referenced CurrentSource

Self-Biasing MOST VBE and UT ReferencedCurrent Source

Band-Gap References

Kujik Band-Gap References

Ahuja Band-gap Reference

Brokaw Band-Gap References

Widlar Band-Gap Reference

Song Band-Gap Reference

Band-Gap Reference Output Issues

10. Output Stages

Output Stage Requirements

Output Stage Design Issues

Nonlinearity and Harmonic Distortion

Class-A BJT Emitter Follower

Class-A BJT Emitter Follower Output Power

Instantaneous Power Dissipation

Class-A MOST Source Follower

Distortion in the MOST Source Follower

Class-A BJT Common-Emitter Stage

Distortion in Class-A BJT Common-EmitterStage

Class-A MOST Common-Source Stage

Class-B Push-Pull Emitter Follower

Output Power of Class-B Push-Pull EmitterFollower

Class-AB Push-Pull Emitter Followers

Class-AB Push-Pull Source Followers

Class-AB Push-Pull Common-Source Stage

Class-AB Quasi-Complementary Configura-tion

An Error Amplifier Example

Combined Common-Drain Common-SourceConfiguration

Parallel Common-Source Configuration

11. Noise Analysis and Modelling

Noise in Time Domain

Probability Density Function

Noise in Frequency Domain

Filtered Noise

Noise Summation

Piecewise Integration of Noise

Thermal Noise

Thermal Noise with Loading

Shot Noise

Flicker Noise (1/f Noise)

BJT Noise Model

FET Noise Model

Equivalent Input Noise Generators

Noise Factor and Input Noise Generators

Noise Generators of a BJT Common-EmitterStage

Noise Voltage Generator of a BJT Common-Emitter Stage

Noise Current Generator of a BJT Common-Emitter Stage

BJT Equivalent Input Shot Noise SpectralDensity

Total Equivalent Noise Voltage of a BJTCommon-Emitter Stage

Noise Generators of a FET Common-SourceStage

Noise Voltage Generator of a FET Common-Source Stage

MOST Equivalent Input Noise Voltage Spec-tral Density

Noise Current Generator of a FET Common-Source Stage

Noise Factor of a BJT Common-Emitter Stage

Noise Factor of an FET Common-SourceStage

Noise Performance of Other Configurations

Emitter-Coupled Pair Noise Performance

Effect of Ideal Feedback on Noise Perfor-mance

Effect of Input Series Feedback Feedback onNoise Performance

Effect of Input Shunt Feedback Feedback onNoise Performance

Effect of Feedback on Noise Performance

Effect of Cµ on Noise Performance

Single-Stage Amplifier with Local Feedback

Operational Amplifier Noise Model

A Low-Pass Filter Example

A Current Amplifier Example

12. Feedback and Compensation

Feedback

Effect of Negative Feedback on Distortion

Series-Shunt Feedback Configuration

Shunt-Shunt Feedback Configuration

Shunt-Series Feedback Configuration

Series-Series Feedback Configuration

Two-Port Analysis of Feedback Amplifier

Loading Approximation Method

Two-Port Analysis of a Shunt-Shunt FeedbackAmplifier

Return Ratio

Closed-Loop Gain Using Return Ratio

Blackman’s Impedance Formula

A Transresistance Feedback Amplifier

Frequency Response of Feedback Amplifiers

Single-Pole Model

Nyquist Diagram

Nyquist Criterion

Phase Margin

Pseudo Dominant-Pole Model

Phase Margin of the Pseudo Dominant-PoleModel

Closed-Loop Response of the PseudoDominant-Pole Model

Quality Factor (Q) and Phase Margin

Dominant-Pole Compensation


Miller (Pole-Splitting) Compensation

Feedforward Zero in Miller Compensation

Miller Compensation With Unity-Gain Buffer

Miller Compensation With Common-GateStage

Miller Compensation With Nulling Resistor

Miller Compensation with FeedforwardTransconductor

Nested-Miller Compensation

Zeros in the Nested-Miller Compensation

Nested-Miller Compensation with Feedfor-ward Transconductors

13.Basic Two-Stage Operational Amplifier De-sign

Ideal Operational Amplifier

Basic 2-Stage CMOS Opamp

Constant gm Bias Generator

Input Stage Small-Signal Model

Input Stage Output Impedance

Input Stage Differential-Mode Transconduc-tance

Input Stage Common-Mode Transconduc-tance

Input Stage Voltage Gain

Simplified Two-Stage Model

Frequency Compensation Using Nulling Re-sistor

Frequency Compensation Using Zero-NullingResistor

Voltage and Current Range

Slew Rate

Settling Time

Input Impedance

Output Impedance

Systematic Input Offset Voltage

Random Input Offset Voltage

Input Offset Voltage and Common-Mode Re-jection Ratio

CMRR Due to Systematic and Random Offset

Mismatches and Input Stage Transconduc-tance

Power Supply Rejection Ratio (PSRR)

Power Supply Rejection Ratio (PSRRSS)

Power Supply Rejection Ratio (PSRRDD)

PSRRDD with Common-Gate Miller Com-pensation

Supply Capacitance

Power-Supply Rejection and Supply Capaci-tance

Device Noise Analysis

Thermal Noise Performance

Flicker Noise Performance

2-Stage Opamp with pMOST Input Stage

14. Operational Amplifiers with Single-EndedOutputs

Two-Stage Operational Amplifier with Cas-code

Telescopic-Cascode Operational Amplifier

Folded-Cascode Operational Amplifier

Current-Mirror Operational Amplifier

Rail-to-Rail Complementary Input Stage

A Rail-to-Rail Input/Output Opamp

Low-Voltage Multi-Stage Opamp

Current-Feedback Configuration

A CMOS Current-Feedback Driver

A General-Purpose BJT Current-FeedbackOpamps

15.Fully Differential Operational Amplifiers

Fully Balanced Circuit Topology

Small-Signal Models for Differential Loading

Small-Signal Models for Differential SignalSources

Common-Mode Feedback (CMFB)

A Fully Differential Two-Stage OperationalAmplifier

CMFB Using Resistive Divider and Error Am-plifier

CMFB Using Resistive Divider and DirectCurrent Injection

CMFB Using Dual Differential Pairs

CMFB Using Transistors in the Triode Region

Switched-Capacitor CMFB



Current-Mirror Push-Pull Operational Ampli-fier

Class-AB Operational Amplifier

Fully Differential Operational Amplifiers

Active-Cascode Telescopic Operational Am-plifier

Fully Differential Gain-Enhancement Auxil-iary Amplifiers

Replica-Tail Feedback

16. Operational Amplifiers and Their BasicConfigurations


Operational Amplifier Imperfections (I)

Operational Amplifier Imperfections (II)

Operational Amplifier Imperfections (III)

Operational Amplifier Imperfections (IV)

Inverting Configuration

Examples of Inverting Configuration

Inverting Summer Configuration

Noninverting Configuration

Switched-Capacitor Applications

Switched-Capacitor Step Response

17. Analog Switches and Sample-and-Hold Cir-cuits

Sample-and-Hold (Track-and-Hold) Circuits

MOST Switches in Sample Mode

MOST Switches from Sample to Hold Mode

Switching Errors in Slow-Gating MOSTSwitches

Switching Errors in Fast-Gating MOSTSwitches

MOST S/H Speed-Precision Tradeoff

Aperture Jitter Due to the Finite Falling Time

Thermal Noise in MOST S/H

Charge Compensation for MOST Switches

Differential Sampling

Bottom-Plate Sampling

Complementary Analog Switches

A Differential BJT Sampling Switch


Open-Loop MOST S/H

MOST S/H Using Miller Holding Capacitor

MOST S/H Using Miller Capacitor andBottom-Plate Sampling

MOST S/H Using Double Miller Capacitors

A MOST Recycling S/H

Closed-Loop S/H

Closed-Loop S/H with Improved tslew

Closed-Loop S/H Using Active Integrator

An RC Closed-Loop S/H

A Switched-Capacitor Closed-Loop S/H

Charge Redistribution Sampled-Data Amplifi-er

Charge Redistribution Sampled-Data Amplifi-er

Charge Redistribution Summing Amplifier

Sampled-Data Amplifier with CDS

A Capacitive-Reset Sampled-Data Amplifier

A Capacitive-Reset CDS Amplifier

18. Comparators and Offset Cancellation Tech-niques

Comparators

Comparator Design Considerations

Comparison with Single-Pole Amplifier

Comparison with Multi-Stage Cascaded Am-plifier

Comparison with Positive-Feedback Regener-ation

Output Offset Storage (OOS)

Multistage Output Offset Storage

Input Offset Storage (IOS)

Multistage Input Offset Storage

MOST Comparator: Auto-Zeroing Inverter

MOST Comparator: Cascaded Auto-ZeroingInverters

MOST Comparator: Preamp + RegenerativeSense Amplifier

MOST Comparator: Merged Preamp + SenseAmplifier

Offset Canceled Latches: Idea

Offset Canceled Latches: Simplified Schemat-ic

Offset Canceled Latches: MOST Implementa-tion

BJT Latched Comparator

BJT Comparator with High-Level Latch

A Sampled-Data Amplifier with Internal Off-set Cancellation

Operational Amplifier with Offset Compensa-tion

The Chopper Stabilization Technique

A Chopper Operational Amplifier

Residual Offset of Chopper Amplifier

Chopper Modulation with Guard Time

19. Oscillators

The Barkhausen Criteria

Three-Stage Ring Oscillator

Three-Stage CMOS Inverter Ring Oscillator

Four-Stage Differential Ring Oscillator

Differential Delay Stage

Delay Variation Using Variable Resistors

Delay Variation Using Positive Feedback

Delay Variation Using Interpolation

LC-Tuned Delay Stage

LC-Tuned Ring Oscillators

Colpitts Oscillator

One-Port Oscillators

The van der Pol Approximation

A CMOS SONY Oscillator

Differential CMOS SONY Oscillators

Single-Transistor Negative Resistance Gener-ator

Piezoelectric Crystals

Crystal Oscillators

Relaxation Oscillators (Multivibrators)

Constant-Current Charge/Discharge Oscilla-tors

The Banu Oscillator

A CMOS Relaxation Oscillator

A Emitter-Coupled Multivibrator

20. Fundamentals of Analog Filters Filters

Low-Pass Filter Specifications

High-Pass Filter Specifications

Band-Pass Filter Specifications

Band-Reject Filter Specifications

Second-Order Filter (Biquadratic Function)

Second-Order Low-Pass (LP) Filter

Second-Order High-Pass (HP) Filter

Second-Order Band-Pass (BP) Filter

Second-Order Band-Reject (BR) Filter - Low-Pass Notch (LPN)

Second-Order Band-Reject (BR) Filter - High-Pass Notch (HPN)

Second-Order Band-Reject (BR) Filter - Sym-metrical Notch

Second-Order All-Pass (AP) Filter

Maximally Flat (Butterworth) Filters

Equi-Ripple (Chebyshev) Filters

Elliptic (Cauer) Filters

Comparison of the Classical Filter Responses

Linear-Phase (Bessel-Thomson) Filters

All-Pass Filter (Delay Equalizer) Specifica-tions

Frequency Transformations

High-Order Filters

LC Ladder Filters

Sensitivity

Transfer Function Sensitivity

Second-Order Filter Sensitivity

High-Order Filter Sensitivity

21. Active-RC Filters

Capacitor Integrators

Active-RC Inverting Integrators

Actively Compensated Inverting Integrator

Noninverting Integrator

Phase-Lead Noninverting Integrator

First-Order Filters

Single-Amplifier 2nd-Order Filters -Sallen-Key LP Biquad

State-Variable Second-Order Filters

Tow-Thomas (TT) Biquad

Ackerberg-Mossberg (AM) Biquad

Arbitrary Transmission Zeros by Summing

Arbitrary Transmission Zeros by VoltageFeedforward

High-Order Filter Using Cascade Topology

Cascaded Filter Design Procedures

High-Order Filter Using the Follow-the-Leader Feedback Topology

High-Order Filter LC Ladder Simulation

LC Ladder Simulation

An All-Pole Low-Pass Ladder Filter

Signal-Level Scaling in Ladder Filters

General Ladder Branches

General Ladder Branches by Active-RC Im-plementation

Finite Transmission Zeros in the SeriesBranches

22. MOST-C and Gm-C Filters

MOSTs in the Triode Region

MOST-C Fully-Balanced Integrators

Double MOST-C Differential Integrators

R-MOST-C Differential Integrators

A MOST-C Tow-Thomas Biquad

Transconductors

Transconductor Basic Circuits

Gm-C Lossy Integrator

Fully-Differential Gm-C Integrators

Gm-C Opamp Integrators (Miller Integrators)

Gyrators

Gm-C Simulated Gyrators

MOST Transconductors

MOST Transconductors with Source Degen-eration

BJT Transconductors

Multi-Input Transconductors

Transconductor’s Imperfections

The Effect of Non-Zero go on Gyrators

The Effect of Phase Shift on Gyrators

Gm-C First-Order Filters

Gm-C Second-Order Filters

Gm-C First-Oder Filters Using Miller Integra-tors

Gm-C Second-Oder Filters Using Miller Inte-grators

Ladder Filter Using Simulated Gyrators

Ladder Filter Using Signal-Flow Graph

Gm-C Simulation of Ladder Branches (I)

Gm-C Simulation of Ladder Branches (II)

Gm-C Resonators

Gm-C Quadrature Oscillators

On-Chip Tuning Strategies

Separate Frequency and Q Control

Gm Tuning

Frequency Tuning Using Switched Capacitors

Frequency Tuning Using Response Detection

Frequency Tuning Using Phase-Locked Loop

Q-Factor Tuning Using MLL

Q-Factor Tuning Using LMS

23. Switched-Capacitor Filters

Switched-Capacitor Equivalent Resistor

Switched-Capacitor Integrators

SC Integrator Analysis

SC Differential Integrators

Effects of Parasitic Capacitances

Parasitics-Insensitive SC Integrators

Fully Differential SC Integrators

MOST Analog Switches

Effects of Opamp’s Finite DC Gain

Effects of Opamp’s DC Offset

An Offset Auto-Zeroing Scheme

Effects of Opamp’s Finite Settling Time

An SC Integrator with CDS

Discrete-Time Signal Processing

Continuous-Time Signals

Discrete-Time Signals

s-to-z Transformation

Bilinear s-to-z Transformation

Hc(s) to H(z) Design Procedures for BilinearTransformation

Switched-Capacitor Filter Systems

Design Constraints

Periodic Time-Variance in Biphase SC Filters

Active Switched-Capacitor Integrators

SC First-Order Filters

Switch Sharing

Bilinear SC First-Order Filters

SC Second-Order Filters

A Low-Q SC Biquad

A High-Q SC Biquad

Time-Staggered SC Stages

Capacitor Scaling

Output Capacitor Scaling

Input Capacitor Scaling


An All-Pole Low-Pass SC Ladder Filter

SC Ladder Filter Using Signal-Flow Graph

SC Ladder Filters Design Methodology

SC Ladder Filters Design Procedures

24. Niquist-Rate Digital-to-Analog Converters

A/D and D/A Interfaces

Continuous-to-Discrete Conversion

Discrete-to-Continuous Conversion

Imperfections in Discrete-to-Continuous Con-version

D/A Transfer Characteristic

D/A Nonlinearity

D/A Performance Metrics - Static Character-istics

D/A Performance Metrics - Dynamic Charac-teristics

Dynamic Range

Resistor-String DACs with Digital Decoding

Folded R-String DACs with Digital Decoding

R-String DACs with Binary-Tree Decoding

Intermeshed Resistor-String DACs (One-Level Multiplexing)

Intermeshed Resistor-String DACs (Two-Level Multiplexing)

Binary-Weighted Current-Steering DACs

Binary-Weighted R-2R Networks

Equally-Weighted Current-Steering DACs

The Matrix Floorplan

A Current Cell Example

Charge-Redistribution DACs

Segmented DAC Architecture

A 10-Bit Segmented Current-Steering DAC

A Segmented Current-Steering DAC

Dynamically-Matched Current Sources

A Segmented Charge-Redistribution DAC

A Capacitor-Resistor Hybrid DAC

25. Niquist-Rate Analog-to-Digital Converters



A/D Quantization Characteristic

Imperfections in A/D Quantization Character-istic

Quantization Noise

Sampling-Time Uncertainty (Aperture Jitter)

DFT Nonlinearity Test of ADCs

Code Density Test of ADCs

Serial (Integrating) Architectures

Parallel (Flash) Architectures

Successive Approximation Architectures

Charge-Redistribution ADC

C-R ADCs Using Input Offset Storage Tech-nique

Self-Calibrating Charge-Redistribution ADCs

Quantized-Feedforward (Subranging) Archi-tectures

Quantized-Feedforward Minimal Design

Over-Range in the Minimal Design

Quantized-Feedforward Redundant Design

Digital Encoding for the Quantized-Feedforward Architecture

A Radix-2 1ff5 Bit SC Pipeline Stage

Multi-Bit Switched-Capacitor Pipeline Stage

Switched-Capacitor Pipelined ADCs

Single-Stage Calibration and Digital Correc-tion

Multi-Stage Calibration and Digital Correc-tion

Calibration of A Radix-2 1ff5 Bit SC PipelineStage

A Radix-2 Cyclic ADCs

A Radix-2 Switched-Capacitor Cyclic ADC

A CMOS Subranging Flash ADC - Dingwall

A CMOS Subranging Flash ADC - Brandt

Interpolated Differential Comparator Bank

A CMOS Subranging Flash ADC - Brandt

Flash Quantization Architecture

Resistor-String Interpolation

Folding

Interpolation and Folding

Averaging Preamplifiers

Effects of Averaging

Bending at the Edges Due to Averaging

Cascaded Folding

Differential Preamplifier

A CMOS 10-Bit Folding ADC - Bult

Time-Interleaved Architectures

26.Oversampling Converters

Sampling and Quantization

Oversampling

First-Order Ó Modulator

First-Order Ó Modulator

First-Order Ó Modulator with SC Circuit Im-plementation

Circuit Considerations

Second-Order Ó Modulator

Integration Range in a Second-Order Ó Mod-ulator

Integration Range in a Second-Order Ó Mod-ulator

Overloading in a Second-Order Ó Modulator

Oversampling ADCs

General Single-Stage Ó Modulator

General Single-Stage Error-Feedback Coder

Single-Stage High-Order Modulators

Stability of Single-Stage High-Order Modula-tors

Multi-Stage Cascaded Modulators

A Third-Order (1-1-1) Cascaded Modulators

Idle Channel Tones (Pattern Noises)

Noise-Shaped Dithering for Single-StageModulators

Noise-Shaped Dithering for Multi-Stage Cas-caded Modulators

Multi-Bit Ó Modulator

Multi-Bit DAC - Dynamic Element Matching

Multi-Bit DAC - Data-Weighted Averaging

Multi-Bit DAC - Noise-Shaped Scrambler

General Mismatch-Shaping DAC

General Mismatch-Shaping DAC - First-OrderExample

General Mismatch-Shaping DAC - Second-Order Example

Multi-Bit Unit Elements

Decimation and Interpolation

Multi-Stage Rate Conversion

sinck Filters

27. Phase-Locked Loops

Phase-Locked Loops (PLLs)

Basic Model

Second-Order PLL - Active Lag-Lead Filter

Second-Order PLL - Passive Lag-Lead Filter

High-Gain Second-Order PLL Frequency Re-sponse

Step Response of a Two-Pole System

Phase Jitter

Phase Noise

PLL Noise Response

Phase Detection Using Analog Multiplier

PLL Tracking Performance - Hold-In Range

PLL Tracking Performance - Pull-Out Range

Noisy PLL Tracking Performance

PLL Acquisition Behavior

Phase Acquisition of a First-Order Loop

Phase Acquisition of a Second-Order Loop

Frequency Acquisition - The Pull-In Process

Aided Frequency Acquisition - FrequencySweeping

Aided Frequency Acquisition - Loop FilterSwitching

Aided Frequency Acquisition - Dual Loops

Digital Phase-Locked Loops (DPLLs)

XOR Phase Detector

Edge-Triggered Set-Reset Phase Detector

Sequential Phase-Frequency Detector (PFD)

Charge-Pump Phase-Locked Loops

PFD and Charge-Pump Filter

PFD with Delayed Reset

Third-Order Charge-Pump PLLs

Multi-Path Charge-Pump Filter


Jieh-Tsorng Wu

July 17, 2002

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E S National Chiao-Tung UniversityDepartment of Electronics Engineering

Copyright c© 2001 by Jieh-Tsorng Wu

• All Rights Reserved.

• Unmodified reproduction of these lecture notes for class or personal use is permitted.

• For commercial use, permission should be obtained from the author.

Contents 0-2 Analog ICs; Jieh-Tsorng Wu

Devices and Technologies

1. Introduction

2. PN Junctions and Bipolar Junction Transistors

3. MOS Transistors

4. Integrated Circuit Technologies


Basic Circuits and Design Techniques

5. Single-Transistor Gain Stages

6. Multiple-Transistor Gain Stages

7. Differential Gain Stages

8. Current Mirrors and Active Loads

9. Voltage and Current References

10. Output Stages

11. Noise Analysis and Modelling

12. Feedback and Compensation


Operational Amplifiers

13. Basic Two-Stage Operational Amplifier Design

14. Operational Amplifiers with Single-Ended Outputs

15. Fully Differential Operational Amplifiers


Analog Functional Blocks

16. Operational Amplifiers and Their Basic Configurations

17. Analog Switches and Sample-and-Hold Circuits

18. Comparators and Offset Cancellation Techniques

19. Oscillators


Subsystems

20. Fundamentals of Analog Filters

21. Active-RC Filters

22. MOST-C and Gm-C Filters

23. Switched-Capacitor Filters

24. Niquist-Rate Digital-to-Analog Converters

25. Niquist-Rate Analog-to-Digital Converters

26. Oversampling Converters

27. Phase-Locked Loops


Introduction

Jieh-Tsorng Wu

July 16, 2002

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Storage MediaDiskTapeBubble

DigitalVLSI

System

Audio I/O

Transmission MediaWire PairsCoaxFiberRF

Physical Sensors & Actuators

Imagers & Displays

PowerSource

Analog/Digital Interfaces

• Usually integrated with digital VLSI circuits monolithically (mixed-signal integratedcircuits) for better performance and/or lower cost.

Introduction 1-2 Analog ICs; Jieh-Tsorng Wu

Analog Signal Processing

Analog Signals

• Always continuous in amplitude.

• Either continuous in time (s-transform) or discrete in time (z-transform).

Analog circuits provide interfaces between the analog environment of the physical worldand a digital environment. Major functions are

• Amplification.

• Filtering.

• Analog-to-digital conversion.

• Digital-to-analog conversion.

• Power supply conditioning.


Design for Analog Circuits

Signal path

• Small (variational) signals related by linear transfer function in the frequency domain.

• Model with linearized small-signal equivalent circuit.

• Analyze using Laplace transforms.

Biasing Circuit

• Establish operating conditions of devices in signal path.

• Concern with sensitivity to variations in temperature, supply voltage, and fabricationprocess.

• Analyze using large-signal device models.


Performance Considerations

• Small-signal response: gain, bandwidth, noises, . . .

• Large-signal response: settling time, distortion, . . .

• Sensitivity to device variation, temperature variation, external noises, . . .

• Cost: power dissipation, chip area, yield.


Design Practices

• Make simplifying assumptions that allow hand analysis.

• Keep in mind potential consequences of the assumptions.

• Use simulations to verify the design.

• Good designs are robust; i.e., insensitive to approximations in the modeling as wellas variations in temperature and fabrication process.


PN Junctions and Bipolar Junction Transistors

Jieh-Tsorng Wu

September 6, 2002

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PN Junctions

Built-in potential = Ψ0 = UT lnNAND

n2i

UT =kT

q≈ 26 mV at 300K

ni ≈ 1.5 × 1010 cm−3 at 300K for Si

Solving Poisson’s equation,

W1 =

2ε(Ψ0 + VR)

qNA

(1 + NA

ND

)

1/2

W2 =

2ε(Ψ0 + VR)

qND

(1 + ND

NA

)

1/2

BJT 2-2 Analog ICs; Jieh-Tsorng Wu


Depletion layer charge is Qj = qNAW1A = qNDW2A, where A is the cross-sectional area.

Depletion-region capacitance

Cj =dQj

dVR= A

[qε

2Ψ0

NAND

NA +ND

]1/2

· 1√1 + VR

Ψ0

=Cj0√1 + VR

Ψ0



• Cj can be expressed as

Cj = A · εxd

xd = W1 +W2

• In general

Cj =Cj0(

1 + VRΨ0

)m 13≤ m ≤ 1

2

– m = 1/2 for abrupt junction.– m = 1/3 for graded junction.

• In forward bias, diffusion capacitance dominates.


Large-Signal Junction Capacitance

Depletion layer charge can be rewritten as

Qj =Cj0

1 −m· Ψ0 ·

(1 +

VR

Ψ0

)1−m

Average capacitance is defined as

Cj−av =Qj(V2) − Qj(V1)

V2 − V1

For an abrupt junction, m = 0.5,

Cj−av = 2Cj0Ψ0 ·

√1 + V2

Ψ0−√

1 + V1Ψ0

V2 − V1

• If V1 = 0 V, V2 = 5 V, and Ψ0 = 0.9 V

Cj−av = 0.56 · Cj0 ≈12Cj0


PN Junction in Forward Bias

V D

I D

r d CT

Small-Signal Model

ID = IS(eVD/UT − 1) ≈ ISeVD/UT IS ≈ A

(1NA

+1ND

)1rd

=dID

dVD=

ID

UT

CT = Cd + Cj

Cd = τT ·ID

UT

=τT

rdτT = Transit Time

• For moderate forward-bias currents, Cd Cj , rdCT ≈ τT .

• For Schottky diode, Cd = 0.


PN Junction Avalanche Breakdown

• The maximum electric field in the depletion region of an abrupt junction is

|Emax| =qNAW1

ε=[

2qNAND(Ψ0 + VR)

ε(NA +ND)

]1/2

|Emax| increases with both VR and doping density.

• As |Emax| → Ecrit, carriers crossing the depletion region acquire enough energyto create new electron-hole pairs when colliding with silicon atoms. The result isavalanche breakdown.

IRA = MIR M =1

1 −(

VRBV

)nBV is the breakdown voltage. And typically 3 ≤ n ≤ 6

• Ecrit is a function of doping density, which can vary from 3× 105 V/cm to 106 V/cm asNA (or ND) varying from 1015 atoms/cm3 to 1018 atoms/cm3.


PN Junction Breakdown

Zener Breakdown

• In very heavily doped junctions where the electric field becomes large enough to stripelectrons always from the valence bonds. This process is called tunneling.

• The Zener breakdown mechanism is important only for breakdown voltages belowabout 6 V.

Punch Through

• A form of breakdown that occurs when the depletion regions of two neighboringjunctions meet.


Bipolar Junction Transistor (BJT)



There is a negligible flow of holes between emitter and collector junctions becauseneither can supply a significant flow of holes into the base. Thus, in the neutral baseregion,

Jp = qµppb(x)E(x) − qDp

dpb

dx= 0 ⇒ E(x) =

Dp

µp

1pb

dpb

dx=

kT

q

1pb

dpb

dx

• Note that for uniformly doped region dpb/dx = 0⇒ E(x) = 0

For electrons in the base,

Jn = qµnnb(x)E(x) + qDn

dnb

dx= kTµn

nb

pb

dpb

dx+ qDn

dnb

dx=

qDn

pb

(nb

dpb

dx+ pb

dnb

dx

)

=qDn

pb

[d (nbpb)

dx

]



Assuming negligible recombination in the base, so that Jn is constant,

Jn

∫ WB

0

pb(x)

qDn

dx =∫ WB

0

d (nbpb)

dxdx = nb(0)pb(0) − nb(WB)pb(WB)

From the Boltzman approximation at the edges of the depletion layers,

nb(0)pb(0) = n2ieVBE/UT nb(WB)pb(WB) = n2

ieVBC/UT

Thus

Jn =qn

2i∫WB

0pbDndx

(eVBE/UT − eVBC/UT

)= JS


)

where

JS ≡qn

2i∫WB

0pbDndx


Gummel Number (G)

Dn is a weak function of x. Then, JS can be expressed as

JS =qn

2i∫WB

0pbDndx

=qn

2i Dn

G

where

G ≡∫ WB

0pb(x)dx ≈

∫ WB

0NA(x)dx

• The Gummel number, G, is simply the dopant concentration per unit cross-sectionalarea of the base.

• For a uniform base region, NA(x) = NA, then G = WBNA.


Base Transport Current

The total minority carrier transport current across the base is

IT = JN × A = IS

[eVBE/UT − eVBC/UT

]where IS = JS × A =

qn2i Dn

G× A

The transport current can be separated into forward and reverse components as

IT = IS

(eVBE/UT − 1

)− IS

(eVBC/UT − 1

)= ICF + IER

• If VBE > 0 and VBC < 0, the device is biased in the forward-active region,

IT = ISeVBE/UT

• If VBE < 0 and VBC > 0, the device is biased in the inverse-active region,

IT = ISeVBC/UT

• If VBE > 0 and VBC > 0, the device is biased in the saturation region.


Base Current

In the forward-active regionIB = IBB + IBE

• IBB is due to the recombination of holes and electrons in the base.

• IBE is due to the injection of holes from the base into the emitter.

Define Qe as the minority carrier charge in the base region

Qe = qA

∫ WB

0nb(x)dx or Qe =

12qAWBnb(0) =

12qAWB

n2i

NA

eVBE/UT

IBB is related to Qe by the lifetime of minority carriers in the base, τb

IBB =Qe

τb=

12

qAWB

τb

n2i

NA

· eVBE/UT


Base Current

IBE depends on the gradient of minority carriers (holes) in the emitter.

• For a “long-base” emitter (all minority carriers recombine in the quasi-neutral region)with a diffusion length Lp

IBE =qADp

Lp

peoeVBE/UT =

qADp

Lp

n2i

ND

eVBE/UT ND = Emitter Doner Density

• For a “short-base” emitter (all recombination at the contact) with emitter width WE , WE

simply replaces Lp in the expression for IBE .

The total base current in the forward-active region is

IB =

[12

qAWB

τB

n2i

NA

+qADp

Lp

n2i

ND

]eVBE/UT

• In modern narrow-base transistors IBE IBB.


Forward Current Gain

In the forward-active region, the forward current gain is

βF ≡IC

IB=

1W 2B

2τbDn+

Dp

Dn

WB

LP

NA

ND

The emitter current is

IE = −(IC + IB) = −(IC +

IC

βF

)= −

IC

αF

where

αF ≡ −IC

IE=

βF

βF + 1=

1

1 + 1βF

=1

1 +W 2B

2τbDn+

Dp

Dn

WB

LP

NA

ND

≈ αT · γ

αT =1

1 +W 2B

2τBDn

γ =1

1 +Dp

Dn

WB

LP

NA

ND

• αT is called the base transport factor, and γ is called the emitter injection efficiency.


BJT DC Large-Signal Model in Forward-Active Region

VV BE(on)BE

I E

C

E

IB II C

B

E

C

B I

I

E

B C

IB =IS

βF

eVBE/UT IC = βF IB

• The voltage on the emitter junction can be approximated by a constant VBE (on).

• VBE (on) is usually 0.6 V to 0.8 V, and has a temperature coefficient of −2 mV/C.


Dependence of βF on Operating Condition

• At high currents, due to high-level injection

IC → ISeVBE/(2UT )

• At low currents, due to recombination in the B-E depletion region

IB → ISeVBE/(2UT )



In the forward-active region, an increase ∆VCE in VCE results in an increase in thecollector depletion layer width, thereby reducing WB by ∆WB, and increasing IC.

IC = ISeVBE/UT = A

qn2i Dn

GeVBE/UT G = Gummel number

∂IC

∂VCE= −A

qn2i Dn

G2eVBE/UT · dG

dVCE= −

IC

G· dGdVCE



For a uniform-base transistor

G = WBNA and∂IC

∂VCE= −

IC

WB

·dWB

dVCE

• dWB/dVCE is typically a weak function of VCE for a reverse biased collector junctionand is often assumed to be constant.

The Early voltage, VA, is given by

VA =IC

∂IC/∂VCE= −WB

1

dWB/dVCE

The influence of changes in VCE on IC can thus be represented as

IC = ISeVBE/UT

(1 +

VCE

VA

)

• Typical values of VA are 15–100 V.


Base Transport Model

B

E

C

IT

IC

IE

IS/βR

IS/βF

IT = IS


)IC = IT −

IS

βR

(eVBC/UT − 1

)IE = −IT −

IS

βF

(eVBE/UT − 1

)

IB =IS

βF

(eVBE/UT − 1

)+

IS

βR

(eVBC/UT − 1

)


Ebers-Moll Model

RecallingIT = IS


)IC = IT −

IS

βR

(eVBC/UT − 1

)IE = −IT −

IS

βF

(eVBE/UT − 1

)SPICE uses the base transport model with the equations rewritten as:

IC = IS

(eVBE/UT − 1

)− IS

(1 +

1βR

)(eVBC/UT − 1

)= IS

(eVBE/UT − 1

)−

IS

αR

(eVBC/UT − 1

)

IE = −IS(

1 +1βF

)(eVBE/UT − 1

)−IS(eVBC/UT − 1

)= −

IS

αF

(eVBE/UT − 1

)−IS(eVBC/UT − 1

)

• Note that, in the classical Ebers-Moll model, parameters IES and ICS are defined suchthat

αF IES = αRICS = IS


Leakage Current

In the forward-active region, eVBE/UT 1 and eVBC/UT 1, then

IC ≈ ISeVBE/UT +

IS

αR

IE ≈ −IS

αF

eVBE/UT − IS

thusISe

VBE/UT = −αF IE − αF IS

and

IC = −αF IE +(

1αR

− αF

)IS = −αF IE + ICO

where

ICO ≡ (1 − αF αR)IS

αR

• ICO is the collector-base leakage current with the emitter open.

• In practice, because of surface leakage effects, ICO is several orders of magnitudelarger than the value predicted by the above definition.


Common-Base Transistor Breakdown

• Avalanche multiplication at the junctionsof a BJT limits the voltage that can besustained.

• BVCBO is the breakdown voltage of C-Bjunction with IE = 0.

BVEBO is much less than BVCBO.

Neglecting leakage currents

IC = −αF IEM where M =1

1 −(

VCBBVCBO

)n



IC

IB

VCE



In this configuration, holes generated in the avalanche process are swept into the basewhere they act as a supply of base current. The avalanche current is thus effectivelyamplified by βF .

IB = −(IC + IE ) = −IC +IC

MαF

⇒ IC =(

MαF

1 −MαF

)IB

where M is as defined above for the common-base case.

BVCEO is defined as the value of VCE for which IC → ∞; that is, for which MαF → 1.Assume VCB ≈ VCE , then

Mα =αF

1 −(BVCEO

BVCBO

)n = 1 ⇒BVCEO

BVCBO= (1 − αF )1/n =

1

(βF + 1)1/n≈ 1

β1/nF

• Note: Here must use value of BVCBO for intrinsic transistor. Actual BVCBO is lower thanthis because of sidewall effects.



E

B C

Ic

Ib

Vbe

VCC

rπ Cπ

rµ

Cµ

vπ gmvπ ro

In the forward-active region

IC = ISeVBE/UT

(1 +

VCE

VA

)IB =

IC

βF

Bias and small-signal variables are:

Ib = IB + ib Ic = IC + ic Vbe = VBE + vbe



gm =∂IC

∂VBE=

qIC

kT=

IC

UT

βo =∂IC

∂IB=[

∂

∂IC

(IC

βF

)]−1

gπ =∂IB

∂VBE=

1rπ

=1βo

∂IC

∂VBE=

gm

βo

go =∂IC

∂VCE=

IC

VA= ηgm

gµ =∂IBB

∂VCB=

∂IBB

∂IC

∂IC

∂VCB=

1rµ

Cπ = Cb + Cje = τF gm + Cje

Cµ = Cjc

• If βF is constant, then βo = βF .

• η ≡ UTVA

.

• If IB = IBB

gµ ≈∂IB

∂IC

∂IC

∂VCE=

go

βo

or rµ = βoro

• Typically, rµ > 10βoro.For lateral pnp, rµ is 2βoro ∼ 5βoro.

• Junction capacitances are

Cj =Cj0(

1 − VΨ0

)n n = 0.2 ∼ 0.5


Charge Storage

In the intrinsic transistor charge is stored in the junction capacitances, Cje and Cjc, andas minority carriers in the base (Qe) and emitter (Qp).

• Both Qe and Qp are proportional to eVBE/UT .

• Qe Qp and typically the effect of Qp is taken into account simply by modifying Qe.

An equivalent forward base transit time, τF , is defined as

τF ≡Qe

ICτF =

W2B

2Dn

for uniform-base transistor

The diffusion capacitance is

Cb =∂Qe

∂VBE= τF

∂IC

∂VBE= τF gm


Complete Small-Signal Model with Extrinsic Components

B C

E

B’

rπ Cπ

rµ

Cµ

gmvπro

rb rc

rex

vπ Ccs


Typical values of Extrinsic Components

rb 50–500 Ωrc 20–500 Ωrex 1–8 ΩCcs 0.2–3 pF

The value of rb varies significantly with IC because of current crowding.


MOS Field-Effect Transistors

Jieh-Tsorng Wu

October 8, 2002

A

1896


MOS Transistors

V D

V S

V G

V G

V B

V B

I D

I D

V S

V D

nMOST

pMOST

Body

Source

Gate

Drain

BodyGate

Drain

Source

S

G

G

D

S

D

MOST 3-2 Analog ICs; Jieh-Tsorng Wu

MOS Transistors

• Lelectrical = Lgate − 2LD. In SPICE, L = Lgate.

• For nMOST, VD > VS > VB.

• For pMOST, VD < VS < VB.

• The I − V equations of nMOST are identical to those of pMOST.

• For enhancement-mode device, Vtn > 0 and Vtp < 0.


Strong InversionV G V DV S

V B

NSUB

n+ n+

DepletionRegion y

L0

V(y)

p- Substrate

The threshold voltage of VGB for strong inversion is

Vt(y) = V (y) + 2φf + γ

√V (y) + 2φf + VF B

2φf = 2kT

qln(NSUB

ni

)γ =

√2qεsiNSUB

Cox

Cox =εox

tox


Channel Charge Transfer Characteristics

The induced channel charge per unit area is

QI(y) = Cox

[VGB − Vt(y)

]when VGB > Vt(y)

The current along the channel is

ID = W · µQI(y) · E(y) = W · µQI(y) · dVdy

⇒ IDdy = WµQI(y)dV

Integration along the channel from 0 to L gives

∫ L0IDdy =

∫ VDB

VSB

W µCox

[VGB − Vt(y)

]dV

ID = µCox

W

L

(VGB − 2φf − VF B)V (y) − 1

2V 2(y) − 2

3γ[V (y) + 2φf ]

3/2∣∣∣∣

VDB

VSB


Simplified Channel Charge Transfer Characteristics

The threshold voltage of VGS for strong inversion is simplfied as

V ′t(y) + VSB = V ′(y) + VSB + Vt(SB) ⇒ V ′

t(y) = V ′(y) + Vt

The channel charge becomes

QI(y) = Cox

[VGS − V ′(y) − Vt

]And the drain current is

ID = µCox

W

L

[(VGS − Vt)VDS −

12V 2DS

]= k′

W

L


12V 2DS

]

• Vt is the threshold voltage of VGS for strong inversion, and depends on VSB.

• k′ = µCox is called the process transconductance.


MOST I-V Characteristics

TriodeRegion

Saturation (Active)Region

ID

VDS

VDS = VDSAT

VGS

√IDSAT

VSB = 0 VSB > 0

Vt0 Vt

ID = µCox

W

L


12V 2DS

]for VDS ≤ VDSAT = VGS − Vt

IDSAT = ID @ VDS = VDSAT =12µCox

W

L(VGS − Vt)

2


Threshold Voltage

Vt = Vt0 + γ

[√VSB + 2φf −

√2φf

]for VSB > 0

Vt0 is the threshold voltage when VSB = 0.

Vt0 = 2φf + γ

√2φf + VF B φf =

kT

qln(NSUB

ni

)γ =

√2qεsiNSUB

Cox

Cox =εox

tox

The Fermi level φf is temperature dependent, i.e.,

dφf

dT= −1

T

[Eg0

2q−φf

]Eg0 = Silicon band gap at T = 0K

The Vt0’s temperature coefficient is

dVt0

dT= −1

T

[Eg0

2q−φf

][2 +

γ√2φf

]

• dVt0/dT is usually in the range between −0.5 mV/C to −4 mV/

C.


Square-Law I-V Characteristics

In triode region, 1st-order long-channel model is

ID = µCox

W

L


12V 2DS

]= k′

W

L


12V 2DS

]

When VDS ≥ VDSAT = VGS − Vt, the MOST is in the pinch-off region (or saturation region),

IDS = IDSAT = ID(VDS = VGS − Vt) =12µCox

W

L(VGS − Vt)

2 =12k′W

LV 2ov

• k′ = µCox is called the process transconductance parameter.

• k = β = µCoxWL

is called the device transconductance parameter.

• Vov = VGS − Vt is called the gate drive or the overdrive.



go

G

DS

L

Leff

ID

VDS

VDSAT

IDSAT

ID(sat) =12k′

W

Lef f

V 2ov Lef f = L − ∆ ∆VDS = VDS − VDSAT

Using one-dimensional abrupt PN junction model,

∆ ≈

√2εsi

qNSUB

√VDS − VDSAT + Ψo



The ID variation due to VDS can be written as:

∂ID

∂VDS

=∂ID

∂Lef f

×∂Lef f

∂VDS

= −ID

Lef f

× −12

√2εsi

qNSUB

1√VDS − VDSAT + Ψo

= ID · λ

The drain current in the pinch-off region can be approximated as

ID(sat) =12k′W

LV 2ov (1 + λVDS) =

12k′W

LV 2ov

(1 +

VDS

VA

)

• λ is inversely proportional to L, i.e., λ ∝ 1/L.

• Typical values of λ are in the range 0.05 V−1 to 0.005 V−1.

• The accurate calculation of λ from the device structure is quite difficult. Extractionfrom experimental data is usually necessary.


MOST Small-Signal Model in Saturation Region

vgs g m vgs vsb

D

G

S

G D

B

S

B g o

vsb

g mb

Transconductance = gm ≡∂ID

∂VGS

= k′W

LVov(1 + λVDS) =

√2k′

W

LID(1 + λVDS) =

ID

Vov/2

Output Conductance = go ≡∂ID

∂VDS

= λID


MOST Small-Signal Model in Saturation Region

Body Transconductance = gmb ≡ −∂ID

∂VSB= −

∂ID

∂Vt×

∂Vt

∂VSB= gm ×

γ

2√VSB + 2φf

Thusgmb = gm × χ where χ ≡ γ

2√VSB + 2φf

• The factor χ is typically 0.1–0.3.

• Since γ =√

2qεsiNSUB/Cox

χ =

εsi/

√2εsi(VSB + 2φf )

qNSUB

1Cox

=εsi/xdmax

Cox

=Cdepl

Cox

xdmax: The width of depletion layer under channel.Cdepl : The capacitance/area of depletion layer under channel.


MOST Small-Signal Capacitances in Saturation Region

Cch

L D L DL

Source Drain

Body

C

CC

GateW

Lg

C sb db

ovdovs

Ccb

Csb = AS × CJ(VSB) + P S × CJSW (VSB) Cdb = AD × CJ(VDB) + P D × CJSW (VDB)

C′sb

= Csb + Ccb Ccb ≈ WL × CJ(VSB)

• AS and AD are the areas of the source/drain junctions.

• P S and P D are the source/drain perimeters excluding the sides adjacent to channel.


MOST Small-Signal Capacitances in Saturation Region

Junction Capacitances:

Csb =Csbo(

1 + VSBΨo

)m Cdb =Cdbo(

1 + VDB

Ψo

)m m =13∼ 1

2

Overlap Capacitances:

Covs = W × CGSO = W × (nLDCox) Covd = W × CGDO = W × (nLDCox)

1 ≤ n ≤ 2 (Due to friniging)


Channel Capacitance in Saturation Region

G

DS

L

y

V(y)

QI(y) = Cox[VGS − Vt − V (y)] = Cox[Vov − V (y)]

ID = W · µQI(y) · E(y) = W · µQI(y) · dVdy

ID =12µCox

W

LV 2ov

Let VS = 0 andID

µCoxW· dy =

[(VGS − Vt) − V (y)

]· dV

Integration from 0 to y ⇒ 12V 2ov

y

L= VovV −

12V 2(y)⇒ V (y) = Vov

(1 −√

1 − y

L

)

Total Channel Charge = QT =∫ L0QI(y)Wdy =

23WLCoxVov =

23WLCox(VGS − Vt)

Channel Capacitance = Cch ≡∂QT

∂VGS

=23WLCox


Complete MOST Small-Signal Model in Saturation Region

g m g mb vsbvgs g ovgs

S

G D

B

C

C

C

CCgb

gd

gs db

sbvsb’

Cgd = Covd Cgs = Covs +23WLCox

C′sb

= Csb + Ccb = (AS +W · L) × CJ(VSB) + P S × CJSW (VSB)


MOST Small-Signal Model in Triode Region

g dsCgd

Cdb

D

’

Cgs

Csb

S

’

B

G

gds =∂ID

∂VDS

= µCox

W

L(VGS − Vt) for VDS → 0

Cgs = Covs +12WLCox Cgd = Covd +

12WLCox

C′sb

= Csb +12WLCJ(VSB) C′

db= Cdb +

12WLCJ(VDB)


MOST Small-Signal Model in Cutoff Region

S D

Cgd

Cdb

Cgs

Csb

B

G

Cgb

Cgs = Covs Cgd = Covd

• Cgb is highly nonlinear and dependent on the gate voltage.



EEc

vd

vscl

gmgm = k

′WLVov

gm(max)

Vov

Vov ≈ EcL

vd = Carrier Drift velocity =µE

1 + E/EcEc ≈ 1.5 × 106 V/m

• µ is the low-field mobility.

In the triode region

ID = WQI(y) · vd ⇒ ID =µCox

1 + 1Ec

VDS

L

· WL


12V 2DS

]



Using ∂ID/∂VDS = 0 to find VDSAT , we have

VDSAT = EcL

√

1 +2VovEcL− 1

= Vov

(1 −

Vov

2EcL+ · · ·

)

And the saturation current is

IDSAT =12µCox

W

LV 2DSAT

=12µCox

W

LV 2ov

(1 −

Vov

2EcL+ · · ·

)2

The transconductance is

gm = WµCoxEc

√1 + 2Vov

EcL− 1√

1 + 2VovEcL

orgm

ID=

2

EcL√

1 + 2VovEcL

(√1 + 2Vov

EcL− 1)


Effects of Carrier Velocity Saturation

• If Vov EcL,

IDSAT ≈12

µCox

1 + VovEcL

W

LV 2ov gm ≈ µCox

W

L

Vov

1 + VovEcL

gm

ID≈ 2

Vov

– The mobility degradation can be modeled by a resistor RSX = 1Ec

1µCox

1W

in serieswith the source of an ideal square-law device.

– Velocity-saturation effects are insignificant in hand calculations if Vov < 0.1EcL.

• If Vov EcL,

IDSAT ≈ µCoxW VovEc = WCoxVovvscl gm ≈ WCoxvsclgm

ID≈ 1

Vov

– vscl = µEc is the scattering-limited velocity.– IDSAT is a linear function of Vov , and independent of L.


Hot Carriers

IDB = K1(VDS − VDSAT )IDe−K2/(VDS−VDSAT )

gdb ≡∂IDB

∂VD=

IDB

VD − VDSAT

(K2

VDS − VDSAT

+ 1)≈

K2IDB

(VDS − VDSAT )2

• K1 ∼ 5 V−1 and K2 = 30 V are process-dependent parameters.


Short-Channel Effects

• Hot Carriers.

– The drain-to-substrate current can be modeled by a finite drain-to-substrateresistor.

– The punch-through current is an additional cause of lower ro and possibly transistorbreakdown.

– Some charges in the gate current can be trapped in the gate oxide, causing a shiftin Vt.

– The host-carrier effects are more pronounced for nMOST than for pMOST, becauseelectrons have larger velocities than holes.

• Drain-Induced Barrier Lowering (DIBL)

– For short-channel devices, DIBL effectively lowers Vt as VDS is increased, therebyfurther lowering the ro.

• Carrier Velocity Saturation.



( I W/L)t

Tn

1

U

I D /

g m I D/

1000.10.010

Weak Inv. Asymptote

Strong Inv. Asymptote

Moderate

Weak Strong101

In the weak inversion region

ID = ItW

LeVov/(nUT )

(1 − e−VDS/UT

)n =

Cox + Cdepl

Cox

= 1 + χ ≈ 1.5

• It ∝ Dnnpo depends on process parameters (e.g., 20 nA).



When |VDS | > 3UT , ID saturates and

gm ≡∂ID

∂VGS

=ID

nUT

=ID

UT

Cox

Cox + Cdepl

gm

ID=

1nUT

=1UT

Cox

Cox + Cdepl

To find Vov for strong inversion, let

gm

ID=

1nUT

=2Vov

⇒ Vov = 2nUT ≈ 78 mV

• 2nUT < Vov → Strong Inversion0 < Vov < 2nUT → Moderate Inversion

Vov < 0 →Weak Inversion

• In weak inversion, Cgs Cgd 0, and

Cgb = WL × (Cox‖Cdepl ) = WL × CoxCdepl/(Cox + Cdepl )


Integrated Circuit Technologies

Jieh-Tsorng Wu

July 16, 2002

A

1896


Integrated-Circuit NPN Transistor

Emitter Diffusion 0.5–2.5 µm, 2–10 Ω/Base Diffusion 1–3 µm, 100–300 Ω/Isolation Diffusion 20–40 Ω/Epitaxial layer 17 µm (BVCEO = 36 V)

1015 atoms/cm3, 5 Ω-cmBuried layer 20–50 Ω/P-Substrate 250 µm

1016 atoms/cm3

1–2 Ω-cm

• Junction isolation.

Technologies 4-2 Analog ICs; Jieh-Tsorng Wu

Lateral PNP Transistor

• Lightly doped base.

• Slow.

• Low current gain, especially as IC ↑.


Vertical PNP Transistors

• Low base resistance.

• Low emitter-base breakdown voltage.

• Substrate collector (no buried layer).


Advanced-Technology NPN Transistor

Emitter 0.1 µmBase 0.1 µmEpitaxial layer 1 µm, 0.5 Ω-cmBuried layer 20–50 Ω/P-Substrate 250 µm

1016 atoms/cm3

1–2 Ω-cm

• Oxide isolation.

• Polysilicon emitter self-aligned structure.

• High fT (> 10 GHz).


Base and Emitter Diffused Resistors


Base Pinch Resistor


Epitaxial Resistor


Properties of IC Resistor


Capacitors

• PN junctions.

• Metal or poly over thin oxide.


Diodes

(a) (b) (c) (d)

• Implementation (a) is usually preferred to avoid forward biasing the C-B junction.

• C-B forward bias injects carriers into the epi, which in turn can be collected in thesubstrate.


CMOS Integrated-Circuit Technologies

0.5 µm CMOSM2 1.20 µmM1 0.60 µmPoly 0.25 µmField Oxide 0.30 µmGate Oxide 130 Ån+ Depth 0.20 µmp+ Depth 0.25 µmN-well Depth 2.50 µm

• Additional polysilicon layer may exist to realize poly-to-poly capacitors.

• There are twin-tub processes that have separate and optimized wells for nMOSTs aswell as pMOSTs.

• Additional processing steps may be used to fabricate vertical bipolar transistors onthe same chip. This is called a BiCMOS technology.


MOS Transistors

• May have devices with different Vt.

• Source/drain can be shared between two series-connected MOSTs of the same type.

• Wide devices usually employ stacked layout.


Parasitic BJTs in CMOS Technologies

C2

C2BC1EB C

Lateral PNP TransistorVertical PNP Transistor

E

C1

p+ p+

VSS

p+

VSS

VDD

p+

N-Well

n+n+p+

N-Well

P-Substrate P-Substrate

• The collector is usually in ring form surrounding the emitter.

• In the lateral devices, the MOST’s L is the base width.

• The ratio of IC2/IC1 is poorly controlled in practice.


Resistors in CMOS Technologies

• n+ and p+ diffusion

– 10–30 Ω/

• Polysilicon

– 20–80 Ω/

• N (or P) well diffusion

– 1k–10k Ω/

• MOSTs in the triode region

– Depends on Vov and W/L

Polysilicon Resistor

• Large R variation due to process variation.

• Matching properties is ∼1%.

• Small voltage coefficient.

• No parasitic pn junction.


Capacitors in CMOS Technologies

• Poly-Poly

• Poly-Metal

• Metal-Metal (MIM)

• Multi-Layer Sandwich.

• Lateral structures.

• MOSTs in triode region

• MOS in accumulation

– Large voltage coefficient.– Large R in one terminal.

Poly-Poly Capacitor

• Bottom-plate Cparasitic is 10%–30% of C itself.

• Matching properties is 0.1%–1%.

• Voltage coefficient is < 50 ppm/V.

• Temperature coefficient is < 50 ppm/C.


Matching Issues

Mismatches between two supposedly identical devices are due to

• Localized geometric variation.

– Resulting from the limited resolution of the photolithographic process itself

• Global material gradient variation.

– Variations across wafer resulting from nonuniform conditions during the fabricationprocesses.

• Temperature gradient variation.



Device Considerations:

• Match devices of equal nature.

– e.g., no JFET-MOST pair or poly-diffusion resistor pair.

• Devices to be matched should operate on the same temperature.

• Input offset voltage for a BJT pair is only ∼1/10 that for a MOST pair.

• May consider post-fabrication trimming.



Local Matching Consideration:

• Increase device size.

• Round devices matches better than square devices.

• Whenever possible, utilize series and/or parallel combination of unit-sized devices toform devices of different sizes.

• Use dummy devices to protect matching devices from different etch effects.



Global Matching Consideration:

• Layout devices with the same orientation.

• Decrease device separation distance.

• Try a common-centroid layout for the devices to be matched.

12

2

M1 21

M2

1M12

1M2


Transistor Pair Layout Example


Resistor Pair Layout Example


Capacitor Pair Layout Example


Capacitor Errors

e y

x

Assume a rectangular capacitor with dimension x and y . Then

Cideal = Cox · x · y

Due to lithography modification ∆e, we have

Ctrue = Cox · (x − 2∆e) · (y − 2∆e) ≈ Cideal · (1 − εr)

εr = 2∆e × x + y

xy= ∆e × Perimeter

Area


Capacitor Layout Design

To minimize capacitor ratio error, want

• Capacitors of identical values should have the same shape.

• Capacitors of different values should have the same perimeter-to-area ratio.

Let unit-size capacitor Cu have a square layout with xu on each side. Want to realize anew capacitor C with dimension x and y so that

C

Cu

= K and12

PerimeterArea

=2xu

x2u

=x + y

x · y

We have

x · yx2u

=x + y

2xu

= K ⇒ y = xu

(K ±

√K 2 − K

)x =

Kx2u

y

• K is usually between 1 and 2.


Analog Section Floor Plan Example


Noise-Coupling Layout Considerations

• Want to minimize noise from digital circuits coupling into the substrate or analog powersupplies.

• Separate power lines for analog and digital circuits.

• Different region for analog and digital circuitry, separated by guard rings and wellsconnected to the power supplies.

• Use metals and wells as shield to protect sensitive nodes. The shields must beconnected to clean supply voltages.

• Whenever possible, bypass the power supplies with junction capacitors and/orMOSTs.


Latch-Up in CMOS Technologies

VDD

Rp

Rn

Q1

Q2

• Keep Rp and Rn small by having low-impedance paths between the substrate andwell to the power supplies.

• Avoid currents flowing in substrate and wells.

• Transistors that conduct large current must be surrounded by guard rings.


Single-Transistor Gain Stages

Jieh-Tsorng Wu

October 25, 2002

A

1896


Unilateral Two-Port Network

i1

Ziv1 Gm

2

Thevenin Output Model

Zov v1

i2

v2

i1

Ziv1 1

Norton Output Model

Zo i

vA v2

Zi =v1

i1Zo =

v2

i2

∣∣∣∣v1=0

Av =v2

v1

∣∣∣∣i2=0

Gm =i2

v1

∣∣∣∣v2=0

Av = Gm × Zo

Single-T Gain Stages 5-2 Analog ICs; Jieh-Tsorng Wu

Common-Emitter Configuration

VCC

Q1

VI

RS

RL

IB

vi

VO + vo

• DC voltage VI establishes bias of Q1 so that it is on the forward-active region. Typicallywant VO ≈ VCC/2.


Common-Emitter Configuration — Bias Analysis

VCCVI

RS RL

VBE

ICIB

IC = ISeVBE/UT = βF IB

If Q1 is in the forward-active region, voltage across the emitter junction can beapproximated by a constant VBE (on).

IB =VI − VBE (on)

RS

VO = VCC − ICRL = VCC − βF IBRL = VCC − βF

RL

RS

[VI − VBE (on)

]

• Dependence on βF is a problem with this direct approach to biasing.


Common-Emitter Configuration — Small-Signal Analysis

RS

RLv1vi

ii

vo

io

rπ gmv1 ro

rb

Av(0) ≡vo

vi

∣∣∣∣ω=0

= −(

rπ

R′S+ rπ

)· gm · (ro ‖ RL) where R′

S≡ RS + rb

Ri ≡vi

ii= R′

S+ rπ Ro ≡

vo

io

∣∣∣∣vi=0

= ro ‖ RL = R′L

• Note that for R′S → 0 and RL→∞

Av(0)→ −gmro = −1η= −

VA

UT


Common-Source Amplifier

+

-

vin

VIN

RS v + Vo O

LZ

VDD

M1

Vo = VDD − Id · RL = VDD −12µnCox

W

L(Vi − Vtn)2 · RL

• DC voltage VI is chosen to bias M1 so that M1 is in active (saturation) region and itsdrain voltage is near the midpoint of the output swing (VO ≈ VDD/2).


Common-Source Configuration — Small-Signal Analysis

i oi i

LR

RS

vin vgs

mg

ro

vgs

vo

Av(0) = −gm(ro ‖ RL) = −gmR′L

Ri =∞ Ro = ro ‖ RL = R′L

• Note that for RL→∞, R′L→ ro, and

|Av(0)|max = gmro =ID

Vov/2×Lef f

ID

∣∣∣∣∂Lef f

∂VDS

∣∣∣∣−1

=2Lef f

Vov

∣∣∣∣∂Lef f

∂VDS

∣∣∣∣−1


Common-Emitter Configuration Small-Signal AC Analysis

RS

RLv1vi

ii

vo

io

rπ Cπ

Cµ

gmv1 ro

rb

⇒

if1i oi

1v

gm

R

C1

1 C

vs vo

f

v1 CR2 2

vs = vi ×(RS + rb) ‖ rπ

RS + rbR1 = (RS + rb) ‖ rπ R2 = ro ‖ RL

C1 = Cπ C2 = CL + Ccs Cf = Cµ


Common-Source Configuration Small-Signal AC Analysis

gsv

gm

vo

LR

vin

RS

Cgs

Cgd

ro

vgs LC

⇒

if1i oi

1v

gm

R

C1

1 C

vs vo

f

v1 CR2 2

vs = vi R1 = RS R2 = ro ‖ RL C1 = Cgs C2 = CL Cf = Cgd


Miller Approximation

if1i oi

1v

gm

R

C1

1 C

vs vo

f

v1 CR2 2

vo = (−gmv1 + if )(R2 ‖

1sC2

)if = (v1 − vo)sCf

If R2-C2 is a non-dominant pole, then, at the frequencies of interest

vo ≈ −gmR2v1 if ≈ (v1 + gmR2v1)sCf ⇒if

vi= s(1 + gmR2)Cf = sCM

CM = (1 + gmR2) · Cf = (1 + av0) · Cf = Miller Capacitance


Miller Approximation Equivalent Circuit

oi1 i

1v

gm

R1

tCvs vo

v1 CR2 2

Ct = C1 + CM = C1 + (1 + gmR2)Cf

Av(s) =vo

vs= Av(0)

1

(1 − s/p1)(1 − s/p2)

Av(0) = −gmR2 p1 =1

R1Ct

p2 =1

R2C2


Short-Circuit Current Gain

ii

oiif

1v

gm

1

Cf

C

R1s v1

io ≈ −gm × v1 = −gm × i1R1s

1 + R1s(C1 + Cf )s

Short-Circuit Current Gain = β(s) = −io

ii=

gmR1s

1 + R1s(C1 + Cf )s=

β0

1 + R1s(C1 + Cf )s

Transition Frequency = ωT ≈gm

C1 + Cf

−3 dB Frequency = ωβ =1

R1s(C1 + Cf )=

1β0

gm

C1 + Cf

=ωT

β0


BJT Transition Frequency

For BJTs, we haveR1s = rπ C1 = Cπ Cf = Cµ

ωT = 2πfT =gm

Cπ + Cµ

τT =1ωT

=Cπ

gm

+Cµ

gm

=Cb

gm

+Cje

gm

+Cjc

gm

= τF +Cje

gm

+Cjc

gm


MOST Transition Frequency

For MOSTs, we have

R1s =∞ C1 = Cgs =23CoxWL Cf = Cgd

ωT = 2πfT =gm

Cgs + Cgd

To calculate intrinsic device speed, let ωT ≈ gm/Cgs.

• For square-law device,

gm = µCox

W

LVov ⇒ ωT =

32· µL2· Vov

• For device with carrier velocity saturation,

gm = WCoxvscl ⇒ ωT =32·vscl

L


MOST Transition Frequency — Weak Inversion

For MOSTs in the weak inversion region,

ωT =gm

Cgb

gm =ID

UT

Cox

Cox + Cdepl

Cgb = WL ×CoxCdepl

Cox + Cdepl

ωT =ID

UT

· 1WLCdepl

=It

UT

· 1Cdepl

· 1

L2·ID

IM

• IM = It ·W/L is the maximum ID for device in weak inversion.

Since It ∝ Dn and Dn = µUT , we have

ωT Dn

L2·ID

IM µ

L2· UT ·

ID

IM



if1i oi

1v

gm

R

C1

1 C

vs vo

f

v1 CR2 2

Av(s) =vo(s)

vs(s)= Av(0)

1 − s/z1

1 + b1s + b2s2

Av(0) = −gmR2

z1 = +gm

Cf

b1 = R1(C1 + Cf ) + R2(C2 + Cf ) + gmR1R2Cf

b2 = R1R2(C1C2 + C1Cf + C2Cf )



Using the dominant-pole approximation, let |p1| |p2|

D(s) = 1 + b1s + b2s2

=(

1 − s

p1

)(1 − s

p2

)= 1 − s

(1p1

+1p2

)+

s2

p1p2≈ 1 − s

p1+

s2

p1p2

p1 ≈ −1b1

=1

R1[C1 + Cf (1 + gmR2)] + R2(C2 + Cf )≈ − 1

R1[C1 + Cf (1 + gmR2)]

p2 ≈ −b1

b2=

R1(C1 + Cf ) + R2(C2 + Cf ) + gmR1R2Cf

R1R2(C1C2 + C1Cf + C2Cf )≈ −

gmCf

C1C2 + C1Cf + C2Cf

• The Miller approximation is a simplified dominant pole approximation.

• The Miller approximation results in incorrect estimation for the second pole.


Common-Emitter Amplifier with Emitter Degeneration

Q1

RE

RE

RE

v1

v1

vi

vi

vi

ii

ii

vo

vo

vo

io

io

ve

rπ Cπ

Cµ

Cµ

gmv1 ro

rπeqCπeq

gmeqv1

roeq



To find rπeq, Cπeq, and gmeq, let vo = 0, then

(gm + gπ + sCπ)(vi − ve) = (GE + go)ve

At frequencies where ω ωT = gm/(Cπ + Cµ),

ve

vi=

gm + gπ + sCπ

gm + gπ + GE + go + sCπ

≈gm + gπ

gm + gπ + GE + go

gmeq =−iovi

= gm

(1 −

ve

vi

)−go ·

ve

vi=

gmGE − gogπ

gm + gπ + GE + go

= gm ·1 − RE

βoro

1 + gmRE

(1 + 1

βo+ 1

gmro

)ii

vi= (gπ + sCπ)

(1 −

ve

vi

)= (gπ + sCπ)

1 + RE

ro

1 + gmRE

(1 + 1

βo+ 1

gmro

)



• If β0 1, ro RE , and gmro 1

gmeq ≈gm

1 + gmRE

rπeq ≈ rπ(1 + gmRE ) Cπeq ≈Cπ

1 + gmRE

To find roeq, let vi = 0, then

(gm + gπ + sCπ + GE )ve = go(vo − ve)

ve

vo=

go

gm + gπ + GE + go + sCπ

≈go

gm + gπ + GE + go

goeq =io

vo= go

(1 −

ve

vo

)−gm

ve

vo= go ·

gπ + GE

gm + gπ + GE + go

= go ·1 + gmRE

βo

1 + gmRE

(1 + 1

βo+ 1

gmro

)roeq ≈ ro(1 + gmRE ) if gmRE β0 roeq ≈ ro(1 + β0) if gmRE β0


Common-Source Amplifier with Source Degeneration

RS

vs

Cgs

gm

vgs gmb

vs

gsv

gmeq

Cgseq

vgs

v

v

o

oi

oi

RS

gs

v

i

i i

o

SR

vo

vi

v

i i

i

v

Cgd

ro

Cgd

roeq

M1



To find Cgseq and gmeq, let vo = 0, then

(gm + sCgs)(vi − vs) = (GS + gmb + go)vs

At frequencies where ω ωT = gm/Cgs,

vs

vi=

gm + sCgs

gm + gmb + GS + go + sCgs

≈gm

gm + gmb + GS + go

gmeq =−iovi

= gm

(1 −

vs

vi

)−(gmb+go)

vs

vi=

gmGS

gm + gmb + GS + go

=gm

1 + (gm + gmb)RS + RS

ro

ii

vi= sCgs

(1 −

vs

vi

)= sCgs ·

1 + gmbRS + RS

ro

1 + (gm + gmb)RS + RS

ro



• If ro RS,

gmeq ≈gm

1 + (gm + gmb)RS

=gm

1 + (1 + χ )gmRS

Cgseq = Cgs ·1 + gmbRS

1 + (gm + gmb)RS

= Cgs ·1 + χgmRS

1 + (1 + χ )gmRS

To find roeq, let vi = 0, then

(gm + gmb + sCgs + GS)vs = go(vo − vs)

vs

vo=

go

gm + gmb + GS + go + sCgs

≈go

gm + gmb + GS + go

goeq =io

vo= go

(1 −

ve

vo

)− (gm + gmb)

ve

vo=

goGS

gm + gmb + GS + go

roeq = RS + ro[1 + (gm + gmb)RS ]

• roeq can be made arbitrarily large by increasing RS.


Common-Base Configuration

VCC

Q1

RL RL CL

v1

vi ii

vo

rπ Cπ ro

VO + vo

II − ii

gmvi

• It is a current buffer, i.e., current gain 1, low Rin, and high Rout.

• Typically neglect rb, rc, and re, so that v1 = −vi .

• Combine Cµ, Ccs, and load capacitance into CL.


Common-Base Configuration AC Analysis

To further simplify the analysis, neglect ro; i.e., assume go(vo − vi) gmvi , then

(gπ + sCπ)vi + gmvi = ii (GL + sCL)vo = gmvi

⇒ Zt(s) =vo(s)

ii(s)=

gm

gm + gπ + sCπ

× 1GL + sCL

=Zt(0)(

1 − s/p1

) (1 − s/p2

)Zt(0) =

gm

gm + gπ

RL =βo

βo + 1RL = αoRL p1 = −

gm + gπ

Cπ

= − 1αo

gm

Cπ

p2 = − 1RLCL

Input Impedance = Zin(s) =vi(s)

ii(s)=

Rin

1 − s/p1

Rin = Zin(0) = rπ ‖1gm

=αo

gm

Current Gain =io(s)

ii(s)=

gmvi

ii= gmZin(s) =

αo

1 − s/p1

• Note that |p1| = (1/αo)(gm/Cπ) > ωT = gm/(Cπ + Cµ).

• Expect |p2| < |p1| in typical cases.


Common-Gate Configuration

vin

IIN iin-

V o

LCLR

vin

iin

Cgs

g mb

-g m

vo

LR

VDD

Bias

C

C’

gd

vin go

vin

sb

Ct

g′m = gm + gmb C′L= Ct + Cgd = CL + Cdb + Cgd Cin = Cgs + C′

sb

The nodal equations are

iin = (g′m + sCin)vin − go(vo − vin) g′mvin = (GL + sC′L)vo + go(vo − vin)



If the go(vo − vin) terms are neglected, then

Transimpedance = Zt(s) =vo

iin=

RL(1 − s/p1

) (1 − s/p2

)

p1 = −g′m

Cin

= −g′m

Cgs + C′sb

p2 = − 1

RLC′L

Input Impedance = Zin(s) =vin(s)

iin(s)=

1/g′m1 − s/p1

Current Gain =io(s)

iin(s)=

g′mvin

iin= g′mZin(s) =

1

1 − s/p1

• Note that p1 ωT = gm/(Cgs + Cgd ).



If go is considered,

Voltage Gain = Av(s) =vo

vin=

g′m + go

go + GL + sC′L

Input Impedance = Yin(s) =iin

vin= g′m + sCin − go(Av − 1)

Zt(s) =vo

iin=

Av(s)

Yin(s)

• At low frequencies where ω→ 0, assuming g′m go,

Av =g′m + go

go + GL

≈g′m

go + GL

⇒ Yin = g′m −g′m

1 + GL

go

+ go ≈g′m

1 + RL

ro

Zt =Av

Yin≈ RL


Common-Collector Configuration (Emitter Follower)

VCC

Q1

VI

RS

RL RLCL CL

R′S

v1

vi

vi

ii

vo

rπ Cπ

Cµ

gmv1

VO + vo

IBIAS

R′S= RS + rb

• It is a voltage buffer, i.e., voltage gain 1, high Zin, and low Zout.

• Neglect Cµ, re, rc, and ro in the following analysis.



Summing currents at the output, we have

iiv1 + gmv1 = (GL + sCL)vo ii = (gπ + sCπ)v1 vi = R′Sii + v1 + vo

We have

Av(s) =gm + gπ + sCπ

gm + gπ + sCπ + (GL + sCL)[1 + R′S(gπ + sCπ)]

= Av(0)1 − s/z1

1 + b1s + b2s2

Av(0) =gm + gπ

gm + gπ + GL(1 + R′Sgπ)

=gm/αo

gm/αo +1RL

(1 + gmR′S/βo)

=gmRL

gmRL + αo +gmR′

S

βo+1

z1 = −gm + gπ

Cπ

= −gm/αo

Cπ

−ωT

b1 =RL[Cπ(1 + R

′S/RL) + CL(1 + gmR

′S/βo)]

1 + gm(RL/αo + R′S/βo)

b2 =RLR

′SCπCL

1 + gm(RL/αo + R′S/βo)



• If CL = 0, then b2 = 0 and

Av(s) = Av(0)1 − s/z1

1 − s/p1

p1 = −1 + gm(RL/αo + R

′S/βo)

(RL + R′S)Cπ

≈ −1 + gmRL

(RL + R′S)Cπ

Av(0) & z1 are unchanged from case where CL = 0.

• If R′S = 0, again b2 = 0 and

Av(s) = Av(0)1 − s/z1

1 − s/p1

Av(0) =gmRL

αo + gmRL

≈gmRL

1 + gmRL

p1 = −1 + gmRL/αo

RL(Cπ + CL)≈ −

gm

Cπ + CL

if gmRL 1

z1 is unchanged from case where R′S = 0.


Emitter Follower’s Input Impedance

Zin(s) =vi(s)

ii(s)= R′

S+

1gπ + sCπ

+1 + gm/(gπ + sCπ)

GL + sCL

= R′S+ Rin

1 − s/z1(1 − s/p1

) (1 − s/p2

)Rin = (GL + gm/αo)/(GL + gπ) = rπ + (βo + 1)RL ≈ rπ(1 + gmRL)

z1 = −gm/αo + GL

(βo + 1)Cπ + CL

= −1 + gmRL/αo

RL[(βo + 1)Cπ + CL]≈ −

gm

(βo + 1)Cπ + CL

if gmRL 1

p1 = − 1rπCπ

= −gm

βoCπ

−ωT

βo

p2 = − 1RLCL

If CL = 0, then

Zin(s) = R′S+

1 + gmRL

gπ + sCπ

+ RL

B’B

Zin R′S

(1 + gmRL)rπ Cπ/(1 + gmRL)

RL



The output impedance looking into the transistor’s emitter is

Zout(s) =1 + R

′S(gπ + sCπ)

gm + gπ + sCπ

= Rout

1 − s/z1

1 − s/p1

Zout(0) = Rout =1 + R

′Sgπ

gm + gπ

=rπ + R

′S

gmrπ + 1=

rπ + R′S

βo + 1Zout(∞) = R′

S

z1 = −1 + R

′Sgπ

R′SCπ

= −rπ + R

′S

rπR′SCπ

= − 1

(rπ‖R′S)Cπ

p1 = −gm/αo

Cπ

−ωT

• If rπ‖R′S > αo/gm (or R′S > 1/gm if βo 1), |z1| < |p1|, which represents inductive

behavior.

• In addition, if R′S rπ

|z1| ≈1

rπCπ

=gm

βoCπ

≈|p1|βo



If βo 1, Zout(s) can be rewritten as:

Zout(s) =rπ + R

′S + sCπrπR

′S

βo + 1 + sCπrπ≈

(1gm

+R′S

βo+ sCπrπ

R′S

βo

)R′S

R′S+ sCπrπ

R′S

βo

R1

L

R2

Zout

If R2 R1, we have

Zout(s) =(R1 + sL)R2

R1 + R2 + sL≈

(R1 + sL)R2

R2 + sL

Then

R1 =1gm

+R′S

βo

R2 = R′S

L = CπrπR′S

βo


Common-Drain Configuration (Source Follower)

go2

go1vg

m1 gs1

g vomb1

I in

I in

vgs1

gs1C

gs1C

C’L

C’LR’L

I in

V gVDD

IBias LC

V o vo

vo

Cgd1

C’R

CR

gm1

Y g

v

gs1v

gs1

g

g

v

v i g

Simplified Small-Signal Model

S S

S S

R CS S

M1

M2

Bias

C′S= CS + Cgd1 C′

L= CL + C′

sb1 + Cdb2 + Cgd2 G′L= go1 + go2 + gmb1 =

1

R′L



Summing the currents at the output node, we have

(gm1 + sCgs1)(vg − vo) − vo(sC′L+ G′

L) = 0

The voltage gain from gate to output is

Avg(s) ≡vo(s)

vg(s)=

gm1 + sCgs1

gm1 + G′L+ s(Cgs1 + C′

L)= Avg(0)

1 − s/z1

1 − s/p1

Avg(0) =gm1

gm1 + G′L

=gm1

gm1 + gmb1 + go1 + go2Avg(∞) =

Cgs1

Cgs1 + C′L

z1 = −gm1

Cgs1≈ −ωT p1 = −

gm1 + G′L

Cgs1 + C′L



For most practical cases

go1 + go2 gm1 + gmb1 = gm1(1 + χ )

Avg(0) ≈gm1

gm1 + gmb1

≈ 11 + χ1

p1 ≈ −gm1(1 + χ1)

Cgs1 + C′L

≈ (1 + χ1)

1

1 +C′L

Cgs1

z1

|p1| > |z1|

|p1| = |z1|

|p1| < |z1|

(C ’ = 0)L

Avg

Avg

Avg

p1 z1

1

p1

(0)

(0)

(0)

Avg

Avg

Avg

ω

ω

ω


Source Follower’s Gate Input Impedance

The input admittance looking into the gate is

Yg(s) =ig

vg= sCgs1[1 − Avg(s)] =

sCgs1(G′L + sC′L)

gm1 + G′L+ s(Cgs1 + C′

L)

Define the capacitance looking into the gate as

Yg(s) = sCg(s)

Cg(jω) = Cgs1[1 − Avg(jω)]

Cg(0) = Cgs1[1 − Avg(0)]

Cg(∞) = Cgs1[1 − Avg(∞)] =Cgs1C

′L

Cgs1 + C′L

|p1| |z1|

Cg

Cg(∞)

Cg(0)ω



o

gs1CRS gs1

vo

vg m11/

g m11/

g

g

g m1

m1R1

R2

m1

L

Zo

v

i ggv

gm1

i

|Zo|

C

1

|Zo|Rs

1

gs1

Cgs1gs1C

R

R

R

S

S

S

<1

>1

SR

SR

ω

ωgs1

Equivalent Circuit

io = −(gm1 + sCgs1)(vg − vo) GSvg + sCgs1(vg − vo) = 0



The output admittance is

Yo(s) =1

Zo(s)≡

io

vo=

GS(gm1 + sCgs1)

GS + sCgs1= GS +

GS(gm1 − GS)

GS + sCgs1= GS +

1

1gm1−GS

+sCgs1RS

gm1−GS

• Note that

Zo(0) =1

gm1Zo(∞) = RS

• The equivalent circuit is

R1 =1

gm1 − GS

R2 = RS L =RSCgs1

gm1 − GS


Source Follower’s Complete Frequency Response

A(s) =vo

iin=

Avg(s)

GS + sC′S+ Yg

=gm1 + sCgs1

b0 + b1s + b2s2= A(0)

1 − s/z1

1 + sωoQ

+ s2

ω2o

where

A(0) = RS ·gm1

gm1 + G′L

= RS ·gm1R

′L

1 + gm1R′L

z1 = −gm1

Cgs1 −ωT

b0 = GS(gm1 + G′L)

b1 = GS(Cgs1 + C′L) + (gm1 + G′

L)C′

S+ G′

LCgs1

b2 = Cgs1C′L+ C′

S(Cgs1 + C′

L)

and

ωo =

√√√√ GS(gm1 + G′L)

Cgs1C′L+ C′

S(Cgs1 + C′

L)

Q =

√GS(gm1 + G′

L)[Cgs1C

′L+ C′

S(Cgs1 + C′

L)]

GSC′L+ (gm1 + G′

L)C′

S+ G′

LCgs1


Source Follower’s Complete Frequency Response• ωo is the pole frequency and Q is the Q-factor.

• The bandwidth can be estimated by

BW ≈ ωo ≈

√√√√ 1

RS(C′S+ Cgs1)

×gm1 + G′

L

C′L

if C′L C′

S

• If Q < 1/√

2 ≈ 0.707, no peaking in |A(jω)|.

• If Q > 0.5, the poles are complex, and overshoot appears in the step response.

% Overshoot = 100e−π/√

4Q2−1

• If gm1 G′L and C

′L C

′S

1Q≈

√√√√ GSC′L

gm1(Cgs1 + C′S)+

√√√√ gm1C′S

GSC′L(Cgs1/C

′S+ 1)

+

√√√√ G′LCgs1

GS(gm1/G′L)(1 + C′

S/Cgs1)



I in

V g

C1

R1

VDD

IBias LC

V o

C2C1

R1

Y g Y g

R Cinin

M1

M2

Bias

Yg =1

−R1 − 1sC1

+ sC2

R1 =(Cgs1 + C

′L)2

Cgs1(gm1C′L− G′

LCgs1)

≈(Cgs1 + C

′L)2

gm1Cgs1C′L

C1 =Cgs1(gm1C

′L − G

′LCgs1)

(gm1 + G′L)(Cgs1 + C′

L)≈

gm1Cgs1C′L

(gm1 + G′L)(Cgs1 + C′

L)

C2 =Cgs1C

′L

Cgs1 + C′L



• Adding R1 and C1 to the input port can eliminate the complex poles.

• For the compensated source follower, we have

A(s) = [GS + s(C′S+ C2)] · Avg = RS

gm1R′L

1 + gm1R′L

×1 + s

Cgs1gm1(

1 − s/p1

) (1 − s/p2

)where

p1 = −GS

C′S+

Cgs1C′L

Cgs1+C′L

≈ −GS

C′S+ Cgs1

if C′L Cgs1

p2 = −gm1 + G

′L

Cgs1 + C′L

≈ −gm1 + G

′L

C′L

if C′L Cgs1


Floating-Well Source Follower

V o

V in

VDD

p+ p+

V in V o

M2Bias

M1

n+

N-Well

M1

P-Substrate

The follower is in an isolated well tied to the M1 source. Thus, VSB(M1) = 0, and

Avg(0) =gm1

gm1 + go1 + go2

• The junction capacitance at the M1’s source is now replaced by the well-substratejunction capacitor.

• p+ guard-ring surrounding the n-well may be required.


Multiple-Transistor Gain Stages

Jieh-Tsorng Wu

October 24, 2002

A

1896


Dominant-Pole Approximation

The response of an amplifier has the form of

A(s) = A(0)N(s)

D(s)= A(0)

1 + a1s + a2s2 + · · · + ams

m

1 + b1s + b2s2 + · · · + bns

n≈ A(0)(

1 − sp1

)(1 − s

p2

)· · ·(

1 − spn

)

If |p1| |p2|, |p3|, · · · , |pn|, then p1 is a dominant pole. We have

b1 = − 1p1− 1p2− · · · − 1

pn

≈ − 1p1

=

∣∣∣∣ 1p1

∣∣∣∣|A(jω)| = A(0)√[

1 +(

ωp1

)2][

1 +(

ωp2

)2]· · ·[

1 +(

ωpn

)2] ≈ A(0)√

1 +(

ωp1

)2

−3 dB Bandwidth = ω−3dB ≈ |p1| ≈1b1

Multiple-T Gain Stages 6-2 Analog ICs; Jieh-Tsorng Wu

Zero-Value Time Constants

C1 C3

C2

v1i1

v2

i2

v3 i3η

• η is a linear active network without energy storage.

• The b1 in the denominator of the system function can be expressed as

b1 =∑

T0 = R10C1 + R20C2 + R30C3 + · · ·

Ri0 is the driving point resistance seen by Ci with all capacitors equal to zero.


Zero-Value Time Constant Example

fi

1

gm

R1

C1vvs vo

fC

v1 CR2 2

R10 = R1

R20 = R2

To determine Rf0, replace Cf with a current source if , then

v1 = ifR1 vo = −(if + gmv1)R2

Rf0 =v1 − vo

if= R1 + R2 + gmR1R2 = R1

(1 + gmR2 +

R2

R1

)We have

b1 =∑

T0 = R1C1 + R2C2 + (R1 + R2 + gmR1R2)Cf


Darlington Configuration

M1

Q2Q2

Q1

cE Ec

Cc

c

Bc cC

cE

B

iR

cG

c

coR

Bc cC

mVEE

v1

VCC

VEE

VCC

v1

For the BJT-BJT Darlington configuration,

βc = βo2(βo1 + 1) Rci= rπ1 + (βo1 + 1)rπ2 Gc

m =gm2

1 + rπ1(βo1+1)rπ2

Rco = ro2

• Use to boost the effective current gain of BJTs.

• No significant application in pure-MOS circuits.


BJT Cascode Configuration

Vi

VCC

Q2

Q1RS

RL

RL

CL

R′S

v1 v2

i2

vi

voio

gmv1

rπ1 rπ2Ct1 Ct2

gmv2

Rin2

VO + vo

VBIAS

CL = Cµ2 + Ccs2 + Capacitive Load Ct2 = Cπ2 + Ccs1

Ct1 = Cπ1 + Cµ1(1 + gm1Rin2) Rin2 =rπ2 + rb2

βo2 + 1=

αo2

gm2+

rb2

βo2 + 1≈ 1

gm2

• Usually IC2 ≈ IC1, then gm2 ≈ gm1 and Ct1 ≈ Cπ1 + 2Cµ1.

• If RL is large compared to ro2, then Rin2 ≈ (1/gm2)(1 + RL/ro2

).


BJT Cascode Characteristics

We can express voltage gain Av(s) as

Av(s) =vo(s)

vi(s)=

v1

vi

i2

v1

io

i2

vo

io=

(rπ1

R′S+ rπ1

1

1 − sp1

)× (−gm1) ×

(αo2

1 − sp2

)×(

RL

1 − sp3

)

⇒ Av(s) =Av(0)

(1 − s/p1)(1 − s/p2)(1 − s/p3)

Av(0) = −αo2gm1RL

rπ1

R′S+ rπ1

p1 = − 1

(R′S‖rπ1)Ct1

p2 = − 1αo2

gm2

Ct2p3 = − 1

RLCL

The output resistance of the cascode stage is

Rout = ro2 ·1 + gm2ro1

(1 + 1

βo2+ 1

gm2ro2

)1 + gm2ro1

βo2

= ro2

1 +

1 + gm2ro1

1 + gm2ro1βo2

≈ βo2ro2


MOST Cascode Configuration

LR LC

V o

VDD

V1

R

Vin

VDD

V1

I

S

LR LC

V

1

I 2

RS

Vin

BiasM2M1

o

vom2 vg’ s2

vin

Folded Cascode

RS

vg1

Cgd1

g m1vg1 Cx

r o1

r o2 LR C’L

gs1C

Bias M2

Telescopic Cascode

M1

vs2

g′m2 = gm2 + gmb2 Cx = Cdb1 + C′

sb2 + Cgs2 C′L= CL + Cdb2 + Cgd2


MOST Cascode Low-Frequency Characteristics

The output impedance looking into M2’s drain is

Rot2 = ro1 + (g′m2ro1 + 1)ro2 ≈ g′

m2ro1ro2

The input admittance looking into M2’s source is

Gin2 ≈g′m2

go2/GL + 1

The overall voltage gain is

Av =vo

vin≈ −

gm1

go1 + Gin2×

g′m2

go2 + GL

= gm1 ×g′m2ro1ro2RL

ro2 + g′m2ro1ro2 + RL

≈ gm1 × (Rot2 ‖ RL)

• Let gm = gm1 = g′m2, ro = ro1 = ro2, and gm go. If RL = Rot2 = gmr

2o , then

Gin2 ≈gm

goRL + 1≈

gm

gmro + 1≈ go Av ≈ −

gm

2go

gm

go + GL

≈ −12

(gm

go

)2


MOST Cascode Zero-Value Time Constant Analysis

Using the zero-value time constant method, we have

Rgs10 = RS Rgd10 = RS + Rx0 + gm1RSRx0

Rx0 = ro1 ‖ Rin2 ≈ ro1 ‖[(1/g′

m2)(go2/GL + 1)]

RL0 = RL ‖ Rot2 ≈ RL ‖(g′m2ro1ro2

)∑

T0 = Rgs10Cgs1 + Rgd10Cgd1 + Rx0Cx + RL0CL ω−3dB = 1/(∑

T0

)

• Let gm = gm1 = g′m2, ro = ro1 = ro2, gm go. If RL = Rot2 = gmr

2o and RS = ro, then

Rin2 ≈ ro Rx0 =ro

2RL0 ≈

gmr2o

2Rgd10 ≈ RS +

ro

2+gmroRS

2≈

gmr2o

2

⇒∑

T0 = RSCgs1 +gmr

2o

2Cgd1 +

ro

2Cx +

gmr2o

2CL

• RL0CL usually is the dominant term, unless RS is very large.



Let RL = Rot2 = g′m2ro1ro2, then

Gin2 ≈g′m2

go2RL + 1≈

g′m2

g′m2ro1 + 1

≈ go1

The dc gain is

Av(0) ≈ −gm1

go1 + Gin2×

g′m2

go2 + GL

≈ −12·gm1

go1·g′m2

go2

The dominant pole is

p1 = − 1RL0CL

≈ − 2

g′m2ro1ro2CL

At frequencies where |p1| ω |p2|,

Av(s) =Av(0)

1 − sp1

≈Av(0)

− sp1

≈ −gm1

sCL

= −ωu

sωu = Av(0) · p1 =

gm1

CL



The second pole is approximately at

p2 = −go1 + Yin2

Cx

Yin2 is the resistance looking into the M2’s source at high frequencies.

Yin2 = g′m2 − go2

(vo

vs2− 1)

• At frequencies ω (go2 + GL)/CL,

vo

vs2=

g′m2 + go2

go2 + GL + sCL

≈g′m2

sCL

⇒ Yin2 ≈ g′m2

(1 −

go2

sCL

)+ go2 ≈ g′

m2

p2 ≈ −g′m2

Cx

≈ −gm2

KCgs2≈ −

ωT

K

where K is between 1 and 2 (usually closer to 1).


Active Cascode Configuration

C2

M3

o

V i

Io

g m1 v

go2

vo

i

V

v2

i

biasV og v2mb2

-g m2 (A+1) v

go1

2

V in

oV

A M2

M1

M2

M1

C2 = (A + 1)(Cgs2 + Cgd3) + Cgs3

The M2’s transconductance is boosted as g′m2 = gm2(A + 1) + gmb2, thus

Rot2 = ro1 + ro2 + g′m2ro1ro2 ≈ [gm2(A + 1) + gmb2]ro1ro2

Gin2 ≈gm2(A + 1) + gmb2

go2/GL + 1Gin2 = gm2(A + 1) + gmb2 + go2 if RL = 0


Active Cascode Characteristics

The equivalent transconductance is

Gm =io

vi

∣∣∣∣vo=0

= gm1 ×Gin2

go1 + Gin2= gm1

(1 − 1

1 + [gm2(A + 1) + gmb2]ro1 + ro1/ro2

)

• If A(s) has a dominant pole, i.e, A(s) = ao/(1 − s/p1) ≈ −ωu/s, ωu = ao · |p1|. Thetransfer function Vo/Vi has an additional zero and pole at

z′ = −ωu p′ = −ωu −1

gm2ro1ro2CL

≈ −ωu CL = Capacitor at Vo

• The non-dominant pole at the M2’s source is

p2 ≈g′m2

C2=

gm2(A + 1) + gmb2

(A + 1)(Cgs2 + Cgd3) + Cgs3≈

gm2

Cgs2 + Cgd3

p2 is degraded slightly by the addition of amplifier A.


Super Source Follower Configuration

I

I1

2

M22

V i

V

vgm1 gs1

gs1C

Cgd1

2

VDD

v2

C

g

g

o1

o

vi

voi o

LC

R2

R1 RL

v

g

oVoI

m2CLLR

2

vmb1

M1 gs1v

Ro =vo

io

∣∣∣∣vi=0

= R1 ‖(

ro1 + R2

[1 + (gm1 + gmb1)ro1](1 + gm2R2)

)≈ 1

gm1 + gmb1

(1

gm2ro1

)

Av(0) =vo

vi

∣∣∣∣io=0

=gm1ro1

1 + (gm1 + gmb1)ro1 +R2+ro1

R1(1+gm2R2)

≈gm1ro1

1 + (gm1 + gmb1)ro1 +1

gm2ro2


Differential Gain Stages

Jieh-Tsorng Wu

July 16, 2002

A

1896


Emitter-Coupled Pair

VCC

VEE

Q1 Q2

RC1 RC2

REEIEE

Ic1 Ic2

Vi1 Vi2

Vo1 Vo2

Assume

• Q1=Q2.

• RC1 = RC2 ≡ RC.

• Q1 and Q2 don’t saturate.

• Neglect rb, ro, and rµ.

• Neglect REE , i.e, REE →∞.

Vid ≡ Vi1 − Vi2 Icd ≡ Ic1 − Ic2

Vo1 = VCC − Ic1RC Vo2 = VCC − Ic2RC Vod = Vo1 − Vo2 = −(Ic1 − Ic2)RC = −IcdRC

Ic1 ≈ IS1eVBE1/UT Ic2 ≈ IS2e

VBE2/UT IS1 = IS2 ⇒Ic1

Ic2= e(VBE1−VBE2)/UT = eVid/UT

Differential Gain Stages 7-2 Analog ICs; Jieh-Tsorng Wu

Emitter-Coupled Pair Large-Signal Behavior

Summing currents at the common emitter node with αF 1 = αF 2 ≡ αF

αF IEE = Ic1 + Ic2 = Ic1

(1 + e−Vid/UT

)⇒ Ic1 =

αF IEE

1 + e−Vid/UTIc2 =

αF IEE

1 + e+Vid/UT

Icd = Ic1 − Ic2 = αF IEE

(1

1 + e−Vid/UT− 1

1 + e+Vid/UT

)= αF IEE tanh

(Vid

2UT

)

Vod = Vo1 − Vo2 = −IcdRC = −αF IEERC tanh(Vid

2UT

)= αF IEERC tanh

(−Vid2UT

)


Emitter-Coupled Pair with Emitter Degeneration

• Series feedback used to exchange gain for linearity.

• Linear input range increased by approximately same factor gain is reduced.

• Doesn’t increase linear output range.


Source-Coupled Pair

I SS

I SS

VDD

RD1 RD2

V o1 V o2

I SSVSS

V id

V IMM1 M2

I dd

V i1 V i2

I Id1 d2

V IM

Assume

• M1=M2.

• RD1 = RD2 ≡ RD.

• Neglect ro.

• RSS →∞.

Vid ≡ Vi1 − Vi2 Idd ≡ Id1 − Id2 Vod ≡ Vo1 − Vo2 = −IddRD

Assume M1 and M2 are in the saturation region,

Id1 =12k(Vgs1 − Vt)

2 Id2 =12k(Vgs2 − Vt)

2 k = µCox

W

L



Summing currents at the common source node, we have

Id1 + Id2 = ISS ⇒ Id1 =ISS

2+Idd

2Id2 =

ISS

2−Idd

2

The gate voltages can be written as

Vgs1 = Vt +

√2Id1

KVgs2 = Vt +

√2Id2

K

The differential input voltage is

Vid = Vgs1 − Vgs2 =

√2Id1

k−

√2Id2

k=

√2k

(√Id1 −

√Id2

)

Squaring

V 2id

=2k

[Id1 + Id2 − 2

√Id1Id2

]=

2k

[ISS −

√I2SS− I2

dd

]



Rearrange, then we have

Idd =k

2Vid

√4ISSk− V 2

idand Id1 =

ISS

2+Idd

2Id2 =

ISS

2−Idd

2

Define VIM as the differential input voltage at which one of the MOST is turned off, i.e.,

ISS =k

2VIM

√4ISSk− V 2

IM⇒ VIM =

√2ISSk

=√

2 (Vov1)|Vid=0 =√

2 (Vov2)|Vid=0


Small-Signal Analysis of Differential Amplifiers

i2

vo2

vo1

vo2

vo1

vic

v

2idv v

2idi1v

The differential and common-mode signals are defined as

vid ≡ vi1 − vi2 vic ≡vi1 + vi2

2vod ≡ vo1 − vo2 voc ≡

vo1 + vo2

2

vi1 = vic +12vid vi2 = vic −

12vid vo1 = voc +

12vod vo2 = voc −

12vod[

vo1vo2

]=[A11 A12A21 A22

][vi1vi2

] [vodvoc

]=[Adm Acdm

Adcm Acm

][vidvic

]



The voltage gain are defined as

A11 =vo1

vi1

∣∣∣∣vi2=0

A12 =vo1

vi2

∣∣∣∣vi1=0

A21 =vo2

vi1

∣∣∣∣vi2=0

A22 =vo2

vi2

∣∣∣∣vi1=0

The differential and common-mode gains are

Differential-Mode Gain = Adm =vod

vid

∣∣∣∣vic=0

=A11 − A12 − A21 + A22

2

Common-Mode Gain = Acm =voc

vic

∣∣∣∣vid=0

=A11 + A12 + A21 + A22

2

Differential-Mode-to-Common-Mode Gain = Adcm =voc

vid

∣∣∣∣vic=0

=A11 − A12 + A21 − A22

4

Common-Mode-to-Differential-Mode Gain = Acdm =vod

vic

∣∣∣∣vid=0

= A11 + A12 − A21 − A22



• Usually want to sense vid while rejecting vic, thus want Adm Acm, Acdm, Adcm.

• The common-mode-rejection ratio is defined as

CMRR ≡∣∣∣∣Adm

Acm

∣∣∣∣• In a perfectly balanced circuit, Acmd = Adcm = 0. However, in practice, these transfer

functions are not zero because of component imbalances.

• The ratio Adm/Acdm is important because it indicates the extent to which a common-mode input corrupts the differential output.


Emitter-Coupled Pair Differential-Mode Half Circuit

VCCVCC

VEE

Q1 Q2E

Q1

RC RCRC

RSRSRS

REEiEE

+vod2 −vod

2 +vod2

+vid2+vid

2 −vid2

ve = 0 ⇒ Adm =vod

vid=

vod/2

vid/2= −gm

(rπ

rπ + RS

)(ro‖RC)


Emitter-Coupled Pair Common-Mode Half Circuit

VCC VCC

VEE VEE

Q1 Q2 Q1

RC RCRC

RSRSRS

2REE2REE 2REE

ix

voc vocvoc

vicvic vic

ix = 0 ⇒ Acm =voc

vic= −

gmRC

1 + 2gmREE

αo

≈ −RC

2REE


Emitter-Coupled Pair Input Resistances

i1

R

vi1vi1

Rid2

Rid2

Ric2

vi1vid

ic RicR

Assume RS = 0 and rb = 0. When vic = 0, ib1 = −ib2 ≡ ibd ,

Differential-Mode Input Resistance = Rid ≡vid

ibd

∣∣∣∣vic=0

= 2rπ

When vid = 0, ib1 = ib2 ≡ ibc,

Common-Mode Input Resistance = Ric ≡vic

ibc

∣∣∣∣vid=0

= rπ + 2REE (βo + 1) ≈ 2βoREE

In general

ib1 = +vid

Rid

+vic

Ric

ib2 = −vid

Rid

+vic

Ric



VCC VCC

Q1

Differential-Mode

Q1

Common-Mode

RCRC

RSRS

2REE

CE

2

vid2

vod2

vic

voc

|Adm|

|Acm|

CMRR = |Adm||Acm|

ω

ωzE p1



• Using the Miller approximation, the differential Response can be written as

Adm(s) =vod

vid≈

Adm(0)

1 − s/p1

Adm(0) = −gmRC

(rπ

RS + rb + rπ

)p1 = − 1

Ct[(RS + rb)‖rπ]Ct = Cπ + Cµ(1 + gmRC)

• Because REE is usually large, the common-mode response is typically dominated bythe time constant at the tail node of the pair.

Acm(s) =voc

vic≈ −

RC

ZE (s)≈ Acm(0)

(1 − s/zE

)ZE (s) =

11

2REE+ s

CE

2

=2REE

1 + sCEREE

Acm(0) = −RC

2REE

zE = − 1REECE


Emitter-Coupled Pair Input Offset Voltage and Current

VEE

V o

V i

I

VCC

RC1 R

EE

C2

VCC

RCRC

V OS

I OS

V

2

VEE

I EE

V o

i

Q1 Q2 Q1 Q2

Circuit with No Mismatches

• VOS and IOS is equal to the value of VID = VI1 − VI2 and IBD = IB1 − IB2 that must beapplied to the input to drive VOD = 0.



For BJTs in the forward-active region,

IC = ISeVBE/UT VBE = UT ln

IC

ISIS = A

qn2i Dn

G(VCB)

The output condition is

VOD = −(IC1RC1 − IC2RC2) = 0 ⇒IC1

IC2=

RC2

RC1

Since VOS = VID = VBE1 − VBE2, we have

VOS = UT lnIC1

IS1− UT ln

IC2

IS2= UT ln

(IC1

IC2

IS2

IS1

)= UT ln

[RC2

RC1·A2

A1·G1(VCB1)

G2(VCB2)

]



To describe the mismatch in the components, using

∆X = X1 − X2 X =X1 + X2

2⇒ X1 = X +

∆X

2X2 = X − ∆X

2

Then

VOS = UT ln

RC −

∆RC

2

RC + ∆RC

2

·A − ∆A

2

A + ∆A2

·G + ∆G

2

G − ∆G2

·

= UT ln

1 − 1

2∆RC

RC

1 + 12∆RC

RC

·1 − 1

2∆AA

1 + 12∆AA

·1 + 1

2∆GG

1 − 12∆GG

From Taylor series, if y 1, ln(1 + y) = y − y2

2 + y3

3 − · · · ≈ y . We have

VOS ≈ UT

(−∆RC

RC

− ∆A

A+∆G

G

)or VOS = UT

(−∆RC

RC

−∆IS

IS

)



• The offset voltage drift due to temperature variation is

dVOS

dT=

d

dT

[kT

q

(−∆RC

RC

−∆IS

IS

)]=

k

q

(−∆RC

RC

−∆IS

IS

)=

VOS

T

• Nulling VOS usually doesn’t null dVOS/dT because of how it is accomplished.

• VOS drifts in the 1 µV/C range can be obtained with careful design.

RC2RC1

R R

VCC

RC1

xx

C2R

VCC

Q1 Q2Q1 Q2


Emitter-Coupled Pair Input Offset Current

The input offset current is defined as

IOS ≡ IBD|VOD=0 = IB1 − IB2 =IC1

βF 1−

IC2

βF 2

As before, the formula can be arranged as

IOS =IC + ∆IC

2

βF + ∆βF

2

−IC −

∆IC2

βF −∆βF

2

≈IC

βF

(∆IC

IC−∆βF

βF

)

Since VOD = 0, we have

IC1RC1 = IC2RC2 ⇒∆IC

IC= −

∆RC

RC

⇒ IOS ≈ −IC

βF

(∆RC

RC

+∆βF

βF

)

• A typical βF mismatch distribution displays a deviation of about 10%.



M2M1M2M1

SS

RD1 RD2 RDRD

V OS

V i

I SS

V o

VDD VDD

I

VSS VSS

Circuit with No Mismatches

iV

oV

VOS = VGS1 − VGS2 VGS = Vt +

√2ID

k′(W/L)k′ = µCox



Since VOD = 0, we have

ID1RD1 = ID2RD2 ⇒∆ID

ID= −

∆RD

RD

The offset voltage is

VOS = VGS1 − VGS2 = ∆Vt +

√2ID

k′(W/L)×

√√√√√ 1 + 1

2∆IDID

1 + 12∆(W/L)(W/L)

−

√√√√√ 1 − 12∆IDID

1 − 12∆(W/L)(W/L)

Using Taylor series,

VOS ≈ ∆Vt +VGS − Vt

2

[∆ID

ID−∆(W/L)

(W/L)

]≈ ∆Vt +

VGS − Vt

2

[−∆RD

RD

−∆(W/L)

(W/L)

]

VGS − Vt ≡√

2IDk′(W/L)

= Vov =

√2[(ID1 + ID2)/2]

k′(W/L)=

√ISS

k′(W/L)



• ∆Vt can be minimized by careful layout. Large-geometry structures can achieve a ∆Vtwith standard deviations on the order of 2 mV in modern MOS process.

• Due to the VGS − Vt term, offset in MOST pairs is typically 10 times larger than that ofBJT pairs.

• Both Vt and Vov have a strong temperature dependence, affecting VGS in oppositedirections.

• dVOS/dT in MOST pairs is not well correlated with VOS , unlike BJT pairs.


Unbalanced Resistor Circuit Analysis

v11R

i1

v22R

i2

RR

c

Differential HC Common-Mode HC

id2

∆R2

ic 2∆R

cidi

2

vdv

2

vd = v1 − v2 = i1R1 − i2R2 =(ic +

id

2

)(R +

∆R

2

)−(ic −

id

2

)(R − ∆R

2

)= idR + ic(∆R)

vc =v1 + v2

2=

(ic +

id2

) (R + ∆R

2

)+(ic −

id2

) (R − ∆R

2

)2

= icR + id∆R

4


Unbalanced gm Circuit Analysis

i1 i2

cidi

2

g

Common-Mode HCDifferential HC

mg2mg

gm1 1v gm2 2v

∆cv∆gm

22dv

mv

cv2d

id = i1 − i2 =(gm +

∆gm

2

)(vc +

vd

2

)−(gm −

∆gm

2

)(vc −

vd

2

)= gmvd + ∆gmvc

ic =i1 + i2

2=

(gm + ∆gm

2

) (vc +

vd2

)−(gm −

∆gm2

) (vc −

vd2

)2

= gmvc +∆gmvd

4



c

1v

1Ri

2R

∆gm

2mg∆

vo1 vo1

2

v

R

Common-Mode HC

SSR

gm2 vi2gm1 vi1

2

v

s

Differential HC

R

vgm id2

v

v1

2odv

di

2ic 2∆R ∆

id

R2

SS2R

i

oc

d

icv

2

gm 1v

If ∆R = 0 and ∆gm = 0, we have

Adm = −gmR Acm = −gmR

1 + 2gmRSS

Acdm = 0 Adcm = 0



Including mismatches, the voltage gains are

[vodvoc

]=[Adm Acdm

Adcm Acm

][vidvic

]

where

Adm =vod

vid

∣∣∣∣vic=0

= −gmR +∆gmRSS

∆gm2 R − ∆gm

2∆R2

1 + 2gmRSS

Acdm =vod

vic

∣∣∣∣vid=0

= −gm∆R + ∆gmR

1 + 2gmRSS

Adcm =voc

vid

∣∣∣∣vid=0

= −14

gm∆R +

∆gmR − gm∆R

(2gmRSS

(∆gm2gm

)2)

1 + 2gmRSS

Acm =voc

vic

∣∣∣∣vid=0

= −gmR + ∆gm

2∆R2

1 + 2gmRSS


Simplified Analysis for Unbalanced Differential Amplifier

First assume no mismatches, and find Adm, Acm, vod , id , voc, ic, and v1,

Adm = −gmR Acm = −gmR

1 + 2gmRSS

vod = Admvid = −gmRvid id = gmvid

voc = Acvic = −gmRvic

1 + 2gmRSS

v1 =vic

1 + 2gmRSS

ic =gmvic

1 + 2gmRSS

Then consider only the mismatch terms,

−ic∆R

2− R

∆gm

2v1 =

v′od

2⇒ Acdm =

v′od

vic

∣∣∣∣∣vid=0

= −gm∆R + ∆gmR

1 + 2gmRSS

−id

2∆R

2− R

∆gm

2(1 + 2gmRSS)

vid

2= v ′oc⇒ Adcm =

v′oc

vid

∣∣∣∣vic=0

= −14

(gm∆R +

∆gmR

1 + 2gmRSS

)


Current Mirrors and Active Loads

Jieh-Tsorng Wu

November 7, 2002

A

1896


Simple BJT Current Mirror

VCC

Q1 Q2

IIN

IC1

IB1 IB2

IC2

IC2

Vo

Vo

VCE (sat)

βF 1 = βF 2 = βF

VA1 = VA2 = VA

IC1 = IS1eVBE/UT

(1 +

VCE1

VA

)

IC2 = IS2eVBE/UT

(1 +

VCE2

VA

)

IIN = IC1 + IB1 + IB2 = IC1 +IC1

βF

+IC2

βF

IC2 = IC1

IS2

IS1

(1 +

VCE2 − VCE1

VA + VCE1

)= IIN ·

IS2

IS1·

1 + VCE2−VCE1VA+VCE1

1 + 1βF

+ 1βF

IS2IS1

(1 + VCE2−VCE1

VA+VCE1

)IC2 = IIN ·

IS2

IS1· (1 + ε) ε = Systematic Gain Error ≈

VCE2 − VCE1

VA− 1βF

(1 +

IS2

IS1

)Ro2 = ro2 Vo(min) = VCE2(sat) VCC(min) = VBE1(on)

Current Mirrors 8-2 Analog ICs; Jieh-Tsorng Wu

Simple BJT Current Mirror with Beta Helper

VCC

Q1

Q2

Q3

IIN

IC1

IB1 IB3

IC3

Vo

• Ignore Early effect. For Q1 and Q2, let

βF 1 = βF 3 = βF

IC3

IC1=

IS3

IS1

• From KCL,

IIN = IC1+IB1 + IB3

βF 2 + 1= IC1+

1βF (βF 2 + 1)

(IC1+IC3)

IC3 = IC1

IS3

IS1= IIN ·

IS3

IS1· 1

1 + 1βF (βF 2+1)

(1 + IS3

IS1

) = IIN ·IS3

IS1· (1 + ε)

ε ≈ − 1βF (βF 2 + 1)

(1 +

IS3

IS1

)Ro3 = ro3 Vo(min) = VCE3(sat) VCC(min) = VBE1(on) + VBE2(on)


Simple BJT Current Mirror with Emitter Degeneration

Q1

Q2Q3

Q4

VCC

R1 R3 R4

IIN

VB

IC3 IC4

VB = IC1R1 + UT lnIC1

IS1= IC3R3 + UT ln

IC3

IS3

IC1R1

(IC3

IC1

IS1

IS3− 1)= UT ln

(IC1

IC3

IS3

IS1

)

IfIS3

IS1=

R1

R3then

IC3

IC1=

IS3

IS1

• The BJT should be scaled with correspondingemitter resistor.

Ro3 ≈ ro3(1 + gm3R3) = ro3

(1 +

IC3R3

UT

)ε|βF=∞ =

VCE3 − VCE1

VA(1 + gm3RE )=

VCE3 − VCE1

VA

(1 + IC3R3

UT

)Vo(min) = VCE3(sat) + IC3R3 VCC(min) = VBE1(on) + VBE2(on) + IC1R1


Matching Consideration in BJT Current Mirrors

Assume Q3Q4, and let

∆IC ≡ IC3 − IC4 ∆IS ≡ IS3 − IS4 ∆αF ≡ αF 3 − αF 4 ∆R ≡ R3 − R4

IC ≡IC3 + IC4

2IS ≡

IS3 + IS4

2αF ≡

αF 3 + αF 4

2R ≡

R3 + R4

2To calculate mismatch between IC3 and IC4,

VB = VBE3 + IE3R3 = VBE4 + IE4R4 = UT lnIC3

IS3+

IC3

αF 3R3 = UT ln

IC4

IS4+

IC4

αF 4R4

UT lnIC3

IC4− UT ln

IS3

IS4+

IC3

αF 3R3 −

IC4

αF 4R4 = 0

UT ln

IC + ∆IC

2

IC −∆IC2

− UT ln

IS + ∆IS

2

IS −∆IS2

+

(IC + ∆IC

2

) (R + ∆R

2

)αF + ∆αF

2

−

(IC −

∆IC2

) (R − ∆R

2

)αF −

∆αF2

= 0

UT

∆IC

IC− UT

∆IS

IS+ICR

αF

(1 +

∆IC

2IC+∆R

2R−∆αF

2αF

)−ICR

αF

(1 −

∆IC

2IC− ∆R

2R+∆αF

2αF

)= 0


Matching Consideration in BJT Current Mirrors

With above approximations, we obtain

∆IC

IC≈

1

1 + gmR

αF

∆IS

IS+

gmR

αF

1 + gmR

αF

(−∆R

R+∆αF

αF

)

For a typical bipolar process

∆IS

IS ±1% − ±10%

∆αF

αF

±0.1%(npn) ± 1%(pnp)∆R

R ±0.1% − ±2%

• If gmR 1, the IC mismatch is determined by IS mismatch.

• If gmR 1, the IC mismatch is determined by R and αF mismatches.


Simple MOST Current Mirror

D2 VD3

VD1

V

VR M2

I I

M1 M3

D3D2

IINk′ = µnCox

IIN =12k′(W

L

)1

(VR − Vt1)2(1 + λ1VD1)

ID2 =12k′(W

L

)2

(VR − Vt2)2(1 + λ2VD2)

ID3 =12k′(W

L

)3

(VR − Vt3)2(1 + λ3VD3)

Let Vt1 = Vt2 = Vt and λ1 = λ2 = λ, then

ID2 = IIN ·(W/L)2

(W/L)1

·1 + λVD2

1 + λVD1= IIN ·

(W/L)2

(W/L)1

· (1 + ε) ε ≈ λ(VD2 − VD1) =VD2 − VD1

VA

Ro2 = ro2 =1

λ2ID2Vo2(min) = Vov2 ≈ Vov1 ≈

√2IIN

k′(W/L)1

VDD(min) = VGS1 = Vt + Vov1


Matching Consideration in Simple MOST Current Mirror

Ignore λ effects. Assume M2M3, and let

∆ID ≡ ID2 − ID3 ∆(W/L) ≡ (W/L)2 − (W/L)3 ∆Vt ≡ Vt2 − Vt3

ID ≡ID2 + ID3

2(W/L) ≡

(W/L)2 + (W/L)3

2Vt ≡

Vt2 + Vt3

2

VR = Vt2 + Vov2 = Vt3 + Vov3 = Vt2 +

√2ID2

k′(W/L)2

= Vt3 +

√2ID3

k′(W/L)3

Neglecting all second order terms, we obtain

∆ID

ID=

∆(W/L)

(W/L)−

∆Vt

Vov/2Vov =

√2ID

k′(W/L)

• To maximize output swing, want a small Vov . But then ∆ID/ID increases as Vovdecreases for a given ∆Vt.


Layout Considerations

Voltage Routing Current Routing

Vg

Vs V’’sV’s

VDD

VSSVSS

VDD



V o

I o

Q2

Q1Q3

Q4

IIN

v1

v2v2

ro1ro1

ro2ro2

rπ1

rπ2rπ2

gm1

gm2

rexgm1v1

gm2v2gm2v2

vovo ioio

gm1 = gm2⇒1rex≈ gm1

1gm1

rπ2 +1

gm2+ 1

gm1

≈gm2

βo2 + 2≈ 1

rπ2⇒ RE = ro1 ‖ rex ≈ rπ2

Ro ≈ ro2

1 +

gm2RE

1 + gm2RE

βo2

≈ ro2

(1 +

βo2rπ2

rπ2 + rπ2

)≈

βo2ro2

2

Vo(min) = VCE1 + VCE2(sat) ≈ VBE3(on) + VCE2(sat) VCC(min) = VBE3(on) + VBE4(on)



Neglect Early effect. Let Q1=Q3,

IC3 = IC1 IC2 = IC1

βF

βF + 1= IC3

βF

βF + 1

From KCL,

IIN = IC4 + IB4 + IB2 = IC3 + IB3 + IB1 + IB2 = IC3 +IC3

βF

+IC3

βF

+IC3

βF + 1

Thus

IC2 = IC3

βF

βF + 1= IIN ·

βF

βF + 1· 1

1 + 2βF

+ 1βF +1

= IIN ·(

1 −4βF + 2

β2F+ 4βF + 2

)

IC2 = IIN(1 + ε) ⇒ ε = −4βF + 2

β2F+ 4βF + 2

≈ − 4βF + 4


MOST Cascode Current Mirror

3V

IIN

1

2

go2

-g v2m2 g mb2 v2

g

V

V v

o1

iovo

2

M2

M3

M4

I

V

o

o

M1

Ro = ro1ro2(gm2 + gmb2 + go1 + go2) ≈ ro1ro2gm2(1 + χ2)

Vo(min) = VDS1 + VDSAT2 = Vt3 + Vov3 + Vov2

VDD(min) = VGS3 + VGS4 = Vt3 + Vt4 + Vov3 + Vov4

ε 0


MOST High-Swing Cascode Current Mirror

4LW

Vov

o

V 1

V 2

VV o

VDD

M3

M2

M1M6

V

V

3

4

M5

I o

VDD

I IN

M3

M4

I IN

V t

M1

M2

I o

M4

(W/L)4 =14

(W/L)

⇒ VGS4 = Vt + 2Vov

V1 = Vt + Vov

V2 = 2Vt + 3Vov

V3 = Vt + 2Vov

V4 = Vov

Vo(min) = VDS1 + VDSAT2 = 2Vov VDD(min) = VGS3 + VGS4 = 2Vt + 3Vov

ε ≈VDS1 − VDS3

VA≈

Vov − (Vt + Vov)

VA= −

Vt

VA

• In practice, select (W/L)4 < (1/4)(W/L) due to body effect and design margin.


MOST Sooch Cascode Current Mirror

M5

M3

M4

M6

VA

LW

3LW W

VB

3L

VDD

V

I IN

V

V 4

V 2

V 3V 5

o

INI

VDD

1

MB

MAI o

M1

M2

IIN =12k′(

14W

L

)(VB − Vt)

2

= k′(

13W

L

)[(VB − Vt)VA − 2V 2

A

]

⇒ VB = Vt + 2Vov VA = Vov

V1 = Vt + Vov

V2 = 2Vt + 3Vov

V3 = Vt + 2Vov

V4 = Vov

V5 = Vov

Vo(min) = VDS1 + VDSAT2 = 2Vov VDD(min) = V2 = 2Vt + 3Vov ε = 0


MOST Low-Voltage High-Swing Cascode Current Mirror

4LM5

WM4

M3

V o

24 V

VDD

V 1

VV

M1

M2

3

I o

I INI IN

V1 = Vt + Vov

V2 = Vt + 2Vov

V3 = Vov

V4 = Vov

Vo(min) = VDS1 + VDSAT2 = 2Vov

VDD(min) = V2 = Vt + 2Vov

ε = 0

• In practice, select (W/L)5 < (1/4)(W/L) due to body effect and design margin.

• To bias M2 and M4 in the active region, want V2 − V1 < Vt ⇒ Vov < Vt.


Sackinger Current Mirror

VSS

VSS

VDD

VSS

VDDI in

VDD V o

I o

I B2 I B1

M5M6

M1M2

M3M4

If A =12gm5ro5

⇒ Ro ≈12gm1gm5ro1ro3ro5

Vo(min) = VGS5 + VDSAT1 = Vov1 + Vov5 + Vt

VDD(min) = VGS5 + VV GS1

= Vov1 + Vov5 + 2Vt

• It may be necessary to add local compensation capacitors to the enhancement loopsto prevent ringing during transients.

• The scheme can substantially slow down the settling times for large-signal transients.A typical settling-time might be increased by 50%.


Gatti Current Mirror

I in

VDD V o

I o

VSS VSS

VDDVDD

4 I B I B4 I BI B

VSS

M1M2

M5M6 M7M8

M3M4M3AM4A

VGS5 = Vov3 + Vov7 + Vt

⇒ VDS3 = Vov3

Vo(min) = VDS3 + VDSAT1

= Vov1 + Vov3

VDD(min) = VGS5

= Vov3 + Vov7 + Vt

• If (W/L)1,2,3,4 = n × (W/L)5,6,7,8,3A,4A, keep Iin < nIB.

• M2 can be a fixed-bias cascode. The resulting circuit is less prone to instability.


BJT Wilson Current Mirror

I o

oV

Q2

Q1Q3 Rin

IIN

v1

v2 ro2rπ2

gm1gm3v1

gm2v2

vo io

Ro ≈βo2ro2

2Vo(min) = VBE1(on) + VCE2(sat)

VDD(min) = VBE1(on) + VBE2(on)

ε ≈ −(− 2

β2F+ 2βF + 2

+VBE2

VA

)

Assume Q1=Q2=Q3, then IC1 = IC3, and

IIN = IC3 +IC2

βF

= IC1 +IC2

βF

IC2 = −IE2

(βF

βF + 1

)= IC1

(1 +

2βF

)(βF

βF + 1

)

IO = IC2 = IIN

(1 − 2

β2F+ 2βF + 2

)=

IIN

1 + 2βF (βF+2)


MOST Wilson Current Mirror

M4

M32V

IIN

V m2 ( - )v v1 1

o2

v2

v1

g 2 mb2 v2io

vo

g

Vo

g

V 3

I o

M1

M2

g v2m3g g go3 o1m1

v

gg

g v

3

3mb4

m4o4

Rin

Ro ≈ ro2

1 +

gm2

gm1(1 + χ2) +

gm2

gm1·

gm3

Gin + go3 ·Gin+gm4gm4(1+χ4)

ε ≈ 0 Vo(min) = VGS1 + VDSAT2 VDD(min) = VGS1 + VGS2


Complementary Current Source Load

o2R

vgm1 i

vi

C’L

vo

g

Vi

Vo

L

o1

C

VDD

C

C

gd1

gs1

M2

M1

G′L= go1 + Go2 C′

L= CL + Co2

• The Vo range in normal operation is between VDSAT1 and VDD − Vo2(min).


Current Mirror Load

M0V

i

LC

o

M2

VDD

RLV

M1go1g

m0vi

ii

go0

v gd2

g m2 v1

vo

Ct2

io1C

g m1 Ct1 go2 LR

G1 = gm1 + go1 + go0 Ct1 = Cgs1 + Cgs2 + Cdb0 + Cdb1 + · · · = KCgs1

G′L= go2 + GL Ct2 = CL + Cdb2 + · · ·

Neglect Cgd2 ⇒ AI(s) ≡io

ii

∣∣∣∣vo=0

=gm2

G1 + sCt1=

AI(0)

1 − s/p1

AI(0) =gm2

G1=

gm2

gm1· 1

1 + go1gm1

+ go0gm1

p1 =G1

Ct1≈

gm1

KCgs1=

ωT1

K


Diode-Connected Load

t2VDD V

VDD

Vi

Vi

oV

t1

M1 Sat’d

M1 Off

M1 Linear

Vgo1g

m1vi

-gm2

vo

gmb2

vo

vi voVo

LC

go2C

C

gd1

gs1 C’LM1

M2

G′L= gm2 + gmb2 + go1 + go2 C′

L= CL + Cdb1 + Cgs2 + C′

sb2

Av(0) = −gm1

G′L

= −gm1

gm2 + gmb2 + go1 + go2≈ −

gm1

gm2 + gmb2

Av(0) ≈ −gm1

gm2

(1

1 + χ2

)= −

√2k1ID1

2k2ID2

(1

1 + χ2

)= −

√√√(W/L)1

(W/L)2

(1

1 + χ2

)


Voltage and Current References

Jieh-Tsorng Wu

November 13, 2002

A

1896


Sensitivity and Temperature Coefficient

• The sensitivity of a parameter y to a second one x is defined as

Syx ≡

(∆y

y

)(∆xx

) =x

y· ∂y∂x

• The variation of a parameter y that results from changes in temperature is usuallycharacterized by its fractional temperature coefficient, which is defined as thefractional change per degree centigrade change in temperature.

TCy ≡

(∆y

y

)∆T

=1y· ∂y∂T

Voltage and Current References 9-2 Analog ICs; Jieh-Tsorng Wu

Simple Current Sources

VD2RR

VDDVCC

ID2

Q1 Q2 M2M1

IC2

VC2

IC2 ≈ IC1 ≈VCC − VBE1(on)

R≈

VCC

R

SIC2VCC

=VCC

IC2·∂IC2

∂VCC=

VCC

VCC/R· ∂

∂VCC

(VCC

R

)= R ·

(1R

)= 1

∂IC2

∂T=

1R

∂VCC

∂T−VCC

R2

∂R

∂T= IC2

(1VCC

∂VCC

∂T− 1R

∂R

∂T

)⇒ TCIC2

= TCVCC− TCR


BJT Widlar Current Source

Q1

VCC

Q2

R1

R2

IIN IO

Let βF →∞ and VA→∞,

IIN ≈VCC − VBE1

R1≈

VCC

R1S

IINVCC≈ 1

UT lnIIN

IS1= UT ln

IO

IS2+ IOR2⇒ UT ln

(IIN

IO·IS2

IS1

)= IOR2

If IS1 = IS2 ⇒ UT lnIIN

IO= IOR2

Differentiating both sides of the above equation with respect to VCC,

UT

IO

IIN

(1IO

∂IIN

∂VCC−IIN

I2O

∂IO

∂VCC

)= R2

∂IO

∂VCC⇒

∂IO

∂VCC=

1

1 + IOR2UT

IO

IIN

∂IIN

∂VCC

SIO

VCC=

VCC

IO

∂IO

∂VCC=

1

1 + IOR2UT

VCC

IIN

∂IIN

∂VCC=

1

1 + IOR2UT

S

IINVCC≈ 1

1 + IOR2UT


MOST Widlar Current Source

R1

R2

IO

VDD

IIN

M1 M2

Let VA→∞ and γ → 0,

IIN =VDD − Vov1 − Vt

R1=

12k′(W

L

)1V 2ov1 Vov1 =

√2IIN

k′(W/L)1

Vov1 = Vov2 + IOR2 ⇒ IOR2 +

√2IO

k′(W/L)2

− Vov1 = 0

√IO =

12R2

(−√

2

k′(W/L)2

+

√2

k′(W/L)2

+ 4R2Vov1

)

1

2√IO

∂IO

∂VDD

=1

4R2

1√2

k′(W/L)2+ 4R2Vov1

4R2

∂Vov1

∂VDD

∂Vov1

∂VDD

=

√2

k′(W/L)1

1

2√IIN

∂IIN

∂VDD

SIO

VDD=

Vov1√V 2ov2 + 4IOR2Vov1

SIINVDD≈

Vov1√4V 2

ov1

SIINVDD

=12S

IINVDD


BJT Peaking Current Source

Q1

R

VCC

INI

O

Q2

I

Since

VBE1 − IINR = VBE2

UT lnIIN

IS1− IINR = UT ln

IO

IS2

We have

UT ln(IIN

IO·IS2

IS1

)= IINR

If Q1=Q2, then

IO = IINe−IINR/UT R =

UT

IINln

IIN

IO


MOST Peaking Current Source

M1

R

IIN

OI

VDD

M2

For M1 and M2 in strong inversion

IO =12k′(W

L

)2V 2ov2 =

12k′(W

L

)2

(Vo1 − IINR)2

Vov1 =

√2IIN

k′(W/L)1

For M1 and M2 in weak inversion region,

VGS2 − Vt = nUT ln

(IIN

(W/L)1It

)− IINR

If M1=M2,

IO ≈ It

(W

L

)2e(VGS2−Vt)/(nUT ) ≈ IINe

−IINR/(nUT )


BJT VBE Referenced Current Source

Q1

Q2

VCC

R1

R2

IINIO

IIN =VCC − VBE1 − VBE2

R1

VBE1 = UT lnIIN

IS1

IO =VBE1

R2=

UT

R2ln

IIN

IS1

∂IO

∂VCC=

UT

R2

(IS1

IIN

)(1IS1

∂IIN

∂VCC−

IIN

I2S1

∂IS1

∂VCC

)=

UT

R2

1IIN

∂IIN

∂VCC

SIO

VCC=(VCC

IO

)∂IO

∂VCC=(VCC

IO

)UT

R2

1IIN

∂IIN

∂VCC=

UT

IOR2S

IINVCC

=UT

VBE1(on)S

IINVCC


MOST Vt Referenced Current Source

R1

R2

IIN

VDD

OI

M2

M1

IIN =VDD − VGS1 − VGS2

R1=

VDD − Vov1 − Vov2 − Vt1 − Vt2

R1

Vov1 =

√2IIN

k′(W/L)1

Vov2 =

√2IO

k′(W/L)2

IO =VGS1

R2=

Vt1 + Vov1

R2=

Vt1 +√

2IINk′(W/L)1

R2

SIO

VDD=

Vov1

2IOR2S

IINVDD

=Vov1

2VGS1S

IINVDD


Self-Biasing BJT VBE Reference

VCC

VEE

IO1

IO2

IOIIN

IIN

IO

Q1

R

Q2

Q3

Q5

Q6

A

B

Q4

IIN ≈ IO ·IS3

IS4

IO ≈VBE1

R=

UT

Rln(IIN

IS1

)

TCIO= TCVBE1

− TCR

• Two possible operating states, A and B. State A is stable and desirable.

• State B, where only leakage currents flow, would normally be unstable. However, itmay become stable due to low loop gain under low-current condition.

• There may exist hidden states when the supply is ramping from 0 V.


Self-Biasing BJT VBE Reference with Start-Up Circuit

VEE

IO2

VCC

4V BE(on)

Rs

IIN

Rx V x

IO

IO1

Q1

R

Q2

Q5

Q3 Q6

D1

D2

D3

D4

D5

Q4 • When in zero-current state (B), Vx ≈ 0,and D5 is forward biased, forcing a currentflowing into the self-basing loop.

• Choose Rx so that, in State A,

Vx = IINRx ≥ 2VBE (on)

Thus, D5 is reversed biased and the start-up circuit won’t disturb the self-biasing loopwhen in State A.

• The start-up circuit may also introduce additional bias points.


Self-Biasing BJT UT Reference

VCC

VEE

V BE

IO1

IO2

I IN

IO

IOI IN

Q1

Q3

A

B

Q2

R

Q5

Q6Q4

IIN ≈ IO ·IS3

IS4

UT lnIIN

IS1= UT ln

IO

IS2+ IOR

TCIO= TCUT

− TCR

∆VBE = VBE1 − VBE2 = UT ln(IIN

IO·IS2

IS1

)= UT ln

(IS3

IS4·IS2

IS1

)IO =

∆VBE

R

• The UT reference is a proportional-to-absolute-temperature (PTAT) circuit.

• A start-up circuit is required to avoid the “zero-current” state.


Self-Biasing MOST Vt Referenced Current Source

Start-Up

R

IOIIN

IO1

I

VDD

O2M2

M1

M3M4

M6

M5M11

M13

M12

Vov1 =

√2IIN

k′(W/L)1

Vov2 =

√2IO

k′(W/L)2

IIN

IO=

(W/L)3

(W/L)4

IO =VGS1

R=

Vt1 + Vov1

R=

Vt1 +√

2IINk′(W/L)1

R≈

Vt1

R


Self-Biasing MOST gm Referenced Current Source

V

V

R

R

O1I

INI

VDD

IIIN

IO1

IO2

OI

VDD

O2I

M1 M5

M3M4

M6

M2

O

M2

M3M4

M6

M5M1

k′ = µnCox

α ≡(W/L)2

(W/L)1

> 1

∆V = I · R

Let M3=M4, then

IIN = IO = I

I =12k′(W

L

)1V 2ov1 =

12k′(W

L

)2

(Vov1 − ∆V )2 ⇒ Vov1 =√α

√α − 1

· ∆V

I =∆V

R=

2(√α − 1)2

α

1

k′(W/L)1R2

gm1 =2IVov1

=∆V

R· 2(√α − 1)√α∆V

=2R

√α − 1√α


Self-Biasing MOST VBE and UT Referenced Current Source

Q1 V

ReferenceTUReferenceBEV

RR

Q2

V

Q1

VDD

IOIININI OI

VDD

M1

M3M4

M6

M1

M3M4

M6

M2 M2

∆V = VBE1 ∆V = UT ln

(IS2

IS1·(W/L)3

(W/L)4

)


Band-Gap References

GeneratorPTAT

IC

VBE

K · UT

VO = VBE + KUT

• UT = kT/q = 26 mV at T = 300K. ∂UT/∂T = k/q = 0.087 mV/

C.

• VBE = 600 mV at T = 300K. ∂VBE/∂T ≈ −2 mV/

C.

• Want K = 23 so that ∂Vo/∂T = 0 at 300K and VO ≈ 1.2 V.


Band-Gap References

For a BJT biased in the forward-active region, we have

VBE = VG0

(1 − T

T0

)+ VBE0

T

T0+mUT ln

(T0

T

)+ UT ln

(JC

JC0

)UT =

kT

q

VG0 Bandgap voltage of Si extrapolated to 0K (≈ 1.206 V)

k Boltzmann’s constantm Constant (≈ 2.3)T0 Reference temperatureJC Collector current density (= IC/AE )JC0 Collector current density at T0

Let

VO = VBE + KUT andJC

JC0=(T

T0

)αWe have

VO = VG0 +T

T0(VBE0 − VG0) + (m − α)UT ln

(T0

T

)+ K · UT


Band-Gap References

Then∂VO

∂T=

1T0

(VBE0 − VG0) + (m − α)k

q

[ln(T0

T

)− 1]+ K · k

q

Set ∂VO/∂T = 0 at T = T0, we obtain

K =1UT0·[VG0 + (m − α)UT0 − VBE0

]UT0 =

kT0

q

VO = VG0 + UT (m − α)[

1 + ln(T0

T

)]∂VO

∂T=

k

q(m − α) ln

(T0

T

)

• At T = T0,

VO = VG0 + UT0(m − α)∂VO

∂T= 0

• If T0 = 300K and α = 1, then,

K =1.24 − VBE0

0.0258and VO = 1.24 V at T = T0



Q1 Q2Q2

Q1

R1 R2

R3 R3

R2R1

VCC

VEE VEE

I1I1 I2I2

∆VBE∆VBE

VO

VO

I1

I2=

R2

R1VR2 =

R2

R3∆VBE ∆VBE = UT ln

(I1

I2·IS2

IS1

)= UT ln

(R2

R1·IS2

IS1

)

VO = |VBE1| + VR2 = |VBE1| +R2

R3∆VBE = |VBE1| + UT ×

R2

R3ln(R2

R1·IS2

IS1

)



• Both IC1 and IC2 are proportional to T .

• In n-well CMOS technologies, use vertical pnp BJTs with with collectors tied to VSS .

• Reference: Kujik, JSSC 6/73, pp. 222–226.

Q1 Q2

R1 R2

R3

VEE

I1 I2

VO

VOS

Let VOS be the opamp’s input offset voltage.

VR3 = |VBE1| − |VBE2| + VOS = ∆VBE + VOS

VR2 =R2

R3VR3 =

R2

R3(∆VBE + VOS)

VO = |VBE1| + VOS + VR2

= |VBE1| +R2

R3∆VBE +

(1 +

R2

R3

)VOS

• The ratio R2/R3 is typically 5 ∼ 10.



Cc

VBE

VDD

VSS

M1 M2 M3 M4 M5 M6

M7 M8 M9 M10 M11

M12

R2

R3

Q6

Q5

Q4

Q1

Q2

Q3

VO



VO = 3|VBE | + 3R2

R3∆VBE +

(1 +

R2

R3

)VOS

• Increase number of VBE to suppress the contribution from VOS.

• Opamp doesn’t need to drive resistive load.

• Cc provides a feedforward path for negative feedback to ensure stability.

• Cascode current sources for better current matching.

• M12 is added for auto start-up to avoid the zero-current state.

• Reference: Ahuja, JSSC 12/84, pp. 892–899.



1

VEEVEE

VEE

VEEVEE

Q3 Q4

V o2

R2R1

V o1

VCC VCC

R4

R3

Q1

R12

R11

R4

R3

Q1Q2 Q2

Rx

I1

I1

I2

I2

∆VBE ∆VBE

βF →∞ ⇒I1

I2=

R2

R1I2 =

∆VBE

R3∆VBE = UT ln

(I1

I2·IS2

IS1

)



The output voltages are

VO1 = VBE1 + (I1 + I2)R4 = VBE1 +∆VBE

R3

(I1

I2+ 1)R4

= VBE1 + UT ×R4

R3

(R2

R1+ 1)

ln(R2

R1·IS2

IS1

)

VO2 =(

1 +R11

R12

)[VBE1 + UT

R4

R3

(I1

I2+ 1)

ln(I1

I2·IS2

IS1

)]

• Both I1 and I2 are proportional to T .

• The resistor Rx =(R3R4R11

)‖ R12 is added to cancel the effects of the finite base

currents going through R11.

• Reference: Brokaw, JSSC 12/74, pp. 388–393.


Widlar Band-Gap Reference

VEE

VEE

VCC

Q4

R1R2

R3

Q1Q2Q3

I1I2

I3

∆VBE

Vo

βF →∞I1

IS1=

I3

IS3VBE1 = VBE3

I1

I2=

R2

R1∆VBE = UT ln

I1

I2

IS2

IS1= UT ln

R2

R1

IS2

IS1

VO = VBE1 +R2

R3∆VBE

= VBE1 + UT ×R2

R3ln(R2

R1·IS2

IS1

)

• Both I1 and I2 are proportional to T . I3 can be mirrored from a separate PTAT source.

• In the simplest form, I3 can be implemented with a resistor.



V R

Q1 Q2

I o

M3M4

M2M1

Q3

M5

M6M6

M8

M9 M10

M11

VDD

VSS

V o

R

R = y Ry

x



Let Q2=Q3, IS2/IS1 = n, and M3=M4=M5, then

∆V = UT ln(n)

The output voltage, VO, and current, IO, are thus

VO = VBE3 + UT · y ln(n) and IO =VO

Rx

• A PTAT current from M8 develops a UT -dependent voltage across resistor Ry . Aproper choice of the ratio y can give a band-gap voltage at VO.

• All currents are proportional to T .

• If desired, a temperature-independent output current can be realized by choosing y

to give an appropriate TC to VO to cancel the TC of resistor R2.

• Reference: Song, et al., JSSC 12/83, pp. 634–643.



RG

RG

RG

RG RG

Reference Generator

CL

Reference

VO

Generator

V

Reference Generator

VOV

O

RO

V’O

R



• Feedback is employed in the reference generator. Loop stability must be ensured.

• The stability can be tested by observing the output step response.

• Capacitive loading at the output of reference generator has to be either extremelylarge (i.e., off-chip capacitors, undesirable because of extra pin, lead inductance, ...)or very small (not easy to accomplish).

• Can use buffers to reduce the output loading. But additional offset and drift areintroduced.

• One possible scheme is using separate generators for different parts of system soas to isolate more sensitive circuits from other ones. However, mismatch amonggenerators, area, power, and trimming cost must be considered.


Output Stages

Jieh-Tsorng Wu

December 5, 2002

A

1896


Output Stage Requirements

Vi Output

Stage

Io

LCLR

VoI

Outputo

Stage

Vi

L

o

CR

V

L

• Deliver large output current to low-impedance loads (resistive and/or capacitive).

• Usually is a voltage buffer, i.e., low voltage gain, high Zin, and low Zo.

• High Zin is to maintain voltage gain and bandwidth of previous stage.

• Wide bandwidth if in the feedback loop,

• May need protection against load shorts.

Output Stages 10-2 Analog ICs; Jieh-Tsorng Wu

Output Stage Design Issues

• Frequency response.

• Output impedance.

• Output current.

• Output voltage range.

• Power efficiency.

• Distortion.



For a nonlinear system with input x, the output y can be expressed as:

y = a0 + a1x + a2x2 + a3x

3 + · · ·

With a pure sinusoidal input x = v cosωt,

y = a0 + a1v cosωt + a2v2 cos2 ωt + a3v

3 sin3 ωt + · · ·

= a0 + a1v cosωt +a2v

2

2(1 + cos 2ωt) +

a3v3

4(3 cosωt + cos 3ωt) + · · ·

= b0 + b1 cosωt + b2 cos 2ωt + b3 cos 3ωt + · · ·

where

b0 = a0 +12a2v

2 + · · · b1 = a1v +34a3v

3 + · · ·

b2 =12a2v

2 + · · · b3 =14a3v

3 + · · ·



The harmonic distortion factors are

HD2 ≡∣∣∣∣b2

b1

∣∣∣∣ ≈ 12

a2

a1· v

HD3 ≡∣∣∣∣b3

b1

∣∣∣∣ ≈ 14

a3

a1· v2

The total harmonic distortion (THD) is

THD =

√b2

2 + b23 + · · ·

b1

The SINAD is the ratio of signal plus noise plus distortion powers to noise and distortionpowers, i.e,

SINAD =S + N + D

N + D


Class-A BJT Emitter Follower

Q2

Q1

R3

R2R1

IQ

IoV

Vi

o

LR

VCC

VCC

Vbe1 = UT ln(Ic1

IS1

)Ic1 = IQ +

Vo

RL

⇒ Vi = Vo + Vbe1 = Vo + UT ln

(IQ + Vo/RL

IS1

)


Class-A BJT Emitter Follower Output Power

Vce1 = VCC − (Ic1 − IQ)RL

For a sinusoidal Vo with amplitudes Vo and Io,

Average Output Power = PL =12VoIo

Average Supply Power = Psupply = 2VCCIQ

Maximum output swing and output power are

Vom = VCC − VCE (sat) = IQ · RL Iom = IQ

PL(max) =12VomIom =

12

[VCC − VCE (sat)

]IQ

Power Conversion Efficiency = ηC =PL

PsupplyηC(max) =

14

(1 −

VCE (sat)

VCC

)≤ 1

4


Instantaneous Power Dissipation

Q1 Instantaneous Power Dissipation is

Pc1 = Vce1Ic1

At maximum ηC,

Pc1 = VCC(1 + sinωt) × IQ(1 − sinωt)

=VCCIQ

2(1 + cos 2ωt)

• The maximum Pc1 occurs at the midpointof any load line.


Class-A MOST Source Follower

IQ

IoM1

Vo

Vi

LR

M2

VDD

VDD

Id1 = IQ +Vo

RL

Vi = Vo + Vgs1 = Vo + Vt1 + Vov1

⇒ Vi = Vo + Vt0 + γ

(√2φf + Vo + VDD −

√2φf

)+

√√√√2(IQ + Vo/RL

)k′(W/L)1



Since Vi = f (Vo), we have

Vi = VI + vi =∞∑n=0

bn(vo)n vo = Vo − VO bn =1n!f (n)(VO) ⇒ vi =

∞∑n=1

bn(vo)n

To find

vo =∞∑n=1

an(vi)n

use

vi =∞∑n=1

bn(vo)n =∞∑n=1

bn

( ∞∑m=1

am(vi)m

)n

= b1a1vi + (b1a2 + b2a21)v2

i+ (b1a3 + 2b2a1a2 + b3a

31)v3

i+ · · ·



Matching coefficients, we obtain

a1 =1b1

a2 = −b2

b31

a3 =2b2

2

b51

−b3

b41

• Assume RL→∞, and let VM = VO + VDD + 2φf , vi = vi sinωt, then

a1 =1

1 + γ

2V−1/2M

a2 =γ

8V−3/2M(

1 + γ

2V−1/2M

)3a3 = −

γ

16V−5/2M(

1 + γ

2V−1/2M

)5

HD2 =12

a2

a1· vi =

γ

16

V−3/2M(

1 + γ

2V−1/2M

)2· vi

HD3 =14

a3

a1· v2

i= − γ

64

V−5/2M(

1 + γ

2V−1/2M

)4· v2

i


Class-A BJT Common-Emitter Stage

R1 R2

Q1

Q2

R3

i

IoVo

LRV

IQ

VCC

VCC

Io = IQ − Ic1 ⇒ Vo = IoRL =(IQ − ISe

Vi/UT

)RL

Same output power, ηC, and Pc1 as the class-A emitter followers, since

Vce1 = VCC − (Ic1 − IQ)RL


Distortion in Class-A BJT Common-Emitter Stage

Assume the input isVi = VBE1 + vi IQ = ISe

VBE1/UT

Then, the output voltage is

Vo = −RL

[ISe

(VBE1+vi )/UT − IQ

]= −RLIQ

(evi/UT − 1

)

= −RLIQ

[vi

UT

+12

(vi

UT

)2

+16

(vi

UT

)3

+ · · ·]= a1vi + a2v

2i+ a3v

3i+ · · ·

Let vi = vi sinωt, then the harmonic distortion factors are

HD2 =12

a2

a1· vi =

14

vi

UT

HD3 =14

a3

a1· v2

i=

124

(vi

UT

)2


Class-A MOST Common-Source Stage

IQ

M1

M2

V R

Io

i

Vo

L

VDD

VDD

Vo = IoRL = (IQ − Id1)RL

Id1 =12µCox

W

L(Vi − Vt)

2 =12k(Vi − Vt)

2

Let Vi = VI + vi , VI = Vov + Vt and IQ = (1/2)kV 2ov

Vo = RL (IQ − Id ) = RL

[IQ −

12k(Vov + vi)

2]

= −RLIQ

[2(

vi

Vov

)+(

vi

Vov

)2]

Let vi = vi sinωt, then the harmonic distortion factors are

HD2 =12

a2

a1· vi =

14

(vi

Vov

)HD3 = 0


Class-B Push-Pull Emitter Follower

Q1Io

Q2

Vo

LR

Vi

VCC

VCC


Output Power of Class-B Push-Pull Emitter Follower

Vce1 = VCC − Ic1RL

For a sinusoidal output

Vo = Vo sinωt Io = Vo/RL = Io sinωt

We have

PL =12VoIo =

12

V2o

RL

Isupply =1

T/2

∫ T/2

0Ic1(t)dt =

2π

Vo

RL

=2πIo

Psupply = VCCIsupply =2π

VCC

RL

· Vo

Power Conversion Efficiency = ηC =π

4

Vo

VCC≤ π

4


Class-AB Push-Pull Emitter Followers

Q5Q5

VCC

VEE

VB2

VB1

V1 Vo

VCC

IQ1 VoV1

V

IB1

IQ2

VCC

i

Vo

Vi

IB1

Q1

Q2

Q1

Q2

Q3

Q4

VEE

Q4

Q3

R1

Q1

Q2

VEE

QI

VBE1 + |VBE2| = VBE3 + |VBE4| ⇒ IQ1 = IB1

√IS1IS2

IS3IS4IQ2 =

√IC3IC4

√IS1IS2

IS3IS4


Class-AB Push-Pull Source Followers

VDD

VSS

IB1

V1 VoIQ1

Vi

VDD

VSS

IQ2

IB1

Vi

VoV1

M1

M2

M3

M4

M1

Q2

M3

Q4

M5M6

M5

VGS1 + |VGS2| = VGS3 + |VGS4| ⇒ IQ1 = IB1

1/

√k′n(W/L)3 + 1/

√k′p(W/L)4

1/√k′n(W/L)1 + 1/

√k′p(W/L)2

2



M5

M5

VDD

VSS

IB

Vo

Vi

IQ

V1

V2

VDD

V bon

V bop

B3I

B2I

V oIQ

Vi

V1

V

R1

B12I

M1

M2

VSS

M1

M3

M4

M11

M12

M2

M14

M13

2



Let IB1 = IB2 = IB3, and

1K

(W

L

)1

=(W

L

)11

(W

L

)3

=(W

L

)12

1K

(W

L

)2

=(W

L

)13

(W

L

)4

=(W

L

)14

Then, VGS1 = VGS11, VGS3 = VGS12, VGS2 = VGS13, VGS4 = VGS14, and

IQ = ID1 = ID2 = K · IB1

• M3 and M4 form a floating resistor.

• Large output impedance. The pole at Vo can be significant.

• Large distortion. Usually this output stage is included in the feedback loop.


Class-AB Quasi-Complementary Configuration

EPEP

EN EN

gm1 gs1v

o2

gm2vgs2

vgs2

vgs1

g

Vo

Iov

go1

Vi iV

R

o

L

VSS

VDD

o

i

M1

M2

Go = −io

vo

∣∣∣∣vi=0

= gm1AEP + gm2AEN + go1 + go2

• The distortion and output resistance are reduced by AEP and AEN.

• Need to control IQ.



EN

EP

RL

V

Io

VSS

oi

VOSP

VOSN

VDD

M1

M2

V

AEP = AEN = A

Vtn = −Vtp = Vt

k′p

(W

L

)1

= k′n

(W

L

)2

= k′(W

L

)

Id1 = −12k′W

L(Vgs1 + Vt)

2

Id2 =12k′W

L(Vgs2 − Vt)

2

If Vi = 0 and VOSP = VOSN = 0, let

−ID1 = ID2 = IQ Vov =

√2IQ

k′(W/L)Vgs1 = −Vt − Vov Vgs2 = Vt + Vov



We have

Vgs1 = −Vt − Vov + A[Vo − (Vi − VOSP )] Vgs2 = Vt + Vov + A[Vo − (Vi − VOSP )]

Io =Vo

RL

Io + Id1 + Id2 = 0 ⇒ Vo =Vi −

VOSP+VOSN2

1 + 1k′(W/L)A[2Vov−A(VOSP−VOSN)]RL

• If VOSP = VOSN = 0,

Vo =Vi

1 + 1k′(W/L)A2VovRL

=Vi

1 + 12AgmRL

gm = k′W

LVov

• If A(VOSP − VOSN) 2Vov and 2AgmRL 1,

Vo =Vi −

VOSP+VOSN2

1 + 1k′(W/L)A2VovRL

=Vi −

VOSP+VOSN2

1 + 12AgmRL

≈ Vi −VOSP + VOSN

2



To find IQ when VOSP and VOSN exist, let Vi = 0 and

Vo + VOSP ≈VOSP − VOSN

2Vo + VOSN ≈ −

VOSP − VOSN

2

IQ =12k′W

L

(Vov − A

VOSP − VOSN

2

)2

Define IQ0 = IQ when VOSP = VOSN = 0, and ∆IQ = IQ0 − IQ,

∆IQ =12k′W

LA(VOSP − VOSN)

(Vov − A

VOSP − VOSN

4

)∆IQ

IQ0= A

(VOSP − VOSN

Vov

)(1 − A

VOSP − VOSN

4Vov

)≈ A

(VOSP − VOSN

Vov

)

• Must keep A small to reduce IQ variation.


An Error Amplifier Example

EP

A

VSS

VSS VSS

VSS

I

SSI

Vi Vo

BB

C1

M12

VDD

M1

M14

M16

M13

M15M17

M11

Let

(W/L)15 = (W/L)16 = (W/L)17

(W/L)13 = (W/L)14

⇒ IQ(M1) = ISS ×(W/L)1

(W/L)17

ID13 = ID14 = ISS − IBB/2

Voltage gain is

AEP =gm11

gm14 + gmb14

• Want large swing at node A to provide strong gate drive for M1.

• Reference: Khorramabadi, JSSC 4/92, pp. 539–544.


Combined Common-Drain Common-Source Configuration

EP

EN

IB1

Vi

IB2VOS

VOS

V1

VDD

VSS

oI

R

oV

L

M5 VSSV

VDD

i

M11

M12M2

M4

M1

M3

M6


Combined Common-Drain Common-Source Configuration

• VOS can be introduced by intentionally mismatching the input differential pair in eacherror amplifier.

• The circuit can be designed so that, when Vo = V1 = 0, the introduction of VOS turn offM11 and M12.

• M11 is turned on only when V1 − Vo − VOS > |Vtp|/AEP .

• Error amplifiers, AEP and AEN, can have high gain, and are often designed as one-stage amplifier with gain ≈ gmro.

• The wide bandwidth of M1 and M2 source followers simplify the design required toguarantee stability.

• The V1 voltage range, limited by Vgs3 and Vgs4, can be increased by adding the M6common-source stage.



M24M23

M21 M22

M26M25

EP2 AmplifierEP1 Amplifier

M6M5

2

EP1

Vi

EN1

EP2V2V3

BV

3V2V

2V

M3 B

2V

1V1V M4

V

EN2

V

VDD

B2IB2I

VDDOSV

oI

VSS

VDD

VSS

VOS

VSS

IB1

VDD

oV

LR

VSS

M1

M2

M11

M12



• Want turn off M11 and M12 when Vo ≈ Vi = 0, so that AEP 2 and AEN2 have high gain,and AEP 1 and AEN1 have low gain.

• VOS of EP1 is introduced by making (W/L)3 0.8(W/L)4. When Vo ≈ Vi = 0,

ID3 = IB1 ·(W/L)3

(W/L)3 + (W/L)4

ID1 = (ID3 − IB2) ·(W/L)1

(W/L)3

AEP 1 =gm3

gm5=

√√√√k′n

k′p·(W/L)3

(W/L)5

·ID3

ID3 − IB2AEP 2 ≈ gm22ro22

• When |Vi | is small, and M11 and M12 are not turned on, the output is

Vo =Vi

1 + 1/(A1gm1RL)



• When Vi is large, M11 can be turned on, and the output becomes

Vo ≈ Vi − VOS if AEP 2→∞

• When V2+ = V2− at EP2, define V3 = Vov25 + Vt25 + VSS = VK + VSS . Then

V3 = [Vo − (Vi − VOS)]AEP 1AEP 2 + VK + VSS

Define Vi (min) as the minimum input to turn on M11. Let V3 = VDD − |Vtp11|, we have

Vi (min) = VOS(1 + AEP 1gm1RL) −(VDD − VSS − VK − |Vtp11|)(1 + AEP 1gm1RL)

AEP 1AEP 2

Vi (min) = VOS(1 + AEP 1gm1RL) if AEP 2→∞

M11 and M12 remain off for only a small range of input voltages.


Noise Analysis and Modeling

Jieh-Tsorng Wu

December 5, 2002

A

1896


Noise in Time Domain

n(t)

t

PDF

n

0

0

Mean = n =1T

∫ T0n(t)dt = 0 Noise Power = n2 =

1T

∫ T0n2(t)dt

Root Mean Square = nrms =(n2)1/2

• T is a suitable averaging time interval. Typically, a longer T gives a more accuratemeasurement.

Noise 11-2 Analog ICs; Jieh-Tsorng Wu

Probability Density Function

• The probability that the noise lies between values n and n + dn at any time is givenby P (n)dn. P (n) is the probability density function (PDF).

• The PDF of a random noise is usually Gaussian, i.e.,

P (n) =1√

2πσe− n

2

2σ2

We have ∫ +∞−∞

PDF(n)dn = 1

and

Variance =∫ +∞−∞

n2 · PDF(n)dn = n2 = σ2


Noise in Frequency Domain

f

log f

log f

Spectral Density

Root Spectral Density

n

PowerMeterf

BPF

V2

Hz

V√Hz

One-sided power spectral density

SD(f ) = lim∆f→0

n2(f )

∆f

One-sided root spectral density

RD(f ) = (SD)1/2

The total noise power is

∫ ∞0

SDn(f )df = n2


Noise Summation

n i1

n i2

n i3

n i1

n i2

n o2

H (s)

H (s)2

H (s)

1

3

n o1

If two noises, ni and nj , are uncorrelated then, i.e., ni · nj = 0. Then

n2o1 = (ni1 + ni2)2 = n2

i1 + n2i2 + 2 · ni1ni2 = n2

i1 + n2i2

SDno2(f ) = |H1(j2πf )|2SDni1

+ |H2(j2πf )|2SDni2+ |H3(j2πf )|2SDni3



N1 N2 N3 N4

101010101010 1010 102 3 4 5 6 7f

200

20

2

2

2

2

(nV)2

Hz ∝ 1f

The noise power in each frequency region is

PN1=∫ 102

100

2002

fd f = 2002 ln(f )|102

100 = 1.84 × 105 (nV)2

PN2=∫ 103

102202df = 202 f |103

102 = 3.6 × 105 (nV)2



PN3=∫ 104

103

(20

103

)2

f 2df =(

20

103

)2 13f 3

∣∣∣∣104

103= 1.33 × 108 (nV)2

PN4=∫ ∞104

2002

1 +(

f

105

)2=∫ ∞0

2002

1 +(

f

105

)2df −

∫ 104

02002df

= 2002(π

2

)105 − 2002 · 104 = 5.88 × 109 (nV)2

Total rms of the noise is

nrms =(PN1

+ PN2+ PN3

+ PN4

)1/2= 77.5 µV rms

• 1/f noise tangent principle: Lower a 1/f line until it touches the spectral densitycurve; the total noise can be approximated by the noise in the vicinity of the 1/f line.


Thermal Noise

RRR

v2i2

v2

∆f= 4kTR

i2

∆f= 4kT

1R

f = 0 ∼ ∞

T = Absolute Temperature in Kelvins

k = 1.38 × 10−23 watt/K-Hz (Boltzmann’s Constant)

∆f = Bandwidth per Hertz

• Thermal noise is a white noise, i.e., its power spectral density v2/∆f is independentof frequency, and its amplitude distribution is Gaussian.

• For a 1 kΩ resistor at 300K, v2/∆f ≈ (4 nV/

√Hz)2.


Thermal Noise with Loading

RL

RRC

P n

v2 v2

v2o

• The RL load receives the maximum power if RL = R. Thus the available noise powerfor RL is

Pn =1

4R· v2 · Bn = kTBn Bn = Noise Bandwidth

• For the RC low-pass network

Bn =π

2· 12πRC

=1

4RCv2o = 4kTR · 1

4RC=

kT

C

If C = 1 pF and T = 300K, v2

o = (64 µV)2


Shot Noise

ID

rd i2

rd =kT

qID

i2

∆f= 2qID f = 0 ∼ ∞

q = 1.6 × 10−19 C (Electronic Charge)

kT/q = UT ≈ 26 mV at T =300K

• Shot noise is also a white noise.

• The shot noise from a diode with 50 µA bias current is the same as the thermal noisefrom a 1 kΩ resistor at room temperature.


Flicker Noise ( 1/f Noise)

• Flicker noise, which is always associated with a flow of direct current, displays aspectral density of the form

i2

∆f= K1

Ia

f bf = 0 ∼ ∞

a ≈ 0.5 ∼ 2 b ≈ 1 K1 = a constant for a particular device

• The flicker noise’s power spectral density is frequency dependent, and its amplitudedistribution is non-Gaussian.

• Flicker noise is caused mainly by traps associated with contamination and crystaldefects. The constant K1 can varies widely even for devices from the same wafer.


BJT Noise Model

v1

v2b

i2b i2

crπ Cπ gmv1

Cµrb

ro

rc

Ccs

B B′

E

C

v2b

∆f= 4kT rb

i2c

∆f= 2qIC

i2b

∆f= 2qIB + K1

IaB

f

• All noise sources are independent of each other.

• The thermal noise of rc is neglected.

• Avalanche noise is found to be negligible if VCE is kept at least 5 V below BVCEO.

• Cµ can be neglected in noise calculation.


FET Noise Model

v1gmv1

i2g i2

dCgs

Cgd

ro

G

S

D

i2g

∆f= 2qIG +

1615

kTω2C2gs

i2d

∆f= 4kT (γgd0) + K1

IaD

f

• Since the channel material is resistive, it exhibits thermal noise. γ is a constant, gd0is the channel conductance at VDS = 0.

γ ≈ 23

gd0 ≈ gm


FET Noise Model

• For short-channel device (L < 1 µm), the thermal noise is 2 to 5 times larger than4kT (2/3)gm.

• The gate-current noise, (16/15)kTω2C

2gs, is usually insignificant at low frequencies.

Its correlation with the thermal noise is 0.39.

• IG is the gate leakage current.

• Cgd can be neglected in noise calculation.

• The 1/f noise in the surface devices, such as MESFETs and MOSFETs, is usuallylarger than that of BJTs.

• pMOSTs have less 1/f noise than nMOSTs, since holes are less likely to be trapped.



Noisy

Network Network

Noiseless

RS RS

v2i

i2i

• The noise in network is lumped and represented by a noise voltage generator v2i

and

a noise current generator i2i. This representation is valid for any source impedance, if

correlation between the noise generators is considered.

• And the total input equivalent noise can be found by

viN = vs + vi + iiRS and v2iN

= v2s + v2

i+ i2

iR2S



• In most practical circuits, the correlation between vi and ii is small and may be

neglected. If either v2i

or i2i

dominates, the correlation may be neglected in any case.

• The value of v2i

can be found by shorting the input ports and equating the output noisein each case.

• The value of i2i

can be found by opening the input ports and equating the output noisein each case.



Network

Noiseless

RS

v2s

v2i

i2i

v2s is the thermal noise of RS, i.e.,

v2s = 4kTRS∆f

Assume no correlation between v2i

and i2i, we have

Na

Ni

=v2i+ i2

iR

2S

v2s



Thus, the noise factor for the two-port network is

F =SNRin

SNRout=

Si/Ni

(G · Si)/[G · (Ni + Na)]= 1 +

Na

Ni

= 1 +v2i

4kTRS∆f+

i2iRS

4kT∆f

• For small RS, v2i

dominates, whereas for large RS, i2i

dominates.

• There exits an optimal RS for minimum F :

R2S,opt

=v2i

i2i

and Fopt = 1 +i2iRS

2kT∆f

This is one reason for the widespread use of transformers at the input of low-noisetuned amplifiers.


Noise Generators of a BJT Common-Emitter Stage

v1

v1

gmv1

gmv1

rb

rb

rπ

rπ

Cπ

Cπ

io

io

v2b

i2b i2

c

v2i

i2i

v2b

∆f= 4kT rb

i2b

∆f= 2qIB + K1

IaB

f

i2c

∆f= 2qIC


Noise Voltage Generator of a BJT Common-Emitter Stage

By shorting the input ports, we obtain

io = gmvb + ic = gmvi

Since rb is small, i2b

is neglected. We have

vi = vb +ic

gm

v2i= v2

b+

i2c

g2m

v2i

∆f= 4kT rb +

2qIC

g2m

= 4kT

(rb +

IC/UT

2g2m

)= 4kT

(rb +

12gm

)= 4kTReq

Req = Equivalent Input Noise Resistance = rb +1

2gm


Noise Current Generator of a BJT Common-Emitter Stage

By opening the input ports, we obtain

io = β(jω)ib + ic = β(jω)ii ⇒ ii = ib +ic

β(jω)i2i= i2

b+

i2c

|β(jω)|2

Thus

i2i

∆f= 2q

[IB + K ′1

IaB

f+

IC

|β(jω)|2

]= 2qIeq K ′1 =

K1

2q

Ieq = Equivalent Input Shot Noise Current = IB + K ′1IaB

f+

IC

|β(jω)|2

β(jω) =βo

1 + j ωωβ

=βo

1 + j ffTβo

=βo

1 + βo

Cπ+Cµ

gmjω


BJT Equivalent Input Shot Noise Spectral Density

f a

f 2

log ff b

1/flog

(i2i

∆f

)

At high frequencies

IC

|β(jω)|2=

IC

β2o

(1 +

f2

f 2T

β2o

)≈ IC

f2

f 2T

Let IB = ICf

2b

f 2T

⇒ fb = fT

√IB

IC=

fT√βF


Total Equivalent Noise Voltage of a BJT Common-Emitter Stage

The total equivalent noise voltage with a source resistance RS can be found as

v2iN

∆f=

v2s

∆f+

v2i

∆f+

i2i

∆fR2S

= 4kT(RS + rb +

12gm

)+ R2

S· 2q(IB + K ′1

IaB

f+

IC

|β(jω)|2

)

= 4kT

[(RS + rb +

12gm

)+

R2S

2UT

(IB + K ′1

IaB

f+

IC

|β(jω)|2

)]

= 2qR2S

[2UT

R2S

(RS + rb +

12gm

)+

(IB + K ′1

IaB

f+

IC

|β(jω)|2

)]


Noise Generators of a FET Common-Source Stage

v1

v1

gmv1

gmv1

i2g i2

dCgs

Cgs

ro

ro

v2i

i2i

io

io

i2g

∆f= 2qIG +

1615

kTω2C2gs

i2d

∆f= 4kT (γgd0) + K1

IaD

f


Noise Voltage Generator of a FET Common-Source Stage

By shorting the input ports, we obtain

io = id = gmvi ⇒ v2i=

i2d

g2m

v2i

∆f= 4kTγ

gd0

g2m

+ K1

IaD

g2mf

= 4kTReq K ′1 =K1

4kT

Req = Equivalent Input Noise Resistance = γgd0

g2m

+ K ′1IaD

g2mf≈ 2

31gm

+ K ′1IaD

g2mf

• For MOST, its voltage generator for flicker noise is approximately independent of biascurrent and voltage and is inversely proportional to the gate-oxide capacitance, i.e.,

v2i

∆f≈ 4kT

(23

1gm

)+

Kf

WLCox

· 1f

Kf ∼ 3 × 10−24 V2-F


MOST Equivalent Input Noise Voltage Spectral Density

f a

1/f

log f

log

(v2i

∆f

)

• At frequencies above the flicker noise region, the Req of a FET is significantly higherthan that of a BJT at a comparable bias current.

• For a MOST, it is not uncommon for the fa to extend well into the MHz region.


Noise Current Generator of a FET Common-Source Stage

By opening the input ports, we obtain

io = iggm

jωCgs

+ id = iigm

jωCgs

⇒ ii = ig +jωCgs

gm

id i2i= i2

g +ω

2C

2gs

g2m

i2d

i2i

∆f= 2qIG +

1615

kTω2C2gs +

ω2C

2gs

g2m

(4kTγgd0 + K1

IaD

f

)= 2qIG +ω2C2

gs(4kTReq)

Req = γgd0

g2m

+K1

4kTg2m

·IaD

f+

415≈ 2

31gm

+K′1

g2m

·IaD

f+

415

• When the source impedance is large, i2i

dominates. Since Ig is very small, FETshave noise performance much superior to that of BJTs. However, for low source

impedances where v2i

dominates, BJTs often have noise performance superior tothat of FETs.



Neglecting flicker noise,

v2i

∆f= 4kT

(rb +

12gm

)i2i

∆f= 2q

(IB +

IC

|β(jω)|2

)= 2q

(IC

βF

+IC

|β(jω)|2

)

The noise factor is

F = 1 +v2i

4kTRS∆f+

i2i

4kT 1RS∆f

= 1 +1RS

(rb +

12gm

)+ RS

(gm

2βF

+gm

2|β(jω)|2

)

= 1 +1RS

(rb +

12gm

)+ RS

[gm

2βF

+gm

2β2o

(1 + β2

o

(ω

ωT

)2)]



For high-frequency circuits, if ω/ωT 1/βo and ω/ωT 1/βF ,

F ≈ 1 +1RS

·(rb +

12gm

)+ RS ·

gm

2·(ω

ωT

)2

• For fixed RS and ωT ,

gm,opt =1RS

·ωT

ωFopt = 1 +

rb

Rs

+ω

ωT

• For fixed gm and ωT ,

RS,opt =

√2rbgm

+1

g2m

·ωT

ωFopt = 1 +

√2rbgm + 1 · ω

ωT



For low-frequency circuits, if ω/ωT 1/βo and ω/ωT 1/βF ,

F ≈ 1 +1RS

·(rb +

12gm

)+ RS ·

gm

2·(

1βF

+1

β2o

)

≈ 1 +1RS

·(rb +

12gm

)+ RS ·

gm

2· 1βF

• For fixed RS and βF ,

gm,opt =1RS

·√βF Fopt = 1 +

rb

Rs

+1√βF

• For fixed gm and βF ,

RS,opt =

√2rbgm

+1

g2m

·√βF Fopt = 1 +

√2rbgm + 1 · 1√

βF


Noise Factor of an FET Common-Source Stage

Neglecting flicker noise, IG, and gate-current noise,

v2i

∆f= 4kTγgd0 ·

1

g2m

i2i

∆f= ω2C2

gs · 4kTγgd0 ·1

g2m

The noise factor is

F = 1 +v2i

4kTRS∆f+

i2i

4kT 1RS∆f

= 1 +1RS

·γgd0

g2m

+ RS ·ω2C2gs ·

γgd0

g2m


Noise Factor of an FET Common-Source Stage

For low-frequency circuits, ωCgs 1/RS ,

F ≈ 1 +1RS

·γgd0

g2m

• For fixed RS, gm,opt →∞ and Fopt → 1

• For fixed gm, RS,opt →∞ and Fopt → 1

• For RS of the order of MΩ or higher, the FET usually has significantly lower noisefigure than a BJT.

For high-frequency circuits, ωCgs 1/RS,

F ≈ 1 + RS ·ω2C2gs ·

γgd0

g2m

≈ 1 + RS · γgd0 ·(ω

ωT

)2



Common−Base Stage

Emitter Follower

zLzL

v2i

v2i

v2i

v2i

i2i

i2i

i2i

i2i



• The equivalent input noise generators of a common-base stage or emitter followerare the same as those of a common-emitter stage.

• For the common-base configuration, since its current gain ≈ 1, any noise current atthe output is referred directly back to the input without reduction.

• For the emitter follower, since its voltage gain ≈ 1, any noise voltage at the output,including noise due to zL, is transformed unchanged to the input.

• In most low-noise designs, common-emitter connection is used for the input stage.


Emitter-Coupled Pair Noise Performance

Q1 Q2

VCC

VEE

Q1 Q2

VCC

VEE

RL RL RL RL

vo vo

IEE IEEREE REE

v2i1 v2

i1v2i2 v2

i2

i2i1

i2i1i2

i2

i2i2

• If the circuit is balanced, the current-source noise represents a common-mode signaland will produce no differential output.


Effect of Ideal Feedback on Noise Performance

v1v1 vovo aa

f × vof × vo

v2i

v2i

i2i

i2i

• For ideal feedback systems, the equivalent input noise generators can be movedunchanged outside the feedback loop and the feedback has no effect on the circuitnoise performance.


Effect of Input Series Feedback Feedback on Noise Performance

v1v1 vovo aa

v2ia

i2ia

RFRFv2f

RERE

v2e

v2i

i2i

v2f= 4kTRF∆f v2

e = 4kTRE∆f R = RF ‖RE

vi = via + iiaR +RF ve

RF + RE

+REvf

RF + RE

ii ≈ iia

⇒ v2i= v2

ia+ i2

iaR2 + 4kTR∆f i2

i≈ i2

ia


Effect of Input Shunt Feedback Feedback on Noise Performance

v1v1 vovo aa

v2ia

i2ia

RFRF

i2f

v2i

i2i

i2f= 4kT

1RF

∆f

vi ≈ via ii = iia +via

RF

+ if

⇒ v2i≈ v2

iai2i= i2

ia+

v2ia

R2F

+ 4kT1RF

∆f


Effect of Feedback on Noise Performance

To analyze the noise performance of a practical feedback system, first use the loadingapproximation according to its feedback configuration to find the loading for the inputport due to the feedback network.

For series feedback at the input

v2i= v2

ia+ i2

ia|Zfb|2 + 4kTRfb∆f i2

i≈ i2

ia

For shunt feedback at the input

v2i≈ v2

iai2i= i2

ia+

v2ia

|Zfb|2+ 4kT

1Rfb

∆f

where Zfb is the loading of the feedback network for the input port, and Rfb representsthe resistive part (thermal noise) of the loading.


Effect of Cµ on Noise Performance

v1

v2b

i2b i2

crπ Cπ gmv1

Cµrb

ro

rc

Ccs

B B′

E

C

• Note that the collector-base capacitor Cµ represents single-stage shunt feedback, andthus does not significantly affect the equivalent input noise generators of a transistor,even if Miller effect is dominant. The capacitor itself contributes no noise. Also, in

calculating i2i, the term v2

ia/|Zfb|

2 can be neglected, since |Zfb| = 1/|ωCµ| is quitelarge at frequencies of interest.


Single-Stage Amplifier with Local Feedback

V o

iV

RFRFRF RF

i2f

i2f

RERERERE

v2e

v2i1

i2i1

v2i2

i2i2

v2i

i2i

v2i1

∆f≈ 4kT

(rb +

12gm

)v2i2

∆f≈ 4kT

(rb +

12gm

+ RE

)v2i

∆f≈ 4kT

(rb +

12gm

+ RE

)

i2i1

∆f≈ 2qIB

i2i2

∆f≈ 2qIB

i2i

∆f≈ 2qIB +

4kTRF


Operational Amplifier Noise Model

v2ia

i2ia+

i2ia−

• With FET input stage, the current noises can often be ignored at low frequenciessince their values are small.


A Low-Pass Filter Example

Rf

V o

R2

Cf

R1

Rf

R2

V i

Cf

R1V o

v2ia i2

ia+

i2ia−

i21

v22

i2f

v2o1 =

(i2a− + i2

1 + i2f

)∣∣∣∣ Rf

1 + j2πfRfCf

∣∣∣∣2

v2o2 =

(v2ia+ i2

a+R22 + v2

2

)∣∣∣∣∣1 +Rf/R1

1 + j2πfRfCf

∣∣∣∣∣2

v2oT

= v2o1 + v2

o2



20 k

Q2

Q1

5.5 k 5k || 500

20 kQ1

5 k

Q2

500is

io

io

i2f

v2ia

i2ia



• Neglect flicker noise and assume

IC1 = 0.5 mA IC2 = 1 mA rb1 = rb2 = 100 Ω β1 = β2 = 100

fT1 = 300 MHz fT2 = 500 MHz

• For both first and second stages, the driving signals are high-impedance currentsources, thus we need to consider only equivalent noise current generators.

• The equivalent noise current from the 2nd stage is approximately

2qIB2 + 4kT1

20 kΩ= 2q(10 µA + 2.6 µA)

which can be neglected when compared to 2qIC1 = 2q × 500 µA.



• The equivalent input noise current for the amplifier is

i2i

∆f=

i2ia

∆f+

v2ia

(5.5 kΩ)2∆f+

4kT5.5 kΩ

= 2q(IB +

IC

|β1|2

)+

4kT

(5.5 kΩ)2

(rb1 +

12gm1

)+

4kT5.5 kΩ

= 2q(

5 µA +500 µA

|β1|2

)+ 2q × 0.2 µA + 2q × 9.1 µA

= 2q(

14.3 +500

|β1|2

)× 10−6 A2/Hz

• We know that

β(j f ) =βo

1 + jβof

fT1

⇒ 1

|β1(j f )|2=

1

β2o1

(1 +

β2o1f

2

f 2T1

)



• The current gain of the amplifier is AI ≈ 11 and is constant up to B = 100 MHz =fT1/3. The total output noise is

i2oT

=∫ B0A2I

i2i

∆fd f = A2

I×∫ B0

2q(

14.3 +500

|β1|2

)× 10−6df

= A2I× 2q × 10−6

[14.3f +

500

β2o1

f +500

f 2T1

f3

3

]B0

= A2I× 2q × 10−6 × (14.3B + 18.6B) = A2

I× 1.05 × 10−15 A2

• The equivalent input noise current is

i2iT

=i2oT

A2I

⇒ iiT = 32.4 nA rms


Feedback and Frequency Compensation

Jieh-Tsorng Wu

December 5, 2002

A

1896


Feedback

a

f

Si So

Se

Sfb

So = a · Se Sfb = f · So Se = Si − Sfb

Closed-Loop Gain = A ≡So

Si=

a

1 + af=

a

1 + T≈ 1

fif T 1

Gain Sensitivity =δA

A=

11 + T

· δaa

Loop Gain = T ≡ a × f

Feedback 12-2 Analog ICs; Jieh-Tsorng Wu

Effect of Negative Feedback on Distortion

If a is a nonlinear amplifier

So = a1Se + a2S2e + a3S

3e + · · · T = a1f

• For constant input level, the harmonic distortions are

HD2 =1

(1 + T )2· HD2|T=0 HD3 =

1 − 2a22f

a3(1+T )

(1 + T )3· HD3|T=0

• For constant output level, the harmonic distortions are

HD2 =1

(1 + T )· HD2|T=0 HD3 =

1 − 2a22f

a3(1+T )

(1 + T )· HD3|T=0


Series-Shunt Feedback Configuration

Basic Amplifier

Feedback Network

vi

vovε

ii io

zi

zoa × vε

f × vo

T = a × fvo

vi=

a

1 + TZi = zi × (1 + T ) Zo =

zo

1 + T


Shunt-Shunt Feedback Configuration

Basic Amplifier

Feedback Network

vivo

iεii io

zi

zoa × iε

f × vo

T = a × fvo

ii=

a

1 + TZi =

zi

1 + TZo =

zo

1 + T


Shunt-Series Feedback Configuration

Basic Amplifier

Feedback Network

vi

vo

iεii io

zi zoa × iε

f × io

T = a × fio

ii=

a

1 + TZi =

zi

1 + TZo = zo × (1 + T )


Series-Series Feedback Configuration

Basic Amplifier

Feedback Network

vi vo

vε

ii io

zi zoa × iε

f × io

T = a × fio

vi=

a

1 + TZi = zi × (1 + T ) Zo = zo × (1 + T )



Topology Series-Shunt Series-Series Shunt-Series Shunt-Shunt

Sfb V V I ISo V I I VFor Li set vo = 0 io = 0 io = 0 vo = 0For Lo set ii = 0 ii = 0 vi = 0 vi = 0Source Thevenin Thevenin Norton Norton

Sfb = Feedback signal; So = Sampled SignalLi = Input loop loading; Lo = Output loop loading

Fundamental Assumptions:

1. The input signal is transmitted to the output through the amplifier a and not throughthe f feedback network.

2. The feedback signal is transmitted from the output to the input through the f block,and not through the amplifier.

3. The feedback factor f is independent of the load and the source impedances.



1. Identify the topology.

2. Draw the basic amplifier circuit without feedback using the loading approximationmethod.

3. Use a Thevenin’s source if Sfb is a voltage and a Norton’s source if Sfb is a current.

4. Indicate Sfb and So on the “open-loop” circuit. Evaluate f = Sfb/So.

5. Evaluate forward gain a = So/Si from the open-loop circuit.

6. Calculate closed-loop characteristics.


Loading Approximation Method

To find the input network:

1. Set vo = 0 for shunt sampling; i.e., short the output node.

2. Set io = 0 for series sampling; i.e., open the output loop.

To find the output network:

1. Set vi = 0 for shunt comparison; i.e., short the input node.

2. Set ii = 0 for series comparison; i.e., open the input loop.


Two-Port Analysis of a Shunt-Shunt Feedback Amplifier

vi

vi

vo

vo

io

vs

is

is =vsRS

RS

RS

RF

RFRF

RL

RLri

ro

Zi Zo if b = − voRF

−avvi

a =vo

is

∣∣∣∣if b=0

= (RS‖RF ‖ri)(−av)RF ‖RL

ro + (RF ‖RL)f =

if b

vo= − 1

RF

T = a × f ≈ av ×RS

RS + RF

vo

is

∣∣∣∣closed loop

=a

1 + af≈ 1

f≈ −RF ⇒

vo

vs≈ −

RF

RS

vi

is= Zi‖RS =

RS‖RF ‖ri1 + T

≈RF

av

vo

io= Zo‖RL =

RF ‖RL‖ro1 + T

≈ro

1 + T


Return Ratio

vivi vovo

vsRS

RSRF RF

RL

RLri

ro

−avvi vt

vr

Return Ratio = R ≡ −vr

vt=

vo

vt·vi

vo· −

vr

vi

=RL ‖ [RF + (RS ‖ ri)]

ro + RL ‖ [RF + (RS ‖ ri)]·

RS ‖ riRF + (RS ‖ ri)

· av

• The loop gain T = a · f in the two-port analysis is an approximation of R.



k

Rest of Circuit

ins ics ocs outsics rs

[sicsout

]=[B1 −Hd B2

][sinsoc

]soc = ksic R ≡ −

sr

soc= kH

B1 =sic

sin

∣∣∣∣soc=0

B2 =sout

soc

∣∣∣∣sin=0

H = −sic

soc

∣∣∣∣sin=0

d =sout

sin

∣∣∣∣soc=0



We have

A =sout

sin=

B1kB2

1 + kH+ d =

g

1 +R+ d g = B1kB2

A =g + d (1 +R)

1 +R=

( gR + d

)R

1 +R+

d

1 +R= A∞ ·

R1 +R

+ d · 11 +R

A∞ =g

R+ d

• d is the transfer function from the input to the output with k = 0.

• The value of A∞ can be found readily by letting k →∞ and sic is virtually “0”.

• Typically, A∞ is determined by a passive feedback network and is equal to 1/f fromtwo-port analysis.



The A∞R term can be rewritten as

A∞ · R =(gR

+ d)· R = B1kB2 + dR =

(B1 +

dH

B2

)· k · B2

=sic

sin

∣∣∣∣sout=0

× k ×sout

soc

∣∣∣∣sin=0


Blackman’s Impedance Formula

v

Port X

Rest of Circuit

ics ocsicsk rsxxi

[vxsic

]=[a1 a2

a3 a4

][ixsoc

]soc = ksic ⇒ ZX (k = 0) =

vx

ix

∣∣∣∣k=0

= a1

R(port X open) = −ka4 R(port X shorted) = −k(a4 −

a2a3

a1

)

ZX =vx

ix= a1 ·

1 − k(a4 −

a2a3a1

)1 − ka4

= ZX (k = 0) · 1 +R(port X shorted)

1 +R(port X open)



RF

ov

RCroti

riCRFR

vo

iin

bevgmrπ

bev

iin

VCC

R = −ir

it=

ro ‖ RC

ro ‖ RC + RF + rπ· rπ · gm

A∞ =vo

iin

∣∣∣∣gm=∞

= −RF d =vo

iin

∣∣∣∣gm=0

=rπ

rπ + RF + ro ‖ RC

· (ro ‖ RC)

sic

sin

∣∣∣∣sout=0

=vbe

iin

∣∣∣∣vo=0

= rπ ‖ RF

sout

soc

∣∣∣∣sin=0

=vo

ioc

∣∣∣∣iin=0

= −[ro ‖ RC ‖ (RF + rπ)]



The closed-loop gain is

A = A∞R

1 +R+

d

1 +R=

sic

sin

∣∣∣∣sout=0

· k ·sout

soc

∣∣∣∣sin=0

· 11 +R

+d

1 +R

The output resistance is

Ro = RX (k = 0) · 1 +R(port X shorted)

1 +R(port X open)= Ro(gm = 0) · 1 +R(output shorted)

1 +R(output open)

Ro(gm = 0) = ro ‖ RC ‖ (RF + rπ)

R(output shorted) = 0 R(output open) = R


Frequency Response of Feedback Amplifiers

a(s)

f

Si So

Sε

Sfb

A(s) =So

Si

=a(s)

1 + a(s) × f


Single-Pole Model

a(s) =ao

1 − s/p1

To = ao · f

A(s) =ao

1 + aof× 1

1 − s(1+aof )p1

=ao

1 + To× 1

1 − s(1+To)p1

p 1p 1(1 + To )

T o = 0 s-plane

σ

jω

For ω |p1|,

a(s) ≈ao

−s/p1

≈ωu

sA(s) ≈

ωu

f ·ωu + s=

1f× 1

1 + s/(fωu)

ωu ≡ ao × |p1| = Unity-Gain Frequency


Nyquist Diagram

T o

-1

Re

Im

T (jω)ω = 0

ω > 0

ω < 0

ω =∞

Nyquist diagram is the polar plot of a feedback amplifier’s loop gain T (jω) = af for−∞ < ω <∞.


Nyquist Criterion

• If the Nyquist plot encircles the point (−1,0), the amplifier is unstable.

• The number of encirclements of the point (−1,0) gives the number of right-half-planepoles.

s-plane

Nyquist Diagrampasses through (-1, 0)

Nyquist Diagramencircles (-1, 0)

σ

jω

• If |T (jω)| > 1 at the frequency where ∠T (jω) = −180, then the amplifier is unstable.


Phase Margin

1 p 2

T

p 3

o

p

90

180

270

1 / f

dB

Deg

T = 1

PhaseMargin

ωt logω

logω

|a(jω)|

∠a(jω)

The phase margin is defined as

PM = 180 + ∠T (jωt)

ωt is the frequency where |T (jωt)| = 1

• A typical lower allowable limit for thephase margin is 45, with a value of60 being more common.


Pseudo Dominant-Pole Model

a(s) =ao

(1 + s/ω1)(1 + s/ω2)

• ω1 = −p1 is the dominant pole frequency.

• If other poles and zero are on the real axis at much higher frequencies, then

1ω2≈

m∑i=2

1−pi

−m∑i=1

1−zi

• In practice, ω2 can be found from simulation. ω2 is the frequency at which

∠a(jω2) = −135


Phase Margin of the Pseudo Dominant-Pole Model

At frequencies ω ω1

a(s) ≈ao

(s/ω1)(1 + s/ω2)=

ωu

s(1 + s/ω2)ωu = ao ×ω1

The loop gain becomes

T (s) = a(s) · f =f ·ωu

s(1 + s/ω2)

Since ∠T (jω) = −90 − tan−1 (ω/ω2

)PM = 180 + ∠T (jωt) = 90 − tan−1

(ωt

ω2

)ωt

ω2= tan(90 − PM)

• ωt is the unity-gain frequency of T , i.e.,

|T (jωt)| = 1

• ωt is independent of the feedback factor f .


Closed-Loop Response of the Pseudo Dominant-Pole Model

Sincea(s) =

ao

(1 + s/ω1)(1 + s/ω2)The closed-loop gain is

A(s) =a(s)

1 + a(s) × f=

Ao

1 + s(1/ω1+1/ω2)1+aof

+ s2

(1+aof )(ω1ω2)

=Ao

1 + sωoQ

+ s2

ω2o

Ao =ao

1 + aofωo =

√(1 + aof )(ω1ω2) Q =

√(1 + aof )/(ω1ω2)

1/ω1 + 1/ω2

• If Q = 1/√

2 = 0.707, |A(jω)| has the widest passband without peaking. It −3 dBfrequency is ωo.

• If Q > 0.5, the percentage overshoot of the step response is

% overshoot = 100e−π/√

4Q2−1



If aof 1 and ω2 ω1, then

Ao ≈1f

ωo ≈√fωuω2 Q ≈

√f aoω1

ω2≈√fωu

ω2

Since |T (jωt)| = 1, we have

|T (jωt)| =∣∣∣∣∣ fωu

jωt(1 + jωt/ω2)

∣∣∣∣∣ = 1 ⇒ fωu

ωt

=

√1 +(ωt

ω2

)2

Q2 = fωu

ω2=

ωt

ω2

√1 +(ωt

ω2

)2

• For a given phase margin, ωt/ω2 is known. Then Q can be found using the aboveequation.



PM ωt/ω2 f (ωu/ω2) Q Overshoot

45 1.000 1.414 1.189 36.8%55 0.700 0.854 0.924 13.3%60 0.577 0.666 0.816 8.7%65 0.466 0.514 0.717 4.7%70 0.364 0.387 0.622 1.4%75 0.268 0.277 0.527 0.008%

• Define αt ≡ ωt/ω2 and αp ≡ f (ωu/ω2). Note that αt ≈ αp for PM > 65.

• Design with PM > 65 for no peaking in frequency response.

• Design with PM > 80 for no overshoot in step response.



gm1 m2g

1p’

Cc > 0

V ip 2

R1 C1 Cc

f

2 C1p

V o

R 2

s-plane

f = 0

σ

jω

The original poles of a(s) are

p1 =−1R1C1

p2 =−1R2C2

ωu = |Av(0)| · |p1| = gm1R1gm2R2 · |p1| =gm1

C1· gm2R2

By adding compensation capacitor Cc

p′1 =−1

R1(C1 + Cc)ω′u =

gm1

(C1 + Cc)· gm2R2



• The −3 dB bandwidth of the closed loop gain is approximately

f ·ω′u = αp · |p′2| ω−3dB ≈ ωt = αt · |p′2|

where αt and αp are determined by the required phase margin.

• Cc usually is quite large (typically > 1000 pF) and cannot be realized on a monolithicchip.

• For a general-purpose opamp where 0 < f ≤ 1, if the opamp is compensated forf = 1, it it guaranteed to be stable for all f , although it will be slower than necessary.



i

1vm1

c

2g gm2

v

C11 RR

Cc

2

f

V o

C2

p 2 p 1 1p’p’2

iV

s-plane

f = 0

σ

jω

Let f = 0, the nodal equations are

[G1 + s(C1 + Cc) −sCc

gm2 − sCc G2 + s(C2 + Cc)

][v1v2

]=[−gm1vi

0

]



The open-loop forward gain a(s) can be solved as

a(s) ≡v2

vi= a0 ×

1 − s/z′1

1 + b1s + b2s2= a0 ×

1 − s/z′1

D(s)

a0 = gm1gm2R1R2

z′1 = +gm2

Cc

b1 = R1(C1 + Cc) + R2(C2 + Cc) + gm2R1R2Cc b2 = R1R2(C1C2 + C1Cc + C2Cc)

Using dominant-pole approximation, i.e., |p′1| |p′2|,

p′1 ≈ −1b1

= − 1R1(C1 + Cc) + R2(C2 + Cc) + gm2R1R2Cc

p′2 ≈ −b1

b2= −

R1(C1 + Cc) + R2(C2 + Cc) + gm2R1R2Cc

R1R2(C1C2 + C1Cc + C2Cc)



Further, if gm2R2 1, R1 ∼ R2, and C1 ∼ C2 ∼ Cc, then

p′1 ≈ −1

gm2R1R2Cc

= −gm1

Cc

× 1a0

p′2 ≈ −gm2Cc

C1C2 + C1Cc + C2Cc

≈ −gm2

C1 + C2

The dominant-pole unity-gain frequency is

ω′u = |ao| × |p′1| =gm1

Cc

• Note that if Cc = 0

p1 = − 1R1C1

p2 = − 1R2C2

• Cc acts as a pole splitting capacitor that separate p1 and p2.



For a given phase margin, we have

f ·ω′u = αp · |p′2| ω−3dB ≈ ωt = αt · |p′2|

Thus|p′2|ω′u

=f

αp

=gm2

gm1×

Cc

C1 + C2

And Cc can be determined by

Cc =f

αp

×gm1

gm2× (C1 + C2)

• For compensation of a general-purpose opamp, let f = 1, then

ω′u = αp · |p′2| Cc =1αp

×gm1

gm2× (C1 + C2)


Feedforward Zero in Miller Compensation

90

180

dB

Deg

1 2p’ z’1 p’

logω

logω

|a|

∠a

• Because z′1 is in the right half-plane (RHP),

it will degrade the amplifier phase marginas it approaches f ·ω′u.

• z′1 is caused by the feedforward path of Cc.

ic = sCc(v2 − v1) = sCcv2 − sCcv1

• To avoid degrading of phase margin by z′1,

want

z′1 f ·ω′u ⇒z′1

ω′u≈

gm2

gm1 f

• Otherwise, additional circuitry must beadded to move z

′1.


Miller Compensation With Unity-Gain Buffer

Fbk

1v

ci

gm2

Mc

gm1v2

21 2R C

V

C

VSS

1

o

Cc

R

VDD

iV

Assume the voltage gain of theMc source follower is 1. Then

ic = sCc(v2 − v1)

−gm2v1 = v2(G2 + sC2)

a(s) =gm1gm2R1R2

1 + s[R1(C1 + Cc) + R2C2 + gm2R2R1Cc] + s2R1R2C2(C1 + Cc)

p1 ≈ −1

gm2R1R2Cc

p2 ≈ −gm2

C1 + C2


Miller Compensation With Common-Gate Stage

Fbki

2v1v

B

gm1

V

g

Mc

m2

c

R2 C2

V o

VDD

Cc

1C1R

iV

Assume the input impedance ofthe Mc common-gate stage is 0.Then

ic = sCc · v2

−gm2v1 = v2(G2 + sC2 + sCc)

a(s) =gm1gm2R1R2

1 + s[R1C1 + R2(C2 + Cc) + gm2R2R1Cc] + s2R1R2C1(C2 + Cc)

p1 ≈ −1

gm2R1R2Cc

p2 ≈ −gm2

C2 + Cc

·Cc

C1



1v 2vgm1 gm2

ZR

Fbk

C11 RR

V o

2 C2

C

i

c

V

a(s) = gm1gm2R1R2 ·1 − sCc

(1/gm2 − RZ

)1 + b1s + b2s

2 + b3s3

b1 = R2(C2 + Cc) + R1(C1 + Cc) + RZCc + gm2R1R2Cc

b2 = R1R2(C1C2 + CcC1 + CcC2) + RZCc(R1C1 + R2C2)

b3 = R1R2RZC1C2Cc



We have

z1 =1

(1/gm2 − RZ)Cc

p1 ≈ −1

gm2R2R1Cc

p2 ≈ −gm2

C1 + C2p3 ≈ −

1RZC1

• In most cases, p3 p1,2.

• Usually want z1 becomes negative and

|z1| ≈1

RZCc

= 1.2ωu ⇒ 1RZCc

= 1.2 ·gm1

Cc

⇒ RZ =1

1.2gm1


Miller Compensation with Feedforward Transconductor

gmf

gm1 m2v2

Fbk

1g

v

22 C

Cc

R

V i

1C1R

V o

a(s) =gm1R1gm2R2 + gmfR2 + sR1R2[gmf (C1 + Cc) − gm1Cc]

1 + s[R1(C1 + Cc) + R2(C2 + Cc) + gm2R1R2Cc] + s2[R1R2(C1C2 + C1Cc + C2Cc)]

To remove zero, let gmf = gm1 ·Cc

C1 + Cc

= gm1 ·1

1 + C1/Cc



2v1v

Fbk

gm3gm13

m2v

g

3 C3C RR2 C21

Cc2

1R

V o

C

i

c1

V

a(s) =N(s)

D(s)=

a0 + a1s + a2s2

1 + b1s + b2s2 + b3s

3

a0 = gm1gm2gm3R1R2R3

a1 = −(gm2R2Cc1 + Cc2)gm1R1R3

a2 = −gm1R1R2R3Cc2(C2 + Cc1)



b1 = K + R1(Cc2 + C1) + gm2R2gm3R3R1Cc2

b2 = R2R3(C3 + Cc1 + Cc2)(C2 + Cc1) − R2R3C2c1 + R1(Cc2 + C1)K

− gm2R2Cc1Cc2R1R3 − R1R3C2c2

b3 = R1R2R3[(C3Cc2 + C1C3 + C1Cc2)(C2 + Cc1) + C1Cc1Cc2 + C1C2Cc1]

K = R3(C3 + Cc1 + Cc2) + R2(C2 + Cc1) + R2Cc1gm3R3

The dominant pole is

p1 ≈ −1

R1Cc2(gm2R2gm3R3)

If Cc1 C1,2, then |p2| |p3|, and

p2 ≈ −gm2gm3

(gm3 − gm2)Cc1p3 ≈ −

(gm3 − gm2)Cc1

C2C3 + Cc1(C2 + C3)≈ −

gm3 − gm2

C2 + C3



• To ensure p2 and p3 are in the LHP, want gm3 > gm2.

• If |p1| |p2| |p3|,

p1 ∝1Cc2

p2 ∝1Cc1

p3 ≈ −gm3 − gm2

C2 + C3

The two-pole model can be used by making |p3| ωt.

• If Cc1 is not large enough, p2 and p3 are either complex conjugates or real but closelyspaced. Higher unity-gain bandwidth may be achievable when p2 and p3 are not realand widely separated.


Zeros in the Nested-Miller Compensation

The numerator of a(s) is

N(s) = gm1R1gm2R2gm3

[1 − s

(Cc1

gm3+

Cc2

gm2R2gm3

)− s2Cc2(C2 + Cc1)

gm2gm3

]

Assuming Cc1 C2 and Cc1 Cc2/(gm2R2), then

N(s) ≈ gm1R1gm2R2gm3

[1 − s

Cc1

gm3− s2 Cc2Cc1

gm2gm3

]

z1 = −gm2

2Cc2

1 +

√1 +

4gm3Cc2

gm2Cc1

z2 = −

gm2

2Cc2

1 −

√1 +

4gm3Cc2

gm2Cc1

• z1 is a LHP zero and z2 is a RHP zero. |z1| > |z2|

• |z1| and/or |z2| can be comparable to |p2|, thus degrading phase margin.


Nested-Miller Compensation with Feedforward Transconductors

mf2

Fbk

g

gm1v1

gm3

g

2vgm2

v3

mf1

C2R2

Cc1

1

c2C

3C

V oV i

C3R1R

a(s) = −R3(n0 + n1s + n2s

2)

1 + b′1s + b′2s2 + b′3s

3


Nested-Miller Compensation with Feedforward Transconductors

b′1 = b1 + gmf2R1R3Cc2

b′2 = b2 + gmf2R1R2R3(C2 + Cc1)Cc2

b′3 = b3

n0 = −gm1gm2gm3R1R2 − gmf1 − gm1gmf2R1

n1 = gm1(gm2 − gmf2)R1R2Cc1 + (gm1 − gmf1)R1Cc2

− gmf1R2(C2 + Cc1) − gmf1R1C1 − gm1gmf2R1R2C2

n2 = (gm1 − gmf1)R1R2(C2 + Cc1)Cc2 − gmf1R1R2(C2 + Cc1)C1

• To eliminate zeros, one can set n1 = n2 = 0.

• If gmf1 = gm1 and gmf2 = gm2, then n0, n1, and n2 are all negative, and both zeros arein the LHP.

• With gmf1 = gm1 and gmf2 = gm2, b1 ≈ a1 and the dominant pole p1 is not changedby gmf . However, p2 and p3 will be different from the case without gmf1 and gmf2.


Basic Two-Stage Operational Amplifier Design

Jieh-Tsorng Wu

December 23, 2002

A

1896



Single-Ended Output Fully Differential

i

oVi

Vi

Vo

V

Vi

Vi Vo

V

cm

ii

A/2 x V

A/2 x V

A x V

• Vo = A × Vi

• Ideal opamp:

– A→∞, Zin→∞, Zout → 0.– No frequency dependence.

Opamp-I 13-2 Analog ICs; Jieh-Tsorng Wu

Basic 2-Stage CMOS Opamp

Vi

Vi Cco

oV’oV

V’

iV

iV

Vo

VB1

Output

A 1 2

Buffer

Cc

A

Differential Input Stage

SecondGain Stage Output Buffer

Optional

1

VSS

VDD

M1 M2

M3 M4

M6

M7M5


Constant g m Bias Generator

B1V

oVci CV

Vi

VSS

VDD

VSS

M14

RB

M1 M2

M3 M4

M6

M7M5

M12

M13

M11

(W

L

)1=(W

L

)2(

W

L

)3=(W

L

)4(

W

L

)13

=(W

L

)14(

W

L

)12

= α ·(W

L

)11

gm =√

2µCox(W/L)ID gm11 =2RB

√α − 1√α

gm1,m2 = gm11 ·

√√√ (W/L)1

(W/L)11

√√√√12

(W/L)5

(W/L)11

gm3,m4 = gm11 ·

√µp

µn

√√√√ (W/L)3

(W/L)11

√√√√12

(W/L)5

(W/L)11

gm6 = gm11 ·

√µp

µn

√√√√ (W/L)6

(W/L)11

√√√ (W/L)7

(W/L)11


Input Stage Small-Signal Model

Vi

vy

gm4 vygm3 go3

go4Cy

B1

C1

vo1

io1

V

V

CR1vx

go5gm1 vi1 vx( ) vx( )gm2 vi2

i

o1v

go2go1

Cx

G

o1

m

o1

Vi

1

VSS

VDD

M1 M2

M3 M4

M5

gm1 = gm2 gm3 = gm4 go1 = go2 go3 = go4 gm go

Cy ≈ Cgs3 + Cgs4 = 2Cgs3


Input Stage Output Impedance

o2g

vy

gm4 vygm3 go3

go4Cy

g

t3

vt

o1

x

I

vi2

t1I t

vx

go5gm1 vi1 vx( ) vx( )gm2

I

C

i

t21

I vi1 = vi2 = 0 G1 = 1/R1 = vt/it

it = it1 + it2 + it3 it1 = vt · go4

f →∞it2 ≈ vt · go2 it3 ≈ i1 ≈ 0

G1 = go2 + go4

f → 0

it2 ≈ vt · go2/2 it3 ≈ i1 ≈ it2

G1 = go2 + go4

it2

vt=

go2(g′m1 + go5 + sC′x)

gm2 + gmb2 + go2 + g′m1 + go5 + sC′x

≈go2

2·

1 + sC′x/g

′m1

1 + sC′x/(2g′m1)

g′m1 = gm1 + gmb1 C′x = Cx + Cgs1 + Cgs2


Input Stage Di fferential-Mode Transconductance

y

vx

gm1 vi1 vx( ) vx( )gm2 vi2

g

y

go2go1

i

v

i

1i 2

vy

gm4 v

gC

m3 go3

o4

o1

i

o1

4

vid = vi2 − vi1 vi1 = −12vid vi1 = +

12vid

i1 = gm1vi1 = −12gm1vid

i2 = gm2vi2 = +12gm1vid

−i4i1

=gm4

gm3 + go1 + go3 + sCy

≈gm3

gm3 + sCy

io = −i4 − i2

Gmd (s) ≡io

vid= −1

2gm1

[1 +

gm3

gm3 + sCy

]= −gm1 ·

1 + sCy/(2gm3)

1 + sCy/gm3

= −gm1 ·1 − s/zm

1 − s/pm

zm = Mirror Zero = −2gm3

Cy

≈ −ωt3 pm = Mirror Pole = −gm3

Cy

≈ −ωt3

2


Input Stage Common-Mode Transconductance

i2v x

vy

gm4 vygm3 go3

go4Cy

vo1

io1

go2

2I1I

xC

o1vx

go5gm1 vi1 vx( ) v

I

( )gm2

4

g

vic = vi1 = vi2

i1 = i2(1 − εd )

−i4 = i1(1 − εm)

io1 = −i4 − i2 = i1(1 − εm) − i2

⇒ io1 = −i2(εd + εm − εdεm) ≈ −i2(εd + εm)

Gmc =io1

vic≈ −

i2

vic· (εd + εm)

i2

vic=

gm1

1 + 2(gm1+gmb1)(go5+sCx)

=gm1(go5 + sCx)

2(gm1 + gmb1) + go5 + sCx

≈go5 + sCx

2 + sCx/gm1

=go5

2·1 − s/zt

1 − s/pt

zt = Tail Zero = −go5

Cx

pt = Tail Pole = −2gm1

Cx



For the M1-M2 source-coupled pair,

i1 = gm1(vic − vx) + go1(vy − vx)

i2 = gm2(vic − vx) + go2(0 − vx) = gm1(vic − vx) − go1vx

vy = −i1

gm3 + go3 + sCy

We have

i1 = i2 + go1vy = i2 − i1 ·go1

gm3 + go3 + sCy

i1 = i21

1 + go1gm3+go3+sCy

≈ i2

(1 −

go1

gm3 + go3 + sCy

)= i2(1 − εd )

εd =go1

gm3 + go3 + sCy

≈go1

gm3 + sCy

=go1

gm3· 1

1 + sCy/gm3

=go1

gm3· 1

1 − s/pm



For the M3-M4 current mirror,

−i4

i1=

gm4

gm3 + go3 + sCy

=gm3

gm3 + go3 + sCy

= 1 −go3 + sCy

gm3 + go3 + sCy

= 1 − εm

εm =go3 + sCy

gm3 + go3 + sCy

≈go3 + sCy

gm3 + sCy

=go3

gm3·

1 + sCy/go3

1 + sCy/gm3

=go3

gm3·1 + sCy/go3

1 − s/pm

The common-mode transconductance is

Gmc(s) ≈ −i2

vic· (εd + εm)

≈ −go5

2·1 − s/zt

1 − s/pt

·(

go1

gm3· 1

1 − s/pm

+go3

gm3·1 + sCy/go3

1 − s/pm

)

= −go5(go1 + go3)

2gm3·

(1 − s/zt)(1 − s/zc)

(1 − s/pt)(1 − s/pm)zc = −

go1 + go3

Cy


Input Stage Voltage Gain

A dm

A cm

zt

CMRR

ω

ω

ωptzmpmzcpo

Adm = Gdm · Z1 Acm = Gcm · Z1

Z1 =1

G1 + sC1=

1go2 + go4

· 1

1 − s/po

po = Output Load Pole = −go2 + go4

C1

CMRR =

∣∣∣∣Gmd

Gmc

∣∣∣∣=

2gm1gm3

go5(go1 + go3)·(1 − s/zm)(1 − s/pt)

(1 − s/zt)(1 − s/zc)

CMRR(∞) =gm1/2

gm1=

12


Simplified Two-Stage Model

gm1vi gm6v1R1 C1 R2 C2

v1 vo

Cc

G1 = go2 + go4 G2 = go6 + go7 C1 Cgs6

Av ≡vo

vi= Av(0)

1 − s/z1

(1 − s/p1)(1 − s/p2)

Av(0) = gm1gm6R1R2

p1 ≈ −gm1

Cc

× 1Av(0)

p2 ≈ −gm6

C1 + C2z1 = +

gm6

Cc


Frequency Compensation Using Nulling Resistor

M16 M15M10

Voc

Vi

Vi

V

B2V

C

B1

VSS

VDD

VSS

M14

RB

M1 M2

M3 M4

M5M12

M13

M11

M6

M7


Frequency Compensation Using Zero-Nulling Resistor

• The zero-nulling resistor Rc is realized by M10 in the triode region.

z1 =1

(1/gm6 − Rc)Cc

= −gm6

(gm6Rc − 1)Cc

• Let (W/L)13

(W/L)14= (W/L)15

(W/L)16and (W/L)7

(W/L)11= (W/L)6

(W/L)13, then

Vov6 = Vov13 = Vov14 Vov10 = Vov15 = Vov16

Vov6

Vov10=

Vov13

Vov15=

√√√√(W/L)15

(W/L)13

gm6Rc =gm6

gm10=

(W/L)6

(W/L)10

Vov6

Vov10=

(W/L)6

(W/L)10

√√√√(W/L)15

(W/L)13

• p2/z1 ≈ (gm6Rc − 1)Cc/(C1 + C2) is independent of process and temperaturevariations.


Voltage and Current Range

Input Common-Mode Range

Vic(max) = VDD − VGS3 + Vt1 Vic(min) = VSS + VDSAT5 + VGS1

• The range is limited to the voltage levels where any transistor goes out of saturation.

Output Voltage Range

Vo(max) = VDD − VDSAT6 Vo(min) = VSS + VDSAT7

• Output resistive load can also limit the voltage range, if the available output current isinsufficient.

Maximum Output Current

Io(sink,max) = ID7 Io(source,max) =12k′p

(W

L

)6

[Vgs6(max) − Vt6]2 − ID7

Vgs6(max) = VDD − Vi+ + Vt2


Slew Rate

B1V

Vi cI

oV

x

SR

C oVi

ISS

I

VDD

VSS

C2

int

SR ext

Log (C )

i

V o

V o

V i

SR

V

2

M1 M2

M3 M4

M6

M7

Log (SR)Exponential

t

t


Slew Rate

The internal slew rate is generally limited by current available to charge and dischargeCc from input stage. Therefore,

SRint =dVo

dt

∣∣∣∣max

=Ix(max)

Cc

=ISS

Cc

=ISS

gm1×gm1

Cc

=ISS

gm1×ωu

= (VGS1 − Vt1) ×ωu

= Vov1 ×ωu

The external slew rate is limited by the available current to charge and discharge C2.Thus,

SRext =ID7 − Ix(max)

C2=

ID7 − ISS

C2


Settling Time

The frequency response and step response of a single-pole amplifier is

A(s) =Ao

1 + s/ωp

Vo(t) = Ao

(1 − e−ωpt

)

The settling time can be written as

ts(ε) =1ωp

ln1ε=

Ao

ωu

ln1ε

• ωu = Ao ·ωp is the dominant-pole unity-gain frequency.

• ε = 1 − |Vo(ts)/Ao| is the error when settling occurs.

The 10% to 90% rise time is

tr =1ωp

ln(9) =2.2ωp

=0.35fp

ωp = 2πfp


Input Impedance

C

C

Vi

C

V

oV

iVVB1

C

in-

o

C

VoVi c

in+

d

C

VDD

VSS

Cgd2

Ct

cC

M1 M2

M3 M4

M5

M6

M7M6

R1

R2

M2g m2


Input Impedance

Shorting the noninverting input to ground,

Cin− = Cd + C− ≈Cgs1

2

Shorting the inverting input to ground,

Cin+ = Cd + C+ ≈Cgs1

2+ Cgd2 · (1 + Ao1) Ao1 = gm2R1

And we have

Cd ≈Cgs2

2C− ≈ 0 C+ ≈ Cgd2 · (1 + Ao1)


Input Impedance

The equivalent voltage gain of the M2 stage decreases with increasing frequency, duethe the effect of Ct. The capacitance C+ is then modified as

C+ ≈ Cgd2 · Ao1 ·1 +

Cgd2gm2

s

1 + Ao1Cgd2+Ct

gm2s

whereCt = Cgs6 + Cc · (1 + Ao2) = Cgs6 + Cc · (1 + gm6R2)

• For gm2/[Ao1(Cgd2 + Ct)] < ω < gm2/Cgd2, C+ become resistive, and

C+ → R+ ≈1

gm2·(

1 +Ct

Cgd2

)


Output Impedance

m6Z o

1/g

Log |Zo|

Log fwith unity-gain feedback

gm6v1R1 C1 R2

R2

v1

Cc

|p1| |p2||z1| ωu

Assuming gm6 R1 and R2, we have

Zo = R2 ·1 + sR1(Cc + C1)

1 + sgm6R1R2Cc + s2R1C1R2Cc

p1 ≈ −1

gm6R1R2Cc

= −gm1

Cc

· 1

|Av(0)|p2 ≈ −

gm6

C1z1 ≈ −

1R1(Cc + C1)


Output Impedance

• For frequencies larger than z1, Cc acts as a short, the Zo is a resistive 1/gm6.

• The closed-loop Zo of the unity-gain buffer is

Zoc ≈Zo

Av

≈R2

Av(0)· (1 − s/z1) for ω < ωu

where ωu = gm1/Cc.


Systematic Input O ffset Voltage

V

Vi

V

c

I

YV1

OS

VB1

SS

iVVo

C

VDD

VSS

M1 M2

M3 M4

M6

M7M5

ID =12kV 2

ov (1 + λVDS)

λ1 = λ2 λ3 = λ4

∆I1−2 = ID1 − ID2 =ISS

2λ1(VY − V1)

∆I3−4 = |ID3| − |ID4| =ISS

2λ3(V1 − VY )

The systematic input referred dc offset can be expressed as

−VOS,s =1

gm1· (∆I1−2 − ∆I3−4) =

Vov,1−2

2· (λ1 + λ3)(VY − V1)


Systematic Input O ffset Voltage

• The systematic offset is caused by asymmetry in the dc biasing of VY and V1.

• To minimize VOS,s, want VDS3 = VDS4 = VGS6, then

(W/L)3

(W/L)6

=(W/L)4

(W/L)6

=(W/L)5

2(W/L)7

• Further, to minimize process induced variations choose

L3 = L4 = L6

However, this constraint may conflict with frequency response and noise constraints.


Random Input O ffset Voltage

∆Vi−j = |Vi | − |Vj | Vi−j =|Vi | + |Vj |

2∆Ii−j = |Ii | − |Ij | Ii−j =

|Ii | + |Ij |2

∆

(W

L

)i−j

=(W

L

)i

−(W

L

)j

(W

L

)i−j

=12

[(W

L

)i

+(W

L

)j

]

⇒∆ID,3−4

ID,3−4=

∆(W/L)3−4

(W/L)3−4

− 2∆Vt,3−4

Vov,3−4=

∆ID,1−2

ID,1−2

−VOS,r = ∆Vt,1−2 +Vov,1−2

2

[∆ID,1−2

ID,1−2−∆(W/L)1−2

(W/L)1−2

]

= ∆Vt,1−2 −Vov,1−2

Vov,3−4· ∆Vt,3−4 +

Vov,1−2

2

[−∆(W/L)1−2

(W/L)1−2

+∆(W/L)3−4

(W/L)3−4

]

= ∆Vt,1−2 −gm3

gm1· ∆Vt,3−4 +

Vov,1−2

2

[−∆(W/L)1−2

(W/L)1−2

+∆(W/L)3−4

(W/L)3−4

]


Input O ffset Voltage and Common-Mode Rejection Ratio

The output voltage change due to common-mode input variation is

∆Vo = Acm · ∆Vic

Want to change differential input so that ∆Vo = 0, then

∆Vid = −∆Vo

Adm

= −Acm

Adm

· ∆Vic

Therefore, we have

CMRR ≡∣∣∣∣Adm

Acm

∣∣∣∣ =∣∣∣∣∣∣(

∂Vid

∂Vic

∣∣∣∣∆Vo=0

)−1∣∣∣∣∣∣ =∣∣∣∣∣(∂VOS

∂Vic

)−1∣∣∣∣∣


CMRR Due to Systematic and Random O ffset

SinceVOS = VOS,s + VOS,r

We have

1CMRR

=

∣∣∣∣∂VOS,s∂Vic+∂VOS,r

∂Vic

∣∣∣∣∂VOS,s

∂Vic=

∂VOS,s

∂Vov1·∂Vov1

∂Id1·∂Id1

∂Vic= −1

2(λ1 + λ3)(VY − V1) · 1

gm1·

gm1

1 + 2(gm1 + gmb1)ro5

= −12

(λ1 + λ3)(VY − V1) · 11 + 2(gm1 + gmb1)ro5

≈ −(λ1 + λ3)(VY − V1)

4(gm1 + gmb1)ro5

∂VOS,r

∂Vic=

∂VOS,r

∂Vov1·∂Vov1

∂Id1·∂Id1

∂Vic= −1

2

[−∆(W/L)1−2

(W/L)1−2

+∆(W/L)3−4

(W/L)3−4

]· 11 + 2(gm1 + gmb1)ro5

= −[−∆(W/L)1−2

(W/L)1−2

+∆(W/L)3−4

(W/L)3−4

]· 14(gm1 + gmb1)ro5


Mismatches and Input Stage Transconductance

Define

∆gm,i−j = gm,i − gm,j gm,i−j =gm,i + gm,j

2∆ro,i−j = ro,i − ro,j ro,i−j =

ro,i + ro,j

2

Then

Gmd ≈ gm,1−2 ·1 −(∆gm,1−22gm,1−2

)2

1 +(∆gm,3−42gm,3−4

) Gmc ≈ −gm,1−2

1 + 2gm,1−2ro5· (εd + εm)

where

εd ≈1

gm3ro1−∆gm,1−2

gm,1−2

(1 +

2ro5

ro1

)−

2ro5

ro1·∆ro,1−2

ro,1−2

εm =1

1 + gm3ro3+

(gm3 − gm4)ro3

1 + gm3ro3≈ 1

gm3ro3+∆gm,3−4

gm,3−4


Power Supply Rejection Ratio (PSRR)

oV

v

ddv

B1

C

V

ss

cvid

VDD

VSS

VDD

VSS

M1 M2

M3 M4

M6

M7M5

vo = −Avvid + Addvdd + Assvss

PSRRDD ≡Av

Add

PSRRSS ≡Av

Ass

Av =Av(0)

1 − s/p1

Av(0) = gm1gm6R1R2

Av(0)p1 = −gm1

Cc

Av ≈gm1

sCc

for ω |p1|


Power Supply Rejection Ratio (PSRR SS)

vo

r x C

x

x

Cc

VDD

VSS

vss1 ss2

Z 6

VSS

v

M1 M2

M3 M4

r C7o7

M6vo

vss1= Av,cm =

Av

CMRR

Z6 ≈1

gm6

Z7 =1

go7 + sC7

vo

vss2=

Z6

Z6 + Z7≈

Z6

Z7≈

go7 + sC7

gm6

1PSRRSS

=vo/vss1 + vo/vss2

Av

=1

CMRR+

(1 + sro7C7)(1 − s/p1)

gm6ro7Av(0)≈ 1

CMRR


Power Supply Rejection Ratio (PSRR DD)

B1V

Cc

VSS

1

xov

y

v

v

y0C

1

g m3

c

g m6 (vdd1 1- v

y

vdd1R1d C1d

v1

g m6

C

vo

R2

y

g m4 (v - v

oC

Cc

v

R2

)

R2

voR1

vdd2

vdd1

Ry0

vdd2 vdd1y )dd2

M1 M2

M4

M5

vy

M3

M6

M7


Power Supply Rejection Ratio (PSRR DD)

The voltage gain from vdd1 to vo is

vo

vdd1=

1

1 + 1+(g1d+sC1d )/(sCc)R2(g1d+sC1d )+gm6R2

≈ 1

1 + C1d/Cc

gm6R2

≈ 1

For vdd2 input, since gm3 + sCy Gy0 + sCy0, the resulting current flow in M3 isapproximately

iy0 ≈ vdd2 · (gy0 + sCy0)

The current is mirrored in M4, and amplified by M6 and Cc. The voltage gain is

vo

vdd2= iy0 · Av2 ≈ −

gy0 + sCy0

sCc

⇒vo

vdd2

vo

vdd1

Thus

PSRRDD ≈Av

vo/vdd1

≈ Av


PSRRDD with Common-Gate Miller Compensation

M3

M2

y 1

x

v1

voCc

vdd1

R1d C1d

vo

R2

v1

Cp

vdd1

Cc

g m6 (vdd1 1− v )

g m6

R2

Cc

vdd1

Cp

vo

Bias

vy

VSS

M6

M10

M7M5

M4

M1M10

M10

Assume the M10 stage has Rin = 1/gm10 and AI = 1. Neglecting R1d and C1d , we have

vo

vdd1=

1

11+sCc/gm10

·(Cc

Cp+ sCc

gm6

)+ 1

gm6R2

≈Cp

Cc

·(

1 + sCc

gm10

)


Supply Capacitance

CI

Vo

CI

CsupVn

cxV

yV

oVC

gd1

VB1

Id5gs1C

C

VDD

VSS

M1 M2

M3 M4

M5

M6

M7Vo = −Csup

CI· Vn

• Both Cgs1 and Cgd1 can function as Csup, and noises at Vx and Vy can leak to theoutput.


Power-Supply Rejection and Supply Capacitance

• The VDD noise can be coupled to Vy through the diode-connected M3 device. The useof cascode input stage can overcome this problem.

• If Id5 is modulated by the supply voltage variation, then vx ≈ id5/(2gm1). The use ofsupply-independent bias reference can overcome this problem.

• The noises at the substrate/well terminals of M1 and M2 can change the Vt of thedevices due to body effect, and cause Vgs variation, introducing noises at Vx. Asolution is to place both M1 and M2 in a single well, and connect well and sourceterminals together to eliminate body effect.

• Interconnect crossovers can introduce undesired coupling capacitors to the Vi−summing node. Careful layout is required.

• Fully-differential circuit topology generally has better power-supply rejectionperformance.


Device Noise Analysis

I SS

V DS3

vnT

I SS

V DS3

vn1 vn2

vn4vn3

I oI o

M1

M3

M2

M4

VDD

VSS

M1

M3

M2

M4

VDD

VSS

v2n ≈ 4kT

(23· 1gm

)+

Kf

W LCox

· 1f

i2n ≈ 0

v2nT

= v2n1 + v2

n2 +(gm3

gm1

)2(v2n3 + v2

n4

)


Thermal Noise Performance

Assuming M1=M2 and M3=M4, and knowing ID1 = ID3 so that

(gm3

gm1

)2

=µpCox(W/L)3

µnCox(W/L)1

=µp(W/L)3

µn(W/L)1

k′n = µnCox k′p = µpCox

The input referred thermal noise is

v2(Θ)T

∆f= 4kT

(43

1gm1

)+(gm3

gm1

)2

× 4kT(

43

1gm3

)= 4kT

(43

1gm1

)×[

1 +gm3

gm1

]

= 4kT

4

3· 1√

2k′n(W/L)1ID1

×

1 +

√√√√µp

µn

·(W/L)3

(W/L)1

• The load contribution can be made small by making gm1 > gm3 or (W/L)1 > (W/L)3.

• gm1 should be made as large as possible to minimize thermal noise contribution.


Flicker Noise Performance

The input referred 1/f noise is

v2(1/f )T

∆f=

2Kfn

W1L1Coxf+(gm3

gm1

)2

×2Kfp

W3L3Coxf=

2Kfn

W1L1Coxf+µp(W/L)3

µn(W/L)1

×2Kfp

W3L3Coxf

=1f×

2Kfn

W1L1Cox

(1 +

Kfp

Kfn

·µp

µn

·L

21

L23

)

• Kfp is typically smaller than Kfn by a factor of two or more.

• The load contribution can be made small by making L3 > L1. But longer L3 can limitsthe signal swing somewhat.

• The width of load devices does not affect the 1/f noise performance. But make itwider can maximize signal swing.

• Making W1 wider can reduce 1/f noise.



oV

Vi

B1

o

Vi

V

V’

VDD

Cc Buffer

VSS

Output

M1 M2

M3 M4

M5

M6

M7



Comparing to the nMOST-input opamps, the pMOST-input opamps have

• Similar dc voltage gain.

• Smaller gm1 and larger gm6.

• Larger unity-gain frequency since ωu |p2| and |p2| = gm6/C2.

• Better slew rate since both Vov1 and ωu are larger.

• Better 1/f noise performance.

• Poorer thermal noise performance.


Operational Amplifiers with Single-Ended Outputs

Jieh-Tsorng Wu

December 23, 2002

A

1896


Two-Stage Operational Amplifier with Cascode

o

Vi

Vi

I

B1V

B1

cCV

VDD

VSS

M7

VDD

M3

M3A

M1 M2

M6

M5

M2AM1A

M4A

M4

M8

M10

M9

• The volage gain Av ∝ (gmro)3.

• Size M8 so that

VDS1 = VDS2 VDSAT

• Input common-mode range isreduced by cascodes.

• The additional poles are non-dominant and located near ωT .

• The 2nd stage can also usecascodes.

Opamp-II 14-2 Analog ICs; Jieh-Tsorng Wu

Telescopic-Cascode Operational Amplifier

Vi

Vi

IB1

VB1

CL

Vo

VB2

VDD

VDD

VSS

M3

M1 M2

M2AM1A

M4

M8

M5

M4AM3A

• The volage gain Av ∝ (gmro)2.

• Consider the output current branch,

VDD − (VIC − Vt) > ∆Vo + 3Vov

⇒ VDD − VIC > ∆Vo + 3Vov − Vt

Since VIC,min = Vt + 2Vov + VSS , we have

VDD − VSS > ∆Vo + 5Vov

• Consider the non-output branch,

VDD − (VIC − Vt) > Vt + 2Vov

⇒ VDD − VIC > 2Vov or VDD − VSS > Vt + 4Vov



VDD

V bsp

V ccp

VSS

V ccn

V o

CL

V i+

V i-

I 1

M2M1

M3M4

M5M6

M7M8

M9M10



• Consider output stage

VDD − VSS > ∆Vo + 4Vov or VDD − VSS > Vt + 3Vov

Consider input stage

VIC,max = VDD − Vov + Vt VIC,min = VSS + Vt + Vov + Vo,min(I1)

• The differential-mode voltage gain is

Av =Av(0)

1 − s/p1

Av(0) = gm1Ro p1 = − 1RoCL

Ro =1

go2+go9gm3ro3

+ go7gm5ro5

At midband frequencies where ω |p1|

Av ≈Av(0)

−s/p1

=gm1

sCL

=ωu

sωu =

gm1

CL



• The dominant poile is associated with the only high-impedance node at Vo. All otherpoles are located near ωT , and their magnitude are normally larger than |p2| of thetwo-stage opamps.

• CL provides the dominant-pole frequency compensation. Increasing CL improves thephase margin.

• If lead compensation is desired, a resistor can be placed in series with CL.

• Use nMOST input stage for larger gm1 and better thermal noise performance.

• Good PSRR since no pole-splitting Cc.

• Slightly higher noise due to more devices.

• Suitable for low-voltage operation.

• Active cascodes can be used to increase voltage gain.



VDD

V ccp

VSS

V ccn

V o

CL

V i+

V i-

I 1

V bsp

M2M1

M3M4

M5M6

M7M8

M9M10M11 M12



If bias currents ID1,D2 > ID3,D4, i.e., I1 > ID9,D10,

• Without M11 and M12, the slew rate is

SR =ID9

CL

=ID10

CL

• During slew condition, M11 and M12 can be used to clamp the drain volage of M1and M2 to reduce bias recovery time, and increase ID9 and ID10 to improve SR.

If bias currents ID1,D2 < ID3,D4, i.e., I1 < ID9,D10,

• This slew rate is

SR =I1

CL

I1 = ID1 + ID2

• M11 and M12 are not required.



V ccp

VDD

V ccn

V o

CL

V i+

V i-

I 1

VSS

M2M1

M3 M4 M5M6

M9M10 M11M12

M7 M8

M13M14



(W

L

)3=(W

L

)4=(W

L

)6=

1K

(W

L

)5

(W

L

)7=

1K

(W

L

)8

ID1,D2 = ID3,D4 = ID6 = ID7 =1KID5 =

1KID8 =

12I1 SR =

K I1

CL

Av(0) = Kgm1Ro Ro =1

go5gm11ro11

+ go8gm14ro14

p1 = − 1RoCL

ωu =Kgm1

CL

• For a given power dissipation, the current-mirror opamps have larger bandwidth andSR than the folded-cascode opamps. But they also suffer from larger thermal noise.

• For small CL, K may have to be reduced to prevent the nondominant poles fromdegrading the phase margin.

• A practical upper limit on K is around 5. For a general-purpose opamp, K 2.



I

o,p1I

o,n2I

o,n1I

o,p2

V i-

i+ V i-

V i+

V

i-V i+

I

I 2n

I 2p

I 1n

I n

I pV

1p

VDD

VSS

M1 M2

M3 M4



• Total input stage transconductance is

Gm = gm1 + gm3

• Gm variation due to Vic change can degrade CMRR. Want

gm1 + gm3 =√µnCox(W/L)1In +

√µpCox(W/L)3Ip = Constant

If µnCox(W/L)1 = µpCox(W/L)3, want

√In +

√Ip =

√I1n − I2p +

√I1p − I2n = Constant



• LetI1n = I1p = 4I I2n = I2p = 3I

At Vic (VDD − VSS)/2 √In +

√Ip =

√1I +

√1I = 2

√I

At Vic VSS , In = 0 and I2n = 0,

√In +

√Ip =

√0I +

√4I = 2

√I

At Vic VDD, Ip = 0 and I2p = 0,

√In +

√Ip =

√4I +

√0I = 2

√I

• Less than 5% change in Gm is possible.

• The variation of the input-referred dc offset VOS due to Vic change also degradeCMRR.



V i-V i+V bon

V bop

V ccp

V ccn

VDD

VSS

Cc

Cc

V o

CL

M1 M2

M3 M4

I p

I n M16

M11 M12

M13M14

M15

M17M18

M23

M24

M25

M26

M21

M22



• Two cascaded gain stages.

• Noises in Vbop and Vbon are canceled at output.

• The bias of the output stage is insensitive to variations in Ip, In and supply voltage.

• The two Cc are connected as Miller frequency compensation using common-gatestages.

• The output pole is

p2 =Cc

Cgso

×gmo

CL

where gmo and Cgso are respectively the total gm and Cgs of the output stage.

• Reference: Hogervorst, et al., JSSC 12/94, pp. 1505–1513.


Low-Voltage Multi-Stage OpampVDD

VSS

V o

V i+ V i-

Bias

M2M1

M3M4

M5 M6M7

M8

M9

M10

C3

C2a C2b

C1b

C1a

M11

M12


Low-Voltage Multi-Stage Opamp

• Four cascaded gain stages.

• Hybrid nested Miller compensation.

• Class-AB output stage.

• A supply voltage below 1.5 V is possible.

• Reference: Eschauzier, et al., JSSC 12/94, pp. 1497–1504.



RL

V i

Z iI x

I oV o

V i

RL

V o

R2

R1

Current-Feedback Opamp

R2

R1

V x

Voltage-Feedback Opamp

For the voltage-feedback opamp, let Vo/Vx = A ≈ ωu/s and Zi →∞, then

Av =Vo

Vi= −

R2

R1· 1

1 + 1A

(1 + R2

R1

) ≈ −R2

R1· 1

1 + sωu

(1 + R2

R1

)

• Trade-off between closed-loop gain and closed-loop bandwidth.



For the current-feedback opamp, let Io/Ix = A ≈ ωu/s, then

Av =Vo

Vi= −

R2

R1·

1 − Zi

AR2

1 + 1A

[1 + R1R2+Zi (R1+R2+RL)

R1RL

] ≈ −R2

R1· 1

1 + sωu

[1 +

R2+Zi

(1+

R2+RLR1

)RL

]

If Zi → 0,

Av ≈ −R2

R1· 1

1 + sωu

(R2RL

)

• The closed-loop gain can be modified by changing R1, leaving the closed-loopbandwidth unchanged.

• For a given R2, frequency compensation can be optimized. Suitable for high-frequency applications.



V bon

V bop

V ccp

V ccn

V icm

V o

V o

VDD

VSS

V i

M21

M22

2I

2I

M4

I

I

LR

R2

R1

M2

M3M23

M24

M11

M12

M1



• This opamp has been designed to drive RL = 25 Ω and provide 50 mA of outputcurrent.

• Two-stage opamp with only one high-impedance node.

• Cgs and Cgd of M21 and M22 are large enough to provide adequate frequencycompensation.

• The class-AB common-gate input stage provides large internal slew rate.

• Large voltage swing of Vgs21 and Vgs22 are required.

• Open-loop current gain is determined by the output stage,

A(s) ≈gmo

sCgo

=ωu

sωu =

gmo

Cgo

• Loop gain T (s) ≈ A(s)RL/(RL + R2) is independent of R1.


A General-Purpose BJT Current-Feedback Opamps

V nV i

VCC

VEE

I B

I B

Ro Cc

V o

I f

I f

Q1

Q2

1:1

1:1

R2

R1

BufferOutput

1Q3

Q4


A General-Purpose BJT Current-Feedback Opamps

Due to the symmetry of the input stage, we have Vi = Vn.

If R1 ‖ R2 1/(gm1 + gm2), we have

If =Vo − Vn

R2−

Vn

R1= Vo

(1R2

)− Vi

(1R1

+1R2

)Vo = −If

(1

sCc + 1/Ro

)

Av =Vo

Vi=[Ro(R1 + R2)

(Ro + R2)R1

][1

1 + sCc(Ro‖R2)

]

If Ro R2,

Av ≈(

1 +R2

R1

)(1

1 + sCcR2

)Also the loop gain is

T (s) =

(1

sCc + 1/Ro

)(1R2

)≈ 1

sCcR2



Jieh-Tsorng Wu

July 16, 2002

A

1896



o1Vx1

Vx2V

Vi2

Vo2

V

i1

[vodvoc

]=[Adm Acdm

Adcm Acm

][vidvic

]Vid = Vi1 − Vi2 Vic = (Vi1 + Vi2)/2

Vod = Vo1 − Vo2 Voc = (Vo1 + Vo2)/2

• In practice, wantAdm 1 Acm 1

• If the circuit is fully symmetrical,

Acdm = 0 Adcm = 0

Opamp-III 15-2 Analog ICs; Jieh-Tsorng Wu


• Signal is carried in Vxd = Vx1 − Vx2. Let

Vx1 = A sinωt + n1 Vx2 = −A sinωt + n2 Vxd = 2A sinωt + n1 − n2

Assuming n1 and n2 are uncorrelated, then

SNRx1 = SNRx2 =A

2/2

n2⇒ SNRxd =

2A2

n21 + n2

2

=2A2

2n2= 2SNRx1

• Immune to common-mode noise, such as noises from power supplies and substrate.

• No even-order harmonic distortion in Vxd .

• Require additional common-mode feedback circuitry to set Vxc = (Vx1 + Vx2)/2.


Small-Signal Models for Differential Loading

i

i1

i2

v1

v2

2

2

cZ

cZ

dZ (-2Z )c

-Network Model

Z

v

cZ

icd

2vc

2

CM Half CircuitDM Half Circuit

2dZ

2dZ

cZ

2 4dZ

i1

iv1

v

π

2d

T-Network Model

d

vd = v1 − v2 vc = (v1 − v2)/2 id = (i1 − i2)/2 ic = (i1 + i2)/2

Zd =vd

id

∣∣∣∣vc=0

Zc =vc

ic

∣∣∣∣vd=0


Small-Signal Models for Differential Signal Sources

Zod2

2

Z

CM Half CircuitDM Half CircuitNorton-Network ModelThevenin-Network Model

i1v1

od

v2i2

i

Zod2

vod2

vod2

odZZoc2 4

voc

od

iod

v1

v2

i1

i2

ocZod (-2Z )

i

c

ocZ

ioc Z

Z

ocZ

ioc

oc

2

id

oc

oc

vod2

Zod2

vd2

2

id

vd

2

cvc

icv

oc

v

i

vod = Admvid voc = Acmvic iod = Gmdvid ioc = Gmcvic

Adm =vod

vid

∣∣∣∣iod=0

Acm =voc

vic

∣∣∣∣ioc=0

Gmd =iod

vid

∣∣∣∣vod=0

Gmc =ioc

vic

∣∣∣∣voc=0


Common-Mode Feedback (CMFB)

Voc

Vod2 CM

Detector

cfbV ncV

2

Vo2

Vo1

Vod

CM

VcfbT(s)

V

Vcfb = (Voc − VCM) · T (s) Voc = Vnc − Vcfb ⇒ Voc =T

1 + T× VCM +

11 + T

× Vnc

• Want large CMFB loop gain, T , to stabilize Voc.

• May want large ωt of T to suppress high-frequency components in Vnc.

• Must check the frequency stability of 1/[1 + T (s)].


A Fully Differential Two-Stage Operational Amplifier

v

Vi2Vi1

VB2

VB1

i1

g

2x

Vo1

o5

VB1

v

Cc1 Cc2

Cc1

DM Half Circuit

v o1i1

Vo2

VB1

Cc1v

CM Half Circuit

C

o1

2

VDD VDD

VDD

VSS

M3 M4

M5

M1 M2

M6

M7

M8

M9

M1

M3

M7

M6

M1

M3

M7

M6


CMFB Using Resistive Divider and Error Amplifier

IB3

VB1

VCM

VB1

B1 I

o1V

B2

o2

I

V

VDD VDD

VSS VSS

C1

R1

M7

C2

R2

M9

MB2

MB4

MB1

MB3

M6 M8

MB5 MB6

Common-Mode Feedback


CMFB Using Resistive Divider and Error Amplifier

C1

R1

MB3

mb1g

2

MB5MB6v

C

nc1i

nc2i

Cc1

oc

v

L

oc

M7

M6

• The loop gain |T | ≈ gmb5(ro6 ‖ ro7) · gmb1/(2gmb3).

• C1 and C2 are used to improve high-frequency response.

• The resistive loading of R1 and R2 can degrade Adm. Voltage buffers can be addedbetween the opamp’s outputs and the resistive divider.


CMFB Using Resistive Divider and Direct Current Injection

I

VB1

B2B1

VB1 IB3

CM

I

o2Vo1V

V

VDD VDD

VDD

VSSVSS

C1

R1

M7

C2

R2

M9

M6 M8


MB3MB1 MB2



VB1 VB1

CM 1I2I

o2V

o1V

B3I B4I

3I

IB1 IB2

V

VDD

VSS

VDD

VSS

M7 M9

M6 M8

MB7 MB8

MB1MB2MB4MB3

MB6 MB5




For the MB1-MB2 and MB3-MB4 source-coupled pairs,

IBB = IB3 = IB4 = 2 × k

2· V 2

ov k = k′(W

L

)

Idd =k

2Vid

√4IBB

k− V 2

idId1 =

IBB

2+Idd

2Id2 =

IBB

2−Idd

2

I1 =IBB

2+k

4(Voc + Vod/2 − VCM)

√4IBB

k− (Voc + Vod/2 − VCM)2

≈IBB

2+k

4(Voc − VCM + Vod/2)

√4V 2

ov − (Vod/2)2 − (Voc − VCM)Vod

≈IBB

2+k

4(Voc − VCM + Vod/2)

√4V 2

ov − (Vod/2)2

×

1 − 1

2

[(Voc − VCM)Vod

4V 2ov − (Vod/2)2

]− 1

8

[(Voc − VCM)Vod

4V 2ov − (Vod/2)2

]2

+ · · ·



I2 ≈IBB

2+k

4(Voc − VCM − Vod/2)

√4V 2

ov − (Vod/2)2

×

1 +

12

[(Voc − VCM)Vod

4V 2ov − (Vod/2)2

]− 1

8

[(Voc − VCM)Vod

4V 2ov − (Vod/2)2

]2

+ · · ·

I3 = I1 + I2 ≈ IBB +k

2(Voc − VCM)

√4V 2

ov − (Vod/2)2

×

1 − 1

4

[V

2od

4V 2ov − (Vod/2)2

]− 1

8

[(Voc − VCM)Vod

4V 2ov − (Vod/2)2

]2

+ · · ·

• The input devices, MB1–MB4, must remain in the forward-active region over thevoltage range of Vo1 and Vo2.

• The variation in Vod can produce an ac component in I3 as well as Voc.

• If Voc = VCM , I1 and I2 are nonlinear functions of Vod , but I3 = I1 + I2 is a constant.



MB3

MB5

MB6

VB1

MB4

MB2

B2

VB1

Vo1

Vo2

MB1VCM

IB3I

V

1I 2I

x y

B1

V

I

VDD

VSS

VDD

VSS

M7 M9

M6 M8




MB1, MB2, and MB5 are in the triode region. Let kB1 = kB2 = kB5 = k,

I1 = k

(Vo1 − Vtn −

12Vx

)Vx I2 = k

(Vo2 − Vtn −

12Vx

)Vx IB3 = k

(VCM − Vtn −

12Vy

)Vy

⇒ I1 + I2 = 2k(Voc − Vtn −

12Vx

)Vx Vx ≈ Vy =

IB3

k(VCM − Vtn − 1

2Vy)

I1 + I2 = 2IB3 ·Voc − Vtn − 1

2Vx

VCM − Vtn − 12Vy

= 2IB3

(1 +

Voc − VCM

VCM − Vtn − 12Vy

)

• Output swing is reduced, since it is required that Vo1,o2 > Vtn + Vx.

• MB1 and MB2 are in the triode region, their effective gm can be small, thus degradingloop gain and bandwidth of the CMFB.



S2S1

S8VB1

S5 S6

S4S3

C4C2

VB1 S7

C1

MB3MB2

Vo1

Vo2

MB1

IB1 IB2

C3

1

φ

2

IB3

CBVx

φ

VCB

VCM

V2

2

2

I1 I2

VCM

1

1

2

1

1

VDD

VSS

VDD

M7 M9

M6 M8


VSS

Voc − Vx = VCM − VCB ⇒ Voc ≈ VCM



• The opamp operates in two different modes. It is in the normal mode when φ2 is low.

• Assuming ∆Q charges are injected into C3 and C4 when φ1 switches are turned off,

Voc − Vx = VCM − VCB +∆Q

C3⇒ Voc ≈ VCM +

∆Q

C3

• The loop gain of the CMFB is approximately

|T | ≈C1

C1 + Cgs,B1× gm,B1 · Ro1

• C1 and C2 add differential-mode capacitive loading to the outputs.

• The additional common-mode capacitive loading is (C1 + C2) ‖ (Cgs,B1 + Cgs,B2).

• The value of C3,4 may be between 1/4–1/10 of C1,2 for low-pass filter function.



V

o1V

BN1V

BP1

1I

VBP2

V

VVi2

CMFB

V

Vi1 o2

BN2 BN2

VDD

VSS

M4

M10

M2M1

MB3M6M5 MB4

MB1M8M7 MB2

M3

M9



• Frequency compensation is provided by the capacitive loads at the outputs.

• Non-dominant poles are determined by M3 and M4, and ≈ ωt3 (ωt4).

• It is not uncommon that ID1,D2 ID3,D4.

• For high-speed designs, use pMOST input stage. The resulting opamps has highernon-dominant poles.

• Active cascode configuration can be applied to M3, M4, M5, and M6.



i1

V

V

o1VV

BP2V

i2

CMFB

o2

1IBN1

BN2V

V

VBN2

VDD

VSS

M2M1

M3 M4 M5M6

M9M10 M12

M13M14

M7M8

MB3MB4

MB1MB2

M11



The M3-M5 and M4-M6 current mirrors have a current gain of K .

(W

L

)3

=(W

L

)4

=1K

(W

L

)5

=1K

(W

L

)6

ID1 = ID2 = ID3 = ID4 =1KID5 =

1KID6 =

12I1

• The single-ended maximum output current for slewing is

Io(max) =K

2I1

• For a general-purpose fully differential opamp, may use large pMOST input stage,K=2, and wide-swing enhanced output-impedance cascode current mirrors.


Current-Mirror Push-Pull Operational Amplifier

1

CMFBCMFB

I1I

Vo2o1Vi2VVi1

Vi2 Vi1

VSS

VDD

1:1K:1

K:1

1:1 1:K

M1 M2 M3M4

1:K


Current-Mirror Push-Pull Operational Amplifier

• The single-ended maximum output current for slewing is

Io(max) = K I1

• The small-signal response is slower due to additional signal paths.



CMFB1 2I

o1V o2V

Vi2i1

I

CMFB

V

VSS

1:KK:1

M1 M2M3 M4

VDD

K:1 1:K

M5 M6M7 M8

II



If nMOSTs M1–M4 are identical, and pMOSTs M5–M8 are identical, and all currentmirrors have a current gain of K , then the bias currents are

ID1 = ID2 = ID3 = ID4 =1KI1 =

1KI2 = I

• Low quiescent power and large slew rate.

• The input level shifter increases the noise and offset, and adds additional poles.

• Not suitable for low-voltage operation.



M10

M6

b2

Telescopic-Cascode

VB2

Vb1

B4

V o2Vi2Vi1V

V

b3V

VB3M4

M8

M9

M3

Two-Stage

V

Vi1 Vi2Vo1 Vo2

VB1

M5

M7

o1

V o1V

i2Vi1V

Vb4

B2

M11

o2

VB1

V

b4

Folded-Cascode

V

c2

VSS

VDD

VSS

VDD

C c1C

VDD

M6

VSS

M3 M4M5

M1 M2

M7M9M8

M1

M4

M6

M8

M2

M3

M5

M7

M9

M2M1

∆Vo(Two Stage) = VDD − 2VDSAT ∆Vo(Telescopic) = VDD − 5VDSAT − 3Vmargin

∆Vo(Folded-Cascode) = VDD − 4VDSAT − 2Vmargin

SNR · Speed

Power∝

∆V2o

kT/C·gm/C

VDD · I∝

∆V2o

VDD


Active-Cascode Telescopic Operational Amplifier

A1

VB1M7

M3

VB4

V o1V

i2Vi1V

V

PCV

M9

A2

M5

NC

o2

VDD

VSS

M8

M4

M6

M1 M2

• Have the best speed/power ratio.

• A1 and A2 auxiliary amplifiers are used to increaseoutput impedance and the dc voltage gain, Av(0).

• Explicit compensation capacitors may be required atthe outputs of A1 and A2.

• To increase ∆Vo, M7, M8, and M9, can be biased inthe triode region. However, Av(0) is reduced due to thereduced ro of M7 and M8. Also, CMRR and PSRR aredegraded due to the reduced ro of M9.

• Reference: Gulati and Lee, JSSC 12/98, pp. 2010–2019.


Fully Differential Gain-Enhancement Auxiliary Amplifiers

V

A1 Aux Amplifier A2 Aux Amplifier

Ma1

Mb1Vi

Vb1

Vi

B1

VNC

Vo

V

b4

VB1

VoVo

VVV

V VB4

PC

VB3

V

i

B4oV

B2i

VDD

VSSVSS

VDD

VDD

VSS

• VS3 ≈ VS4 ≈ VNC, due to the CMFB of M3, M4, and A2.

• VS5 ≈ VS6 ≈ VP C, due to the CMFB of M5, M6, and A1.



V

A3 Aux Amplifier

A2 Aux Amplifier

A3

M9

B1

M3

VNC

V

Vy

Cc

VNCA2

Vbt

M9r

i

Ic

Vo2 Vo1

Vi1 Vi1Vi2

V

Vbt

B4

NC

VB1

VoVo

VVB3

V y i

V

VSS

VDD

VSS

VSSVSS

VDD

M4

M1 M2 M1r M2r



• The feedback loop increase M9’s output resistance, Ro9, i.e.,

Ro9 = ro9

[1 + A3 · (gm9rro9r)(gm1rro1r)

]= ro9

[1 + Aloop

]

• It can be shown the effective common-mode transconductance of M1-M2-M9 is

Ge = Gm ×1 + Aloop ·M

1 + Aloop

M = 1 −gm9

gm9r·Gmr

Gm

Gm =gm

1 + gmro9gm = gm1 + gm2

Gmr =gmr

1 + gmrro9rgmr = gm1r = gm2r

• The mismatch M and the bandwidth of the feedback loop limit the enhancement effect.


Operational Amplifiers and Their Basic Configurations

Jieh-Tsorng Wu

July 16, 2002

A

1896



Single-Ended Output Fully Differential

i

oVi

Vi

Vo

V

Vi

Vi Vo

V

cm

ii

A/2 x V

A/2 x V

A x V

• Vo = A × Vi

• Ideal opamp:

– A→∞, Zin→∞, Zout → 0.– No frequency dependence.

Opamps-BC 16-2 Analog ICs; Jieh-Tsorng Wu

Operational Amplifier Imperfections (I)

VDD

VSS

Vi+

Vi−

IB1

IB2

Vo

VOS

IB

IB

IOS2

Zid

Zic

Zic

Zo

VeAVe

Differential Input = Vid ≡ Vi+ − Vi− Common-mode Input = Vic ≡Vi+ + Vi−

2


Operational Amplifier Imperfections (II)

• Finite differential-mode gain, Adm ≡dVodVid

∣∣∣Vic=0

• Non-zero common-mode gain, Acm ≡dVodVic

∣∣∣Vid=0

Common-Mode Rejection Ratio (CMRR) ≡∣∣∣∣Adm

Acm

∣∣∣∣• Frequency response: Adm(s) and Acm(s).

• Input impedance: Zid and Zic.

• Output impedance: Zo.

• Power supply bias current: IDD.


Operational Amplifier Imperfections (III)

• Input offset voltage: VOS ≡ (Vi+ − Vi−)|Vo=0

• Input bias current: IB ≡ (IB1 + IB2)/2

• Input offset current: IOS ≡ IB1 − IB2

• Input common-mode range: Vic(max) and Vic(min). Range of Vic for which amplifier isoperational.

• Output voltage range: Vo(max) and Vo(min).

• Maximum output currents: I+o(max) and I−o(max).

• Internal slew rate: SR+ and SR−. Internally-limited rate of change in Vo in responseto a step input.


Operational Amplifier Imperfections (IV)

• Power supply signal gain: ADD(s) and ASS(s). Power supply rejection ratio (PSRR)are:

PSRRDD ≡∣∣∣∣Adm

ADD

∣∣∣∣ PSRRSS ≡∣∣∣∣Adm

ASS

∣∣∣∣• Supply capacitance. Capacitive coupling between power supplies and the opamp’s

input leads.

• Inherent noises in active devices and resistors.



Vi Vo

−AV −

Z

Z1

I

I1

V−

I−

Let Zin =∞ for the opamp, then

I− = I1 − I =Vi − V

−

Z1−V− − Vo

Z= 0

Vo = −A × V −

Closed-Loop Gain = ACL =Vo

Vi= − Z

Z1

1

1 + 1A

(1 + Z

Z1

) = − Z

Z1

(1

1 + εrr

)

Input Impedance = Zic =Vi

I1=

Z1

1 + ACL

A

≈Z1

1 + 1A·(− Z

Z1

)Opamps-BC 16-7 Analog ICs; Jieh-Tsorng Wu


The error term, εrr(s), is due to the finite opamp gain.

εrr =1A

(1 +

Z

Z1

)

• εrr(s) can be expressed in terms of magnitude and phase, i.e.,

εrr(jω) = mrr(ω)ejϕrr (ω) ≈ mrr(ω) + jϕrr(ω)

• If εrr 1,

ACL ≈ −Z

Z1· (1 − εrr)


Examples of Inverting Configuration

R1 R1

Inverting Amplifier Inverting Integrator

R

ViVo

ViVo

C

For the inverting amplifier

ACL = − R

R1

(1

1 + εrr

)εrr =

1A

(1 +

R

R1

)

For the inverting integrator

ACL = − 1sR1C

(1

1 + εrr

)εrr =

1A

(1 +

1sR1C

)


Inverting Summer Configuration

Vo

Z

1Z

Z 2

Z N

V

V

V

1

2

N

Vo = −N∑i=1

(Z

Zi

Vi

)·

1

1 + 1A

(1 +∑N

i=1ZZi

) = −

N∑i=1

(Z

Zi

Vi

)·(

11 + εrr

)


Noninverting Configuration

Vi

Vo

A(Vi − V−)

ZA

ZB

IA

IB

V−

I−

Let Zin =∞ for the opamp, then

I− = IB − IA =Vo − V

−

ZB

− V−

ZA

= 0

Vo = −A × (Vi − V −)

Closed-Loop Gain = ACL =Vo

Vi=(

1 +ZB

ZA

) 1

1 + 1A

(1 + ZB

ZA

) = ACL,∞(s)

(1

1 + εrr

)

Input Impedance = Zic = Zi(1 + T ) Output Impedance = Zoc =Zo

1 + T

T = Loop Gain = A ×ZA

ZA + ZB


Switched-Capacitor Applications

1

Model During

oI

φ

2

2

1φ

φ

1

2

1

iV

L

V o

C2

C C CL

V o

C2

V i

C1 V a1C

p

For the opamp in closed-loop gain calculation, let Vo = −A × Va.

C1(Vi − Va) = CpVa + C2(Va − Vo) ⇒ C1

(Vi +

Vo

A

)= −Cp

Vo

A− C2Vo

(1A+ 1)

ACL =Vo

Vi= −

C1

C2

1

1 + 1A

(C1+C2+Cp

C2

) = −

C1

C2

(1

1 + εrr

)εrr =

1A

(1 +

C1 + Cp

C2

)



For the opamp in step response calculation, let Io = −GmVa.

C1(Vi − Va) = CpVa + C2(Va − Vo) Io = −GmVa = sC2(Vo − Va) + sCLVo

⇒ ACL =Vo

Vi= −

C1

C2

1 − s · C2

Gm

1 + s · (C1+Cp)C2+(C1+C2+Cp)CL

C2Gm

= −

C1

C2

1 − s · C2

Gm

1 + s · τa

τa =(C1 + Cp)C2 + (C1 + C2 + Cp)CL

C2Gm

=C1 + C2 + Cp

C2·CL + [(C1 + Cp) ‖ C2]

Gm

Open-Loop Unity-Gain Frequency = ωu,OL =Gm

C′L

C′L= CL + [(C1 + Cp) ‖ C2]

Feedback Factor = f =C2

C1 + C2 + Cp

Closed-Loop −3 dB Bandwidth = ωu,CL = ωu,OL · f =1τa



The closed-loop step response is

Vo(t) = Vstep

(1 − e−t/τa

) dVo

dt

∣∣∣∣t=0

=Vstep

τa

The settling time is

tsettle = τa × ln(

1ε

)ε = 1 −

Vo(tsettle)

Vo(∞)

• For ε < 0.001, require tsettle > 6.9 × τa.

• Total delay can be estimated by

td = tslew + tsettle =Vstep

SR+ τa × ln

(1ε

)


Analog Switches and Sample-and-Hold Circuits

Jieh-Tsorng Wu

October 8, 2002

A

1896



φφ

φφ

Hφ

L

V o

CL

i

V o

kTs

V o (k)

o

V

VS/H

Switched-Capacitor S/H

V i M11iV

Vo(k) = (1 + ε) × Vi(kTs + ∆t) + Vos

S/H 17-2 Analog ICs; Jieh-Tsorng Wu


Impairments:

• Finite bandwidth in sample mode.

• Acquisition time and hold settling time.

• Aperture jitter ∆t.

• Sampling pedestal (Offset VOS and gain error ε).

• Droop in hold mode.

• Feedthrough.

• Thermal Noise.


MOST Switches in Sample Mode

φ= φH

Cgd

Cdb

gs

Csb CL

V oV i

g on

C

B

’’

S D

G

gon = µCox

W

L(VGS − Vt) = µCox

W

L(ϕH − Vi − Vt)

Cgs = Covs +12WLCox Cgd = Covd +

12WLCox

C′sb

= Csb +12WLCJ(VSB) C′

db= Cdb +

12WLCJ(VDB)


MOST Switches from Sample to Hold Mode

φ

Lφ

Hφ

G

V i

Cov CCH

Q CH

V o

CL

ovC

DS

Vo = Vi + ∆V = (1 + ε)Vi + VOS

• ∆V is due to switch’s clock feedthrough and charge injection.

• ∆V depends on the waveform of φ.

• Due to the finite slope of φ, the exact turn-off time of the switch depends on Vi .


Switching Errors in Slow-Gating MOST Switches

The body effect of MOSTs can be approximately by

Vt = Vt0 + γ

(√VS + 2φf −

√2φf

)≈ Vt0 + (n − 1)Vs

• n is a constant, and 1 < n < 2.

For slow gating (slow φ fall time), ∆V is due to the clock feedthrough after the switch isturned off.

∆V = −Cov

Cov + CL

(Vi + Vt −φL) = −Cov

Cov + CL

(nVi + Vt0 −φL) = εVi + VOS

⇒ ε = −n ·Cov

Cov + CL

VOS = −(Vt0 −φL) ·Cov

Cov + CL


Switching Errors in Fast-Gating MOST Switches

For fast gating (fast φ fall time), assuming the channel charge QCH is divided equallybetween input and output, then

∆V = −(φH −φL)Cov

Cov + CL

+12QCH

1Cov + CL

= εVi + VOS

QCH = −CCH · [(φH − Vi) − Vt] = −CCH · (−nVi +φH − Vt0)

CCH = Cox ·W (L − 2LD)

⇒ ε = +n

2·

CCH

Cov + CL

VOS = −(φH −φL)Cov

Cov + CL

− 12

(φH − Vt0)CCH

Cov + CL

• In practice, ε and VOS decrease with increasing fall time of φ.

• The body effect of Vt can cause nonlinearity.


MOST S/H Speed-Precision Tradeo ff

ViV Vi

Q C

On Conductance = gon = µCox

W

LVov

Charge Injection = ∆Q = α ·Q

Q = CoxW LVov = gon ·L

2

µ

Time Constant in Sampling Mode = τon =C

gon

Absolute Voltage Error = ∆V =∆Q

C=

αL2

µτonRelative Voltage Error =

∆V

Vi=

αL2

µτonVDD

• Want Ts,on > 7τon for a 0.1% settling accuracy, where Ts,on is the sampling time.

• α can be reduced by compensation.

• Relative error ∆V/Vi is increased when reducing VDD.


Aperture Jitter Due to the Finite Falling Time

VDD

Vi Vt

tf

t

kTs

s

φ

Vi

0 t

kTs(k-1)T

Vo φ

C

∆t = tf ×VDD − (Vi + Vt)

VDD

0 ≤ ∆t ≤ tf

(1 −

Vt0

VDD

)

• The jitter is input dependent, and introduces noise at output.



VoV iViV o

C

Ron m Ts

(f)Sn H(f)SnS

C

Ts

During sampling mode, the two-sided noise PSD at Vo is

SSn (f ) = Sn(f ) =

12· 4kTRon · |H(j2πf )|2 =

12·

4kTRon

1 + (2πfRonC)2Bn =

14RonC

• For sampling rate fs = 1/Ts, want

Ts,on = m · Ts > 7 · RonC ⇒ Bn >74· 1m· fs or Bn ≥ 5fs



During the hold mode, the noise is sampled and the noise PSD is

SHn (f ) =

∞∑i=−∞

Sn(f − i · fs) ≈2Bn

fs× Sn(f ) ≈

1/(2RonC)

fs× 2kTRon =

kT

C· 1fs

• It is assumed that Bn fs.

• The total noise power in the baseband −fs/2 ≤ f ≤ fs/2 is hence kT/C.

• Want large C for low-noise performance.

• Reference: Roubik Gregorian and Gabor Temes, “Analog MOS Integrated Circuits forSignal Processing,” John Wiley & Sons, Inc., 1986.


Charge Compensation for MOST Switches

Dummy Switch Dummy Switch with Equalizing Capacitor

CL

V o

L

RS

V

C

RS

o

CL

ii

VV

M1 M2M1 M2

φ φφ φ

∆Q1 ∆Q1 ∆Q1∆Q2 ∆Q2

Design the M2 dummy switch so that

L2 = L1 W2 =12W1

Then

∆Q1 = ∆Qov1 + α∆QCH1 ∆Q2 = ∆Qov1 +12∆QCH1

• The problem is that α is not exactly 1/2.


Differential Sampling

i2

o1V

φ

Vo2V

i1V

CL

M1CL

M2

Vo1 − Vo2 = [Vi1(1 + ε1) + VOS1] − [Vi2(1 + ε2) + VOS2]

= (Vi1 − Vi2)[1 + εD] + (Vi1 + Vi2)εC + VOS

εD =ε1 + ε2

2= Differential-Mode Gain Error

εC =ε1 − ε2

2= Common-Mode Gain Error

VOS = VOS1 − VOS2 = Offset

• The switching errors of M1 and M2 at Vo1 and Vo2 are to the first order equal andhence appear as a common-mode component at the output.

• Good CMRR and PSRR. Less sensitive to φ waveform.

• The body effect can cause εC = 0 as well as nonlinearity.


Bottom-Plate Sampling

φa

Vi

φa

Vo

φ

φ

Q1

Q2

kTs

M1

M2

x

BA C

C

The charge in C can be expressed as

QC(A) = C · Vi(t)QC(B) = C · Vi(kTs) − ∆Q2

QC(C) = C · Vi(kTs) − ∆Q2 + ∆Q1 ≈ C · Vi(kTs) − ∆Q2

• The switching charge ∆Q2 is independent of Vi , andcontains little noise due to aperture jitter.

• Since node x is floating during period B and C, theswitching charge ∆Q1 ≈ 0.

• Parasitic capacitance from node x to ground canenhance ∆Q1.


Complementary Analog Switches

g n

g p

0 1

A B A B

gap

V DD

VV i i V

V

i

DD

gon = µCox

W

L(Vg − Vs − Vt) = β(Vg − Vt0 − nVs) β = µCox

W

LVt = Vt0 + (n − 1)Vs

gn = βn[VDD − Vt0,n − nnVi ] gp = βp[VDD − Vt0,p − np(VDD − Vi)]

VDD(min) =nnVt0,p + npVt0,n

nn + np − nnnp

VDD(min) =2Vt0

2 − nif nn = np and Vt0,n = Vt0,p

• If VDD > VDD(min), no gap between gn and gp curves, thus conduction for any Vi ispossible by parallel connection of nMOST and pMOST.



V i+ V i-

CH

V o+

CH

VEE

VCC

I 1

CF

CF

Q1

R1 R2

Q2V o-

R3 R4

Q3 Q4

Q5 Q6

Q7 Q8 Q9 Q10

II 2 2

CF

φφ φφ



• The nonlinearities of Q1 and Q2 are canceled by Q3 and Q4.

• The differential operation results in only odd harmonics introduced by the Q5 and Q6followers.

• During hold mode (φ = 0), Q5 and Q6 are in cut-off region, the feedthrough gain is

AH(Without CF ) ≈Cje5

CL + Cje5AH(With CF ) ≈

Cje5

CL + Cje5

(1 −

CF

Cje5

)

• Reference: P. Vorenkamp, et al., Fully Bipolar 120 MS/s 10-b Track-and-Hold Circuit,JSSC 7/92, pp. 988–992.


Open-Loop MOST S/H

V iV iV o

CH2

V oA1

CH1

M1

A1

CH1

M1

M2

φ

φ φ

• M2 and CH2 are used to compensate for the switching error of M1.

• The VOS of the opamp is shown in Vo.

• The aperture jitter can be reduced by having clock signals that change above andbelow Vi by fixed amounts.



2t1t

VOS VOS

V1 V1V o

V i

CH

V o V o

CH

A1

M2

M3

M1CH

V i

A1 A1

Hold ModeSample Modeφ1

φ1

φ2

φ1

φ2φ1 = 1 φ2 = 1



To consider the VOS effect, let A1 =∞ and Vi = 0, then

Vo(t1) = VOS(t1) Vo(t2) = VOS(t2) − VOS(t1)

• The VOS is sampled in the sample mode, and canceled in the hold mode.

To consider the finite gain effect, let VOS = 0, then during the hold mode,

Vo − V1 = Vi Vo = −A1V1 ⇒ Vo =Vi

1 + 1A1

≈ Vi ·(

1 − 1A1

)

• The Vo is reset to ground in sample mode. High slew-rate opamp is required.

• The virtual ground is not ideal at high frequencies in the sample mode.

• The switching errors are concerns.


MOST S/H Using Miller Capacitor and Bottom-Plate Sampling

Vo1

Vo2

Vo1

Vo2

Vi1

VCMI

Vi2

2

2

VCMI

1

1

1

1Vi2

Vi1

Vo1

Vo2

a

a

S1

S6

S5

S4

S2

S3

CL2

CL1CL1

CL2

CH1 CH1

CH2CH2

CL1CH1

CH2 CL2

Sample Mode Hold Mode

φ1 = 1 φ2 = 1


MOST S/H Using Miller Capacitor and Bottom-Plate Sampling

• The opamp is open-loop during the sample mode. Glitches can occur during thetransition from the sample mode to the hold mode.

• VOS of the opamp is not canceled.

• The outputs, Vo1 and Vo2, are precharged to Vi1 and Vi2 during the sample mode, sothat the settling time in the hold mode can be reduced.

• The input common-mode voltage, VCMI , can be different from the value of (Vi1+Vi2)/2.

• The VCMO of the opamp’s CMFB should closely follow the value of (Vi1 + Vi2)/2.

• The mismatches of the switching errors of S3–S8 can introduce a constant offsetvoltage in the outputs.



Sample Mode Hold Mode

V i

A1

CH2CH1CH1

A1

CH2

V o

V 2A1

CH1 CH2

Q 1

Q 2

V o

M2

M1V i

V 1

φ

φa

φ

φa

φ = 1 φ = 0



Let ∆Q2 be the charge injecting to V1 when M2 turns off. Then

∆Q2 = CH1(∆V1 − ∆Vo) ∆Vo ≈ ∆V2 = −A1∆V1

⇒ ∆V1 =1

1 + A1·∆Q2

CH1∆Vo = −

A1

1 + A1·∆Q2

CH1

• ∆Q2 is independent of Vi .

Let ∆Q1 be the charge injecting to Vo when M1 turns off. Then

∆Q1 = CH1(∆Vo − ∆V1) + CH2(∆Vo − ∆V2) ∆V1 ≈ ∆Vo ∆V2 = −A1∆V1 ≈ −A1∆Vo

⇒ ∆Vo =1

1 + A1·∆Q1

CH2

• Small CH1 and CH2 can be used.



• The VOS is sampled in the sample mode, and canceled in the hold mode.

• The opamp’s output has small voltage variation. Thus, it is easier to design the opampfor high speed.

• Suitable for high speed.



A1

CH2CH1

B1

V o

Hold Mode

A1

CH2CH1

B1

V oV i

Sample Mode

CLK

A1

M1

B2B1

M5

CH3

M2

M3

M4

CH1

V o

CH2

V i

φ1

φ1 φ2

φa1

φa1

φa2

φ1

φ2

φa1

φa1

φ1

φ2



• B1 and B2 are two unity-gain buffer.

• M5 and CH3 is to compensate for the M4’s switching error.

• The switching errors of M1 and M2 does not affect Vo.

• The switching error of M3 does affect Vo. But its effect is reduced by the opamp’svoltage gain.

• Mismatch between B1 and B2 can affect Vo.


Closed-Loop S/H

V iV o

M11

CH

A1

φ


Closed-Loop S/H

• The circuit is in the track mode when φ = 1, and is in the hold mode when φ = 0.

• High input impedance.

• The offset and gain of the output buffer are not critical.

• The input offset of the A1 opamp is not canceled.

• The speed can be seriously degraded due to the necessity of guaranteeing that theloop is stable in the track mode.

• The A1 opamp is open loop when in the hold mode. It takes time to recover the biaswhen switches to the track mode.


Closed-Loop S/H with Improved tslew

V iV o1

CH

A1M1

M3

M3φ

φ

φ

• During hold mode, A1 is configured as a unity-gain amplifier. Thus, the slewing timeis greatly minimized.



V oA2

M3

V i M1

M2

A1

C

CH1

H2

φ

φφ



• When in the track mode, the voltage on both sides of M1 are closed to ground, andare nearly signal independent.

• Aperture jitter is minimized.

• The switching error of M1 causes a dc offset in Vo, which will be signal independent.

• M2 and CH2 are to compensate for the M1 switching error.

• When in the hold mode, M3 clamps the A1’s output to ground, speeding up the timeit takes the S/H to return to the tack mode.

• M3 also reduces signal feedthrough when in the hold mode.

• The speed is degraded because of the necessity to guarantee stability in the trackmode.


An RC Closed-Loop S/H

V oV i

M1

CH

A1M2

R

R

φ

φ

• The A1 opamp need to have low output impedance.



Sample Mode

Hold Mode

o

Vo

V

M3

CH1

C

M1

M2

M4

M5

M6

CH3

H4CH2

A1

V i

A2

A1

CH3

A2

CH1

CH2

o

A1

C

CH3

H4

CH1

V i

A2

CH2

V

φ1 φ2

φa1

φa2

φ1

φ2

φa1

φa1

φa2

φa2

φ1 = 1

φ2 = 1



• The Vo is always valid.

• The VOS1 of A1 is stored in CH2 during the sample mode.

• The M2’s switching error is canceled by M3.

• The M5’s switching error is canceled by M6.

• The switching error of M1 and M4 doesn’t affect Vo.


Charge Redistribution Sampled-Data Amplifier

V1

1t 2t

OSV

V oC1

OSV

V oC1

V i

OSV

1a

S3

C2

V o

Q

C12

1V i

C2C2

S2

S1

φa1

φ1

φ2

φ1 = 1 φ2 = 1



To consider the ideal case, let A =∞ and VOS = 0, then

Vo(t1) = 0

C1Vi(t1) = C2Vo(t2) ⇒ Vo(t2) =C1

C2× Vi(t1)

To consider the VOS effect, let A =∞, then

Vo(t1) = VOS(t1)

Vo(t2) =C1

C2× Vi(t1) + VOS(t1) +

(1 +

C1

C2

)×[VOS(t2) − VOS(t1)

]=

C1

C2×[Vi(t1) +

C2

C1· VOS(t1)

]+(

1 +C1

C2


]

• The input referred offset is VOS · (C2/C1).



To consider the finite gain effect, let VOS = 0, then during φ2 = 1

C1Vi + C1V1 = C2(Vo − V1) Vo = −AV1 ⇒ Vo =C1

C2· 1

1 + 1A

(1 + C1

C2

) × Vi

To consider the effect S3 switching error, let A = ∞, VOS = 0, and Vi = 0, then duringφ2 = 1

Vo = V ′OS

= −∆QC2

• V′OS is independent of input.

• If S3 is opened before S1, the switching errors of S1 and S2 have no effect on Vo.


Charge Redistribution Summing Amplifier

1

1OSV

C1

S1V i1

V2

S2

C

V

V2

i2

i3

i4

S3

S4

2

1a

S5

C3

V o

During the sample mode (φ1 = 1)

Vo = VOS

During the hold mode (φ2 = 1)

Vo =C1

C3(Vi1 − Vi2)

+C2

C3(Vi3 − Vi4) + VOS



V1

1t 2t

OSV

V oC1

OSV

V oC1

1

2V i

1a

C2 1C2

OSV

V oC1

C2

V i

S2

S1

S3

2

S5S4

φa1

φ1

φ2

φ1 = 1 φ2 = 1



Let A =∞, then

Vo(t1) = Vc1 = Vc2 = VOS(t1)

Vo(t2) = −C1

C2× Vi(t2) +

(1 +

C1

C2

)[VOS(t2) − VOS(t1)]

• The correlated double-sampling (CDS) technique, resulting in VOS(nTs) − VOS(nTs −Ts/2), can reduce the effects of the opamp’s input offset voltage and its 1/f noise.

• To minimize switching noises, realize switches with nMOSTs whenever possible, andturn off the switches near the virtual ground node of the opamps first.

• Reference: C. Enz and G. Temes, “Circuit Techniques for Reducing the Effectsof Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and ChopperStabilization,” Proc. IEEE, Nov. 1996, pp. 1584–1614.



3t 4t1t 2t

V1V1

C1

C2a1

V o

C3

1

2V i

1

OSV OSV

V o

C3

OSV

V o

C3

V i

C4

S5

S2

S1

2

S4S3

S6

2a

C1C1

C2 C2

φa1

φa2

φ1

φ2

φ1 = 1 φ2 = 1



To consider the VOS effect, let A =∞ and Vi = 0, then

V1(t1) = VOS(t1)

Vo(t2) =(

1 +C1

C2


]Vo(t3) = VOS(t3) + Vo(t2) +

C2

C3× Vo(t2) +

(1 +

C1 + C2

C3


]≈ VOS(t3)

Vo(t4) =(

1 +C1

C2


]

• During φ2 = 1, the effects of opamp’s VOS and 1/f noise are reduce by CDS.



To consider the finite gain effect, let VOS = 0, then

−C1V1(t1) − C2V1(t1) = C1[Vi (t2) − V1(t2)] + C2[Vo(t2) − V1(t2)] V1 = −Vo/A

⇒ Vo(t2) = −C1

C2· 1

1 + 1A

(1 + C1

C2

) × Vi(t2) +1A

(1 +

C1

C2

)· 1

1 + 1A

(1 + C1

C2

) × Vo(t1)

≈ −C1

C2(1 − ε1) × Vi(t2) + ε1(1 − ε1) × Vo(t1)

Vo(t3) ≈ (1 − ε2)Vo(t2) +C1

C3(1 − ε2)Vi (t2) +

C2

C3(1 − ε3)Vo(t2) ≈ Vo(t2) ≈ −

C1

C2Vi(t2)

Vo(t4) ≈ −C1

C2(1 − ε1) × Vi(t4) + ε1(1 − ε1) × Vo(t3)

≈ −C1

C2× Vi(t4) + ε1

C1

C2× [Vi(t4) − Vi (t2)] + ε2

1

C1

C2× Vi (t2)

ε1 =1A

(1 +

C1

C2

)ε2 =

1A

(1 +

C1

C3

)ε3 =

1A

(1 +

C2

C3

)



• During φ2 = 1, the effects of opamp’s VOS and 1/f noise are reduce by CDS.

• During φ2 = 1, the errors due to opamp’s finite gain, A, are proportional to 1/A2 forlow-frequency input.

• During φ1 = 1, the output keeps the value obtained in the previous φ2 = 1 period.

• C4 is an optional deglitching capacitor used to provide continuous-time feedbackduring the nonoverlap clock times. This capacitor would normally be small.

• The clock phases for S1 and S2 can be exchanged, to obtain noninverting gain.

• When CDS is used, the opamps should be designed to minimize thermal noise ratherthan 1/f noise.



C2

1a

V o

2S6

2S5

1

1C’

V i

2C’

C2

V oV i

1C’

C1

2C’

C2

V i

V o

C1

1C’

S1

2

C1

1S3

S2

S7

S9

1

S8S10

a2

2C’1

S42 A

A

φ1 = 1

φ2 = 1



• During φ1 = 1, C′1 and C′2 are used in the feedback network to have

Vo ≈ −C′1

C′2· Vi

but with errors due to VOS , 1/f noise, and A.

• During φ1 = 1, the opamp input voltage is sampled and stored in C1 and C2.

• During φ2 = 1, C1 and C2 are used in the feedback network, the output errorsdue to VOS , 1/f noise, and A are canceled by the correlated double-sampling (CDS)operation.


Comparators and O ffset Cancellation Techniques

Jieh-Tsorng Wu

October 25, 2002

A

1896


Comparators

Vi1

Vi2Vo

Vi1 Vi2

Vo VoVi2

Vi1

0

A

CLK

Latch

Typical Architecture

• A comparator compare the instantaneous values of two inputs generate a digital 1 or0 level depending on the polarity of the difference.

• Usually a clock is applied to improve the performance.

Comparators 18-2 Analog ICs; Jieh-Tsorng Wu

Comparator Design Considerations

• Resolution (gain).

• Accuracy (offset).

• Input range (dynamic range).

• Common-mode rejection.

• Speed (conversion time, over-drive recovery).

• Power dissipation.

• Input kickback noise.

• Area


Comparison with Single-Pole Amplifier

Vi

Vo

VoVi

U

tt a

A o

R

V ig m

C

U =Vo

Vi= Ao

[1 − e−ta/(RC)

]Ao = gmR τm =

C

gm

ta

τm= Ao × ln

1

1 − UAo

⇒

ta

τm≈ U if U Ao

• The amplification in a comparator need not be linear.


Comparison with Multi-Stage Cascaded Amplifier

Vi

Vo2Vo1 Vo

VV o1 o(N−1)

R C

g m g mV ig m

R C R C

ta

τm≈ (U ×N!)

1N for ta Aoτm

• There exits an optimum number of cascaded stages for minimum ta.

• Optimum in N is very broad.

• Gain of√

10 (i.e. 10 dB) per stage results in near optimum delay (within 10%).


Comparison with Positive-Feedback Regeneration

Vo1 Vo2Vo (0)

(t)

oVoV

CRRC

U

tg m g m t a

U =Vo(ta)

Vo(0)= e

(Ao−1)taRC Ao = gmR τm =

C

gm

ta

τm=

1

1 − 1Ao

× ln(U) ⇒ta

τm≈ ln(U) if Ao 1


Comparison with Positive-Feedback Regeneration

• The gain is not bounded by Ao.

• It is faster than the multi-stage cascaded amplifier, and dissipates less power.

• Require a strobe signal (clock).

• Let Tc be the conversion time, the final output Vo(Tc) = V , and the initial sampledinput Vo(0) has a uniform distribution between −V and +V . Then the probability ofobserving a metastable state is

P =V/U

V=

1U

= e−(Ao−1)Tc

RC ≈ e− TcC/gm

The metastable state occurs when the sampled input is so small that the regeneratedoutput, |Vo|, cannot reach |V | after the Tc period.


Output O ffset Storage (OOS)

V o

CL1a

S3

oV’Q

V i

V OS

V c

CoV OSL

LatchAS1

2

S21

During the reset mode (φ1 = 1)

Vo = 0 Vc = A × VOS

During the amplification mode (φ2 = 1)

V ′o = Vi × A ·Co

Co + CL

+∆Q

Co + CL

− VOSL = A ·Co

Co + CL

(Vi +

∆Q

ACo

−VOSL

A·Co + CL

Co

)

Input-Referred Offset = VOS,in =1A· ∆QCo

−VOSL

A·Co + CL

Co


Output O ffset Storage (OOS)

• During the reset-to-amplification transition, let S3 open before S2, so that ∆Q can bea constant.

• Amplifier A cannot employ high gain.

• Amplifier A must cover the input common-mode range.

• Want latch with high-impedance (capacitive) input so as not to discharge Co duringamplification.

• Make Co CL to avoid attenuation.


Multistage Output O ffset Storage

V oV i

S1

S2

C

V

1

c1 X

V OS1

1A

S3

C

V

2

Yc2

V

A 2

OS2

S4

C

V

3

c3

V

A 3

OS3

S5

S3

S5

S2

S1

S4

II III IV VI



During Period I, S1 open, S2–S5 closed.

Vc1 = A1VOS1 Vc2 = A2VOS2 Vc3 = A3VOS3

During Period II, S3 open.

VX = ε2 = S3 Switching Error Vc1 = A1VOS1 + ε2 Vc2 = A2(VOS2 − ε2)

During Period III, S4 open.

VY = ε3 = S4 Switching Error Vc2 = A2(VOS2 − ε2) + ε3 Vc3 = A3(VOS3 − ε3)

During Period IV, S5 open.

Vo = ε4 = S5 Switching Error Vc3 = A3(VOS3 − ε3) + ε4



During Period V (amplification mode), S2 closed, S1 open.

Vo = A1 · A2 · A3 · Vi + ε4

VOS,in =ε4

A1 · A2 · A3


Input O ffset Storage (IOS)

V c

V OS

1a

S3

V iiC

V o

CL

Q

AS2

2

1

S1

V OSL

Latch oV’


Vo = Vc = VOS ×A

A + 1


V ′o = −Vi × A + VOSA

A + 1− ∆Q

Ci

A − VOSL = −A(Vi −

VOS

A + 1+∆Q

Ci

+VOSL

A

)

Input-Referred Offset = VOS,in = −VOS

A + 1+∆Q

Ci

+VOSL

A


Input O ffset Storage (IOS)

• The S3 switching error ∆Q is input-independent.

• During the reset-to-amplification transition, let S3 open before S2.

• The IOS allows rail-to-rail input common-mode level and quick overdrive recovery.

• Amplifier A can employs high gain.

• Amplifier A may require compensation Cc to ensure closed-looped stability. Cc canbe switched off during the amplification mode.


Multistage Input O ffset Storage

V oC1

Vc1

C2

Vc2

X

V

A

S3

V

A 1

OS1

S4

OS2

2

S1

S2

V i

S1

S2

S3

S4

I II III IV



During Period I, S1 open, S2–S4 closed.

Vc1 =A1

A1 + 1VOS1 Vc2 =

A2

A2 + 1VOS2 − Vc1 =

A2

A2 + 1VOS2 −

A1

A1 + 1VOS1

During Period region II, S3 open. Let ε1 be the 3 switching error.

Vc1 =A1

A1 + 1VOS1 + ε1 Vc2 =

A2

A2 + 1VOS2 −

A1

A1 + 1VOS1 + A1ε1

During Period III, S4 open. Let ε2 be the S4 switching error.

Vc2 =A2

A2 + 1VOS2 −

A1

A1 + 1VOS1 + A1ε1 + ε2 Vo =

A2

A2 + 1VOS2 − A2ε2



During Period IV (amplification mode), S2 open, S1 closed.

Vo = A1A2Vi +A2

A2 + 1VOS2 − A2ε2 = A1A2

[Vi +

VOS2

A1(A2 + 1)−

ε2

A1

]

Input-Referred Offset = VOS,in =VOS2

A1(A2 + 1)−

ε2

A1



VSS

VDD

2

1MB

V o

V i1

V i2

V o

V x

CI

S1

S2

1

S3

XMA

Bias Poin t



• Trade-off between speed and resolution by selecting different value of C.

• Very sensitive to supply noises.

• Power dissipation is strongly process- and supply-dependent.

• Kickback noise presented at the inputs.

• Reference: T. Kumamoto, et. al., JSSC, 12/86, pp. 976–982.


MOST Comparator: Cascaded Auto-Zeroing Inverters

S1

S2

S3 S4C1 C2

M1

M2

M3

M4

VSS VSS

VDDVDD

CK

Latch

V i2

V i1

V o

S1

S2

S3

S4

CK


MOST Comparator: Preamp + Regenerative Sense Amplifier

VDD

VSS

V i1

VSS

V i2

VSS

V o

I 1

M1 M2

M3

M4

M5

M6

M7 M8 M9 M10

M11 M12VDD φ



• During the track mode (φ = 1), want gm7,m8 < gm9,m10 so that the combination ofM7-M8 and M9-M10 pair become the resistive loads for M5 and M6. The small-signalvoltage gain is

vo

vi≈

gm1

gm9 − gm7·(W/L)6

(W/L)4

• During the latch mode (φ = 0), M7, M8, and M11 must be large enough to preventthe change of latched state by the Vi variation.

• All nodes are low impedance, thus giving fast operation.

• Overdrive recovery can be improved by adding an equalizing switch between the Vonodes.

• The preamplifier buffers the kickback from the input circuitry.

• Reference: B. Song, et al., JSSC, 12/90, pp. 1328–1338.



VDD

VSS

V i1

VSS

V i2

I 1

VSS

VDD

V o

M3

M4 M6

M5

M1 M2

M7M8M9 M10

M11 M12

M13

IVT1

IVT2

A

B

φ

φ



• During the track mode (φ = 1), need M7 and M8 large enough to overpower the M9-M10 cross-coupled pair and pull VA and VB below the input threshold level of IVT1 andIVT2.

• During the latch mode (φ = 0), the M9-M10 and M11-M12 pairs provide regeneration.They must be large enough to to prevent the change of latched state by the Vivariation.

The input threshold level of IVT1 and IVT2 must be high enough to avoid falsetriggering.


MOST Comparator: Merged Preamp + Sense Amplifier

CKCKM8

M2

M7M5

M9 M10

M11

M4M3

M1

CK

Vi

Vo

M6

VSS

VDD

• No power dissipation whenCK=0.

• When CK=1, the M1-M2 pair isactivated first, the M3-M4 pair issecond, and the M5-M6 pair isthe last.

• Kickback noise is generated atinput during the 0-to-1 transitionof CK.

• Reference: B. Razavi, 1999ISSCC Short Course.


Offset Canceled Latches: Idea

Gm1

RL1

RL2

V i V o

Gm2

C1

C2

S5

S6

S1

S2

S3

S4

12

1

1

• During reset mode (φ1 = 1), the OOS is applied to both Gm1 and Gm2.

• During reset mode, the finite on-resistance of S5 and S6 may cause oscillation.

• During reset-to-regeneration transition, any mismatch of the switching errors betweenS5 and S6 can trigger a false regeneration, yielding a large input-referred offset.


Offset Canceled Latches: Simplified Schematic

Gm1

RL1

RL2

V i V o

C2

C1

S31

Gm2

a2

S1

S2S41

B1

B2

S51

S61

1

S7

S8

S9

S10

1

2

2


Offset Canceled Latches: Simplified Schematic

• During reset mode, the positive feedback loop is completely broken.

• The regeneration begins only after Vi has been sensed and amplified.

• Buffers B1 and B2 isolate output nodes from C1 and C2, thus enhancing regenerationspeed.

• The residual offset is primarily cause by the switching errors of S5–S10.

• Reference: B. Razavi, et al., “Design Techniques for High-Speed High-ResolutionComparators,” JSSC, 12/92, pp. 1916–1926.


Offset Canceled Latches: MOST Implementation

VSS

VSSVSS

VDD

V o+ V o-

V 1+

V 2+ V 2-

V 1-

VSS

V B1 V B1

M1 M2

I1

I2

M3 M4

M5 M6M7 M8

M9M10

C1 C2

I4I3

MS1

MS3

MS2

MS4

MS5 MS6

MS7 MS8

MS9 MS10A B

E F DC

φ1 φ1

φ1 φ1

φ2 φ2φ1φ1


Offset Canceled Latches: MOST Implementation

• M7 and M8 are active loads, which both decrease the voltage drops across M5 andM6, increase available gain, increase Vo output swing, and enhance speed.

• An equalizing switch driven by φd1 can be placed between node C and D to eliminate

the switching error mismatch between MS7 and MS8.

• An equalizing switch driven by φd2 can be placed between node E and F to eliminate

the mismatch between MS5 and MS6. In this case, MS9 and MS10 are driven byφ

dd2 and the charge absorption mismatch between MS9 and MS10 becomes the only

significant contribution to the offset, which is

VOS(in) =∆Q

C·gm3 + gm7

gm1

• Reference: B. Razavi, JSSC, 12/92, pp. 1916–1926.



V oV i

Q1 Q2 Q3 Q4

Q5 Q6

Q7

Q8

R1 R2

I1 I2 I3

VEE

VCC

φ



• During the track mode (φ = 1), the variation of input capacitance with Vi causesinput-dependent delay and hence harmonic distortion.

• Speed may be limited by overdrive recovery.

• During latch-to-track transition, Q1 and Q2 are initially off, the I1 current then flowsthrough Q5 and the emitter junctions of Q1 and Q2 to the input, creating kickbacknoise.

• Usually preceded by a buffer.


BJT Comparator with High-Level Latch

I1

VEE

VCC

V i

V o

R1 R2

Q1 Q2

Q6 Q7Q8

Q3 Q4

Q5

AB

φ φ

• During the latch mode (φ = 0), the variationin Vi will not disturb the latched state.

• Q1 and Q2 are never turned off, thusreducing kickback noise.

• The kickback noise results only from thetransients at nodes A and B. Adding aresistor between A and B decreases thesetransient and improves the recovery at thesenode.


A Sampled-Data Amplifier with Internal O ffset Cancellation

V o1

V o2

C3

C5

C6

o1V

o2V

C5

C6

V o2

V o1

V i2

V i1

C1

2CC3

C4

C41

1

2

2

C

C

C

C

3

4

5

6

a1 a2

1

1

1

1

a1 a2

C1V i1

V i2

2C

a1 a2

2C

C1

2

1

1

φ1 = 1

φ2 = 1


A Sampled-Data Amplifier with Internal O ffset Cancellation

• During reset mode, OOS is applied to a1 and IOS is applied to a2. a1 is low gain anda2 is high gain.

• The OOS and IOS perform correlated double sampling (CDS) so that the effect of 1/fnoise is also reduced.

• Additional capacitors in the signal path (i.e., C5 and C6) can degrade the closed-loopsettling behavior.

• Reference: Yen, JSSC, 12/82, pp. 1008–1013.


Operational Amplifier with O ffset Compensation

V i

C1

Gm1

Gm2

V o

C2

S1 S3

S4

2

1

1 S5

1

R

S6

S2

• The Gm2 compensation circuit is not in the signal path. The original frequency/speedperformance can be maintained.




Vo = VOS1 · Gm1R + (VOS2 − Vo) · Gm2R

⇒ Vo =VOS1 · Gm1R + VOS2 · Gm2R

1 + Gm2R⇒ Vo ≈ VOS1 ·

Gm1

Gm2+ VOS2 If Gm2R 1

• VOS1 and VOS2 are the input-referred offset of the Gm1-R and Gm2-R pairs.


Vo = Vi · Gm1R + VOS1

Gm1

Gm2+ VOS2 + ∆V · Gm2R = Gm1R

(Vi +

VOS1

Gm2R+

VOS2

Gm1R+ ∆V

Gm2

Gm1

)

Input-Referred Offset = VOS,in =VOS1

Gm2R+

VOS2

Gm1R+ ∆V ·

Gm2

Gm1

• ∆V is due to the mismatch between the switching errors of S5 and S6. Its effect on Vocan be reduced by making Gm2/Gm1 small.



2

VBP2

VBP1

Vi1 V

o1V

VBN2V

1

i2

I VBN1 I

o2

VSS

C1

VDD

C2

M4

M10

M6M5

M8M7

M3

M9

1

1

S2

S1

2

211

S5 S6

M2M1

S3

S4

M11M12


The Chopper Stabilization Technique

11fc

V

f

VOS

iV o

cfc

1f

A

f0 0000

LPF

ff ff

• The bandwidth of the amplifier A must be wider than fc.

• The amplifier A should employ design of minimizing thermal noise.



φ

φ

1

iV

I3I

I

o

L

I5

R

I1

φ

φ

V

2R1R

i

φ

V

b

a

4

2

a

a

b

b

2C

1C

VDD

VSS

M7 M8 M9

M5 M6

M4M3

M2M1



• The M1–M2 is a low-gain low-noise stage.

• The M3–M4 is a high-gain stage with low Gm. A common-mode feedback circuit isrequired to stabilize the drain voltages of M3 and M4.

• The M5–M8 is a high-gain Miller stage for frequency compensation and low-passfilter.

• The M9 is a low-gain buffer stage.

• The chopper can introduce additional kT/C noise.

• Reference: A. Bakker, et al., “A CMOS Nested-Chopper Instrumentation Amplifierwith 100-nV Offset,” JSSC 12/2000, pp. 1877–1883.

• Reference: C. Enz and G. Temes, “Circuit Techniques for Reducing the Effectsof Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and ChopperStabilization,” Proc. IEEE, 11/1996, pp. 1584–1614.


Residual O ffset of Chopper Amplifier

Residual Offset

t Spikes at Input

t

VOS

Demodulation Signal

t Demodulated Spikes

t Modulation Signal

cf

VoVi

11

f1

A

LPF



Residual Offset

t Demodulated Spikes

t

VOS

Spikes at Input

t Demodulation Signal

t Modulation Signal

cf

VoVi

11

f1

A

LPF



• The spikes at the input is due to the switching error mismatch of the chopper.

• The residual offset is linear dependent on chopper frequency.

• Reference: Q. Huang and C. Menolfi, “A 200nV Offset 6.5nV/√

Hz Noise PSD 5.6kHzChopper Instrumentation Amplifier,”, ISSCC 2002.


Oscillators

Jieh-Tsorng Wu

October 16, 2002

A

1896


The Barkhausen Criteria

S i a

f

S o

S fb

S e

So = a · Se Sfb = f · So Se = Si − Sfb

Closed-Loop Gain = A ≡So

Si=

a

1 + af=

a

1 + TLoop Gain = T ≡ a × f

The feedback system oscillates at ωo, if

|T (jωo)| ≥ 1 ∠T (jωo) = 180

OSCs 19-2 Analog ICs; Jieh-Tsorng Wu


V3V2V1

V1

V2

V3

C

R

C

R

C

R

t

VDD VDD VDD

−T (s) =[−

gmR

1 + sRC

]3

= −A

30(

1 + sωp

)3A0 = gmR ωp =

1RC



From the Barkhausen criteria,

tan−1(ωo

ωp

)= 60 ⇒ ωo =

√3ωp

A30[√

1 +(ωo

ωp

)2]3

= 1 ⇒ A0 = gmR = 2

• The phase difference between the neighboring nodes is 180 + 60 = 240.

• If A0 > 2, the oscillation amplitude increase exponentially until nonlinear effect limitsthe growth.

V (t) ∝ exp(A0 − 2

2ωpt

)cos(A0

2ωot

)


Three-Stage CMOS Inverter Ring Oscillator

V3V2V1

VDD

VDD

GND

t

fo =1

6tptp =

12

(tpHL + tpLH

)=

12

(0.69ReqnC + 0.69ReqpC

)

Req =−1

VDD/2

∫ VDD/2

VDD

V

IDSAT (1 + λV )dV ≈ 3

4

VDD

IDSAT

(1 − 7

9λVDD

)

• The oscillation frequency fo can be varied by changing VDD.


Four-Stage Di fferential Ring Oscillator

IS

V1aV1b

VB

V2c

IS

V2aV2b

Va

Vb

Vc

Vmin

VmaxR

M1 M2

M5

R C C RR

t

VDD


Four-Stage Di fferential Ring Oscillator

From the Barkhausen criteria,

tan−1(ωo

ωp

)= 45 ωp = RC ⇒ ωo = ωp

A40[√

1 +(ωo

ωp

)2]4

= 1 ⇒ A0 = gmR =√

2

The delay stage is usually designed to experience complete switching, i.e.,

Vmax = VDD Vmin = VDD − ISR ∆V = Vmax − Vmin = ISR


Differential Delay Stage

Let

∆V = ISR Vt = Vt1 = Vt2 Vov = Vov1 = Vov2 =

√√√√ 2(IS/2)

µCox(W/L)1,2

• To maintain M1 and M2 in the forward-active region, ISR < Vt1,2.

• For complete switching, want ∆V >√

2Vov ⇒ Vov < ∆V/√

2.

• For enough loop gain, want gmR = [(IS/2)/(Vov/2)] · R >√

2 ⇒ Vov < ∆V/√

2.

• The minimum VDD can be approximated by

VDD,min ≈ Vov5 + Vt + Vov +∆V

2


Delay Variation Using Variable Resistors

Vb Va

ISVct

VRVcb

M1 M2

M4M3

MB1

M5

MB2

VDD MB1=M3=M4 and MB2=M5,

∆V = VDD − VR ≈ ISRon

ωp =1

RonC≈

IS

∆V · CA0 = gm1,2Ron

=∆V

IS

√2µnCox

(W

L

)1,2

IS

=∆V√IS

√2µnCox

(W

L

)1,2

• MB1, M3, and M4 are biased in the triode region.

• A0 decreases at higher oscillation frequencies.


Delay Variation Using Positive Feedback

Vct1 Vct2Vb

Va

1R 2RIT

IS1 IS2VB2VB1VB1 VB2

M1 M2 M3 M4

M5 M6

VDD

IT = IS1 + IS2 ∆V = ITR1,2 ωp =≈ C

G1,2 − gm3,4A0 ≈

gm1,2

G1,2 − gm3,4

gm1,2 =√

2µnCox(W/L)1,2IS1 gm3,4 =√

2µnCox(W/L)3,4IS2


Delay Variation Using Interpolation

3R 4R

Vin1

Vin2

IS

IS2

1R 2R

IS1

VaVb

M5 M6

M3 M4

M1 M2VDD

VDD

IS1 + IS2 = Constant



mg

Vo

Vi90o

90o

(−H)

R

ωr

ω

ω

|H|

L C R

VDD

ωr =1√LC

Q = ωrRC =R

ωrL

H(s) =Vo(s)

Vi(s)=

gm

(sL)−1 + sC + 1/R= gmR ·

1Q

(sωr

)(

sωr

)2+ 1

Q

(sωr

)+ 1



In the frequency domain

H(jω) = gmR ·1

1 + jQ(

ωωr− ωr

ω

) = gmR · A(jω)

• A(jω) is a band-pass function with −3 dB frequencies at ω1 and ω2, and bandwidthB = ω2 −ω1.

ω1 ·ω2 = ω2r B =

ωr

Q= ω2

rRC =R

L

• If ∆ω = ω −ωr ωr , we have

A(jω) ≈ 1

1 + j2Q · ∆ωωr


LC-Tuned Ring Oscillators

V1 V2 V2V1

L C RL C R

M1 M2

L C RCR L

M2M1

VDDVDD VDD

• Oscillation frequency is ωo = ωr = 1/√LC.

• V1 and V2 are 180 out of phase.

• Need gmR > 1 to start oscillation.

• Varactors, such as pn junctions with reverse bias or MOSTs in the accumulationmode, are used for ωo variation.


Colpitts Oscillator

mg

C1

C2

Vo

V1

C1

C2

Vo

C2 mg

C1 C2C1

Vo

C1

C2

VB

s

N

L C R

L C R1 : N

L C R

VDD


Colpitts Oscillator

• The oscillation frequency is

ωo ≈ ωr =

√1

LCp

Cp = C + (C1 ‖ C2) = C +C1C2

C1 + C2

• The loop gain at ωr is

|T (jωr)| =gm

G + gm

N2

· 1N

=gm

G · N + gmN

Want

|T (jωr)| > 1 ⇒ gmR > N +gmR

N

• If C1 C2, i.e., N ∼ 1, oscillation cannot occur.


One-Port Oscillators

L C G f(V)

I

V

V

I

0

0

1L

∫V dt + C

dV

dt+ G · V + f (V ) = 0 ⇒ LC

dV2

dt+ L

d

dt[G · V + f (V )] + V = 0

• For small-signal analysis, let f (V ) = −a · V with a = − df (V )/dV∣∣V =0. Then, we have

LCs2 + L(G − a)s + 1 = 0

s1, s2 = −(G − a

2C

)± j

√1LC−(G − a

2C

)2

= α ± jβ ⇒ V (t) ≈ Aeα cosβt

Need a > G to start oscillation.



Let T = t/√LC, we have

d2V

dT 2+

√L

C· ddT

[F (V )] + V = 0 F (V ) = G · V + f (V )

The van der Pol approximation for F (V ) is

Fv(V ) = −a1 · V + b1 · V 3 a1 = a − G

V max

V x

V x

V

F v (V)

V

±Vx = ±√

a1

b1

V − =

√13·a1

b1

ε =

√L

C· a1 =

√L

C· (a − G)



For near-sinusoidal oscillations, ε > 0 and ε→ 0.

v(t) =

√43

a1

b1· 1√

1 + e−(t−t0)ε/√LC

cos(

t√LC

)

• At the start of oscillation, e−(t−t0)ε/√LC 1, we have

V (t) = Aeεt/(2√LC) cos

(t√LC

)= AeεT/2 cos T A =

√43

a1

b1· e−εt0/(2

√LC)

• In steady state, t→∞,

V (t) =

√43

a1

b1cos(

t√LC

)= Vmax cos T

Vmax =

√43

a1

b1=

√43· Vx = 1.15Vx = 2V −


A CMOS SONY Oscillator

VB

Io

Vo

IS

IS

VIMVIM

L C G

2

M1 M2f(V)

V

I

0

VDD

VDD V = Vo − VB

I = Io −IS

2

I = f (V ) =k

4V

√4ISk− V 2 VIM =

√2ISk

k = µCox

(W

L

)1,2


Differential CMOS SONY Oscillators

Io

IS

Io

IS

VoVo

M2M2 M1

2LC/2

G/2

M1

L C G CG L

VDDVDD

V = Vo I = Io I = f (V ) =k

4V

√4ISk− V 2 k = µCox

(W

L

)1,2


Single-Transistor Negative Resistance Generator

Ix

Vx

Cx

Vx

Ix

C1

C2

Ix

xR

Vx =(Ix −−IxsC2· gm

)1

sC1+

Ix

sC2⇒

Vx

Ix=

gm

s2C1C2

+1

sC1+

1sC2

Rx = −gm

ω2C1C2

Cx = C1 ‖ C2 =C1C2

C1 + C2


Single-Transistor Negative-Resistance Oscillators

C2

C1

C2

C1 C1

C2

C2

C1VB C1

C2

C2

VB

C1

C1

C2

L

LL

L

L

L

L

VDD VDD

VDD



Co

ωaωs

Circuit Model

R C Lω

+jX

−jX

0

Z(jω) =[R + (jωC)−1 + jωL](jωCo)−1

R + (jωC)−1 + jωL + (jωCo)−1

ωs =1√LC

ωa =1√

L(C‖Co)

ωa

ωs

=

√1 +

C

Co

Q =1

ωsRC=

ωsL

R



• Example: R = 16.3 Ω, C = 0.009 pF, L = 7.036 nH, Co = 2.3 pF; thus fo = 20 MHz,Q = 54245.

• The serial RLC can be transformed into a parallel circuit

Rp = R(1 +Q2

s

)Xp = Xs

(1 +

1

Q2s

)where Xs = ωL − 1

ωCQs =

Xs

R

At ω = ωa, with Qs 1, we have

Xp =1

ωaCo

Rp ≈X

2s

R≈

X2p

R=

1

R(ωaCo)2

• Circuits containing crystals are designed so that the frequency range of interest isbetween ωs and ωa.


Crystal Oscillators

C2

VB

C1

C1

C2

C2

C1

VB

Colpitts Oscillator

LLVDD

VDD

C1C2

VDD

Pierce Oscillator


Relaxation Oscillators (Multivibrators)

TbTa

Tba

Tab

State BState A fo =1

Ta + Tb + Tab + Tba

fo,max ≈1

Tab + Tba

• The two states are created by positive feedback.

• Ta and Tb are usually determined by the charging and discharging of timing capacitors,while Tab and Tba are the transient response of the circuit.

• Comparing with the frequency-tuned oscillators, the relaxation oscillators have widertuning range, predictable waveforms, but poorer spectral purity.


Constant-Current Charge/Discharge Oscillators

VA

VBT1 T2

Vo

VA

VBVo

I1

I2

R

SQ

D x

Schmitt Trigger

D

DC

VDD

T1 =C · (VA − VB)

I1T2 =

C · (VA − VB)

I2 − I1

fo =1

T1 + T2=

I1

C · (VA − VB)

(1 −

I1

I2

)


The Banu Oscillator

IB

Vx Vy

Va

Vb

Vx

Vy

Va

VDD

Vth

Vb

CC

VDD

• Oscillation frequency is fo = 1/(2T ) where T = C · (VDD − Vth)/IB.

• Reference: Banu, M., “MOS Oscillators with Multi-Decade Tuning Range and GHzMaximum Speed,” JSSC, 12/1998, pp. 1386–1393.


A CMOS Relaxation Oscillator

V 1

V 3

V 2 T 1

T 2

V DD

V DDV x

V DD

V x V DDV i

V o

V 1 V 2 V 3

VDD VDD

0 tR C

V1(t) = 0 + (Vx + VDD − 0)e−t/(RC) ⇒ T1 = RC lnVx + VDD

Vx

V1(t) = VDD + (Vx − VDD − VDD)e−t/(RC) ⇒ T2 = RC ln2VDD − Vx

VDD − Vx



Vc1

Vc2

Ve1

Vx

Ve1 Ve2

Vc2Vc1

Vx Ve2

R1

I 1

R2

I 2

VCCV CC

V CC V BE(on)

V CC V BE(on )2

V CC

V BE(on)

V BE(on)

T 2

T 1

V CC

V CC V BE(on )2

V i

Q1

Q3

D1

Q2

Q4

D2

C

Q2 OnQ1 Off Q1 On

Q2 Off

V BE(on)

0



• Q1, Q2, Q3, and Q4 are never saturated.

• D1 and D2 act as voltage clamps. Thus the maximum voltage across R1 and R2 areVBE (on).

• The relaxation times are

T1 =C · 2VBE (on)

I1T2 =

C · 2VBE (on)

I2

• If I1 = I2 = I , the frequency of oscillation is

fo =1

T1 + T2=

14· I

C · VBE (on)


Fundamentals of Analog Filters

Jieh-Tsorng Wu

July 16, 2002

A

1896


Filters

Xi

Xi

Xi

Xo

Xo

Xo(t)

(t)

(t)

(t)

(t)

(t)

FilterReconstructionAnti−Aliasing

Filter

Continuous Analog Filter

H(s)

Sampled Data Filter

Digital Filter

H(z)

H(z)D/AA/D

Filters 20-2 Analog ICs; Jieh-Tsorng Wu

Filters

Continuous-Time Analog Filters

• Differential equations.

• Laplace transforms. s = jω

Discrete-Time (Sampled-Data) Analog Filters

• Difference equations.

• Z-transform; z−1 is unit delay operator. z = ejωTs; Ts is sampling period.

Discrete-Time (Sampled-Data) Digital Filters

• Discrete-time systems.

• A/D introduces quantization noise.


Low-Pass Filter Specifications

PB Ripple

SB Attenuation

A

TB

PBSB

|H(jω)| (dB)

ωωc ωs


High-Pass Filter Specifications

PB Ripple

PBSB

SB Attenuation

A

TB

|H(jω)| (dB)

ωωcωs


Band-Pass Filter Specifications

SB L SB H

A

PB

|H(jω)| (dB)

ωωcL ωcH

ωsL ωsH


Band-Reject Filter Specifications

PB HPB L

A

SB

|H(jω)| (dB)

ωωcL ωcH

ωsL ωsH



jω

σ

H(s) =a2s

2 + a1s + a0

s2 + b1s + b0

=a2(s − z1)(s − z2)

(s − p1)(s − p2)

= K ·s

2 + (ωz/Qz)s +ω2z

s2 + (ωp/Qp)s +ω2p

ωp = Pole Frequency = |p1| = |p2| ωz = Zero Frequency = |z1| = |z2|

Qp = Pole Quality Factor =ωp

2Re(p1)Qz = Zero Quality Factor =

ωz

2Re(z1)



• For complex poles and zeros, z2 = z∗1 and p2 = p

∗1.

• H(0) = Kω2z/ω

2p and H(∞) = K .

• |H(jω)| is maximum, at ω ≈ ωp.

• The sharpness of the maximum is determined by Qp.

• |H(jω)| is minimum, at ω ≈ ωz.

• The depth of the minimum is determined by Qz.


Second-Order Low-Pass (LP) Filter

M

K

jω

σ

ωM

ω

|H(jω)|

H(s) =Kω

2p


ωM = ωp ·√

1 − 1/(2Q2) M =KQ√

1 − 1/(4Q2)


Second-Order High-Pass (HP) Filter

M

K

jω

σ

ωM

ω

|H(jω)|

H(s) =Ks

2


ωM =ωp√

1 − 1/(2Q2)M =

KQ√1 − 1/(4Q2)


Second-Order Band-Pass (BP) Filter

jω

σ

ωp

ω

K

K/√

2

|H(jω)|

H(s) =K (ωp/Qp)s


3 dB Bandwidth =ωp

Qp


Second-Order Band-Reject (BR) Filter — Low-Pass Notch (LPN)

K

M

jω

σ

ω

|H(jω)|

ωM ωz

H(s) =K (s2 +ω

2z)


ωz > ωp


Second-Order Band-Reject (BR) Filter — High-Pass Notch (HPN)

K

M

jω

σ

ω

|H(jω)|

ωz ωM

H(s) =K (s2 +ω

2z)


ωz < ωp


Second-Order Band-Reject (BR) Filter — Symmetrical Notch

jω

σ

ω

|H(jω)|

ωz = ωp

K

K/√

2

H(s) =K (s2 +ω

2z)


ωz = ωp

3 dB Notch Width =ωp

Qp



0

360

180

jω

σ

ωωp

|H(jω)| ∠H(jω)



H(s) = K ·s

2 − (ωp/Qp)s +ω2p


|H(jω)| = K

φ(ωn) = −2 tan−1ωn/Qp

1 −ω2n

ωn =ω

ωp

Group Delay = τ = −dφ(ω)

dωτn(ωn) = ωpτ(ωn) =

2Qp

·1 +ω

2n

(1 −ω2n)2 + (ωn/Qp)2

• For Qp = 1/√

3, the delay curve is maximally flat.

• For Qp > 1/√

3, τ has a peaking, τn,max ≈ 4Qp/ωp at ωn ≈√

1 − 1/(4Q2p).

• For 2nd-order filters,

τn,(LP,HP,BP,BR)(ωn) =12τn,AP (ωn)



1 1

1

1

jω

σ

ωωs

|H(jω)|2

1/(1 + ε2)

1/(1 + δ2)

|H(jω)|2 =1

1 + ε2ω2N

Poles = sk = ε−1/N · exp(j2k +N − 1

2Nπ

)k = 1,2, · · · , N



The relationship between the filter order, N, and the steepness of the magnituderesponse is

N ≥logδ − logε

logωs

• Good flatness in passband.

• Poor phase linearity.

• Moderate attenuation slope steepness.



1

1

N=3

N=4

1

1

Chebyshev Inverse Chebyshev

ωωωsωs

|H1(jω)|2 |H2(jω)|2

1/(1 + ε2)

1/(1 + δ2)

Chebyshev = |H1(jω)|2 =1

1 + ε2C2N

(ω)

Inverse Chebyshev = |H2(jω)|2 =ε

2C

2N(1/ω)

1 + ε2C2N

(1/ω)



The function CN is

CN(ω) = cos[N cos−1(ω)] for ω ≤ 1

= cosh[N cosh−1(ω)] for ω > 1

= 2ωCN−1(ω) − CN−2(ω)

The relationship between the filter order, N, and the steepness of the magnituderesponse is

N ≥cosh−1(δ/ε)

cosh−1 ωs

≈ln(2δ/ε)

ln(ωs +

√ω2

s − 1)

• Good steepness of the attenuation slope.

• Poorer phase linearity and passband flatness than the Butterworth filters.

• Inverse Chebyshev filters have better phase and delay performance.



1

1ω

ωs

|H(jω)|2

1/(1 + ε2)

1/(1 + δ2)

|H(jω)|2 =1

1 + ε2R2N

(ω)



The function RN is

RN(ω) = k

N/2∏i=1

ω2 − (ωs/ωzi)

2

ω2 −ω2zi

for N even

= kω

(N−1)/2∏i=1

ω2 − (ωs/ωzi)

2

ω2 −ω2zi

for N odd

In the stopband, if ε2R

2N(ω) 1,

20 logδ

ε≈ 20 log |RN(ωs)|

• Best steepness of the attenuation slope.

• Poor phase linearity.


Comparison of the Classical Filter Responses

Comparing filters that satisfy the same δ and ε requirements:

• The Cauer filter has the lowest order, while the Butterworth filter has the highest order.

• The Butterworth filter has the best passband performance, and the inverseChebyshev filter is a close second.

• The Cauer filter has the largest pole quality factor; next is the Chebyshev filter,followed by the inverse Chebyshev and the Butterworth filters.

• The Chebyshev filter has the worst group delay variation; next is the inverseChebyshev filter, followed by the Butterworth and the Cauer filters.

• The Butterworth and the Chebyshev are all-pole filter, while the inverse Chebyshevand Cauer filters have finite transmission zeros.

• The inverse Chebyshev filters have low order, modest Q values, good delayperformance, and minimal passband attenuation, making them most attractive.


Linear-Phase (Bessel-Thomson) Filters

1

1ω

ωs

|H(jω)|2

1/(1 + ε2)

1/(1 + δ2)

H(s) =bo

D(s)D(s) =

N∑i=0

bisi bi =

(2N − i )!

2N−i i !(N − i )!i = 0,1, · · · , N − 1

D(s) is related to Bessel polynomials.

D(s) = (2N − 1)DN−1 + s2DN−2


Linear-Phase (Bessel or Thomson) Filters

• Approximate the linear-phase response.

• Poor steepness of the attenuation slope.

• It is usually more efficient to use a Butterworth, Chebyshev or a Cauer filter cascadedwith an all-pass filter to achieve required gain and linear-phase response.


All-Pass Filter (Delay Equalizer) Specifications

1

PB

|H(jω)| (dB)

ωωcL ωcH

jω

σ

H(jω) = |H(jω)|ejφ(ω)

Group Delay = τ(ω) = −dφ(ω)

dω



Low-Pass to High-Pass Transformation

HHP(s) = HLP

(1s

)

• For RC active filters, it is an RC-CR transformation.

Low-Pass to Band-Pass Transformation

HBP(s) = HLP

(Q · s

2 + 1s

)

• Q = ωo/B is the quality factor, where ωo is the center frequency, B = ωcH − ωcL isthe passband bandwidth.

• Transformation always results in symmetrical band-pass filters.



Low-Pass to Band-Reject Transformation

HBR(s) = HLP

(1Q· s

s2 + 1

)

• Q = ωo/B is the quality factor, where ωo is the center frequency, B = ωsH −ωsL is thepassband bandwidth.

• Transformation always results in symmetrical band-reject filters.

Frequency ScalingH ′(s) = H(

s

a)

• So that ω′c = a ·ωc, ω′s = a ·ωs, ω′o = a ·ωo


High-Order Filters

H1 H2 H3 H4

H1 H2 H4H3

H2H1 H3 H4

In Out

Cascade Topology

Follow-the-Leader Feedback (FLF) Topology

F1 F2 F3 F4

In Out

In Out

F2 F4

F3 F5

H5

Leapfrog (LF) Topology


High-Order Filters

Cascade Topology:H(s) = H1 · H2 · H3 · H4

Follow-the-Leader Feedback (FLF) Topology:

H(s) =H1H2H3H4

1 + F1H1 + F2H1H2 + F3H1H2H3 + F4H1H2H3H4

Leapfrog Topology:

H(s) =H1H2H3H4H5

D(s)

D(s) = 1 + F2H1H2 + F3H2H3 + F4H4H4 + F5H4H5

+F2F4H1H2H3H4 + F2F5H1H2H4H5 + F3F5H2H3H4H5


LC Ladder Filters

RS

RS

V 1

V S

V S

RL

V 2

RL

V 2V 1

I 1

A Fifth-Order Elliptic Low-Pass Filter

Lossless LC Network

Y2

Z3

Y4

Z(n-2)

Y(n-1)

Z(n)Z1


LC Ladder Filters

When designed for maximum power transfer, the LC ladder filters are inherentlyinsensitive to component variations, particularly in their passband.

Input Power = P1 = |I1(jω)|2ReZin(jω) =|VS |

2

|RS + Zin(jω)|2ReZin(jω)

Maximum Input Power = P1,max =14

|VS |2

RS

Output Power = P2 =|V2|

2

RL

H(s) =

√4RS

RL

·V2

VS=

N(s)

D(s)|H(jω)|2 =

4RS

RL

·∣∣∣∣V2

VS

∣∣∣∣2

≤ 1

|H(jω)|2 = 1 −∣∣∣∣RS − Zin(jω)

RS + Zin(jω)

∣∣∣∣2

= 1 − |ρ(jω)|2 ρ(s) = ±RS − Zin(s)

(RS + Zin(s))

• ρ(s) is the reflection coefficient.


Sensitivity

Let P is a function of x. The sensitivity of P with respect to x is defined as:

SPx =

∂P/P

dx/x=

x

P· ∂P∂x

=∂(ln P )

∂(lnx)

The semirelative sensitivity is defined as

QPx =

∂P

∂x/x= x · ∂P

∂x

• Some useful relationships:

SP1P2x = S

P1x + S

P2x S

P1/P2x = S

P1x − S

P2x SP

x = SPy · S

yx


Sensitivity

• Let Y is a function of x1, x2, · · · , xn.

dY =∂Y

∂x1· dx1 +

∂Y

∂x2· dx2 + · · · +

∂Y

∂xn

· dxn

d Y

Y= SY

x1·dx1

x1+ SY

x2·dx2

x2+ · · · + SY

xn·dxn

xn

• Let the forward gain T = T1 · T2, we have

STT2=

T2

T· ∂T∂T2

= 1

With negative feedback factor H , we have

T =T1T2

1 + HT1T2⇒ ST

T2=

T2

T· ∂T∂T2

=1

1 + HT1T2

The T sensitivity is reduced by the loop gain HT1T2



Let the transfer function be

H(s) =N(s)

D(s)=

amsm + · · · + a1s + a0

bnsn + · · · + b1s + b0

= K ·(s − z1)(s − zi) · · · (s − zm)

(s − p1)(s − p2) · · · (s − zn)

The sensitivity is

SHx = SN

x − SDx =

∂ lnN

∂ lnx− ∂ lnD

∂ lnx

= SKx + x

∂

∂x[ln(s − z1) + · · · + ln(s − zm)] − [ln(s − p1) + · · · + ln(s − pn)]

= SKx −

x

∂z1∂x

s − z1+ · · · +

x∂zm∂x

s − zm

+

x

∂p1∂x

s − p1+ · · · +

x∂pn∂x

s − pn

= SKx −[z1S

z1x

s − z1+ · · · +

zmSzmx

s − zm

]+

[p1S

p1x

s − p1+ · · · +

pnSpnx

s − pn

]



• Any pole or zero shift influences H(s) most strongly in the neighborhood of that poleor zero.

• SHx →∞ at a jω-axis transmission zero zi = jωzi

.

• For frequencies s = jω in the neighborhood of pole with large quality factor, highsensitivities are expected.

• Sensitivities are normally largest at the passband corner.



The Biquadratic function is

H(s) =N(s)

D(s)=

a2(s − z1)(s − z2)

(s − p1)(s − p2)=

a2s2 + a1s + a0


p1 = −ωp

(1

2Qp

− j

√1 − 1

4Q2p

)p2 = p∗1 = −ωp

(1

2Qp

+ j

√1 − 1

4Q2p

)

The sensitivity of the poles are

Sp1x = S

ωp

x − jS

Qp

x√4Q2

p − 1S

p2x =

(S

p1x

)∗= S

ωp

x + jS

Qp

x√4Q2

p − 1

• The pole is√

4Q2p − 1 ≈ 2Qp times more sensitive to variations in ωp than to variations

in Qp.



The transfer function can be expressed as H(jω) = |H(jω)|ejθ(ω), then

SH(jω)x =

∂ lnH(jω)

∂ lnx=

∂ ln |H(jω)|∂ lnx

+ jx∂θ(ω)

∂x= S

|H(jω)|x + jθ(ω)Sθ(ω)

x

Consider only the effects of poles on the passband of H(s)

SH(s)x = − x

D(s)

∂D(s)

∂x= −

(sωp

Qp+ 2ω2

p

)S

ωp

x −sωp

QpS

Qp

x


= −

(snQp

+ 2)S

ωp

x −snQpS

Qp

x

s2n + sn/Qp + 1

SH(jω)x = −

[(ωn

Qp

)2+ 2(

1 −ω2n

)]S

ωp

x −(ωn

Qp

)2S

Qp

x

(1 −ω2

n

)2+(ωn/Qp

)2+ j

ωn

Qp

(1 +ω

2n

)S

ωp

x +(

1 −ω2n

)S

Qp

x(1 −ω2

n

)2+(ωn/Qp

)2

sn =s

ωp

ωn =ω

ωp



We have

S|H(jω)|x = −

2(

1 −ω2n

)2+(ωn/Qp

)2

(1 −ω2

n

)2+(ωn/Qp

)2· Sωp

x +

(ωn/Qp

)2

(1 −ω2

n

)2+(ωn/Qp

)2· SQp

x

θ(ω)Sθ(ω)x = x

∂θ(ω)

∂x=

(1 +ω

2n

)2 (ωn/Qp

)(1 −ω2

n

)2+(ωn/Qp

)2· Sωp

x +

(1 −ω

2n

)2 (ωn/Qp

)(1 −ω2

n

)2+(ωn/Qp

)2· SQp

x

And

S|H(jω)|x = S

|H |ωp· Sωp

x + S|H |Qp· SQp

x

⇒ S|H |ωp

= −2(

1 −ω2n

)2+(ωn/Qp

)2

(1 −ω2

n

)2+(ωn/Qp

)2S|H |Qp

=

(ωn/Qp

)2

(1 −ω2

n

)2+(ωn/Qp

)2



S|H |ωp

S|H |Qp

maxS |H |ωp ≈

Qp

1 + 1/Qp

at ωn ≈ 1 +1

2Qp

minS |H |ωp ≈ −

Qp

1 − 1/Qp

at ωn ≈ 1 − 12Qp

maxS |H |Qp = 1 at ωn = 1



• Small variations of ωp are far more important than small change in Qp.

• Since the errors increase with Q, low-Q filters are easier to design with less accuratecomponents than high-Q filters.

• Sensitivities are strong functions of frequency, and the passband edges are verycritical.


High-Order Filter Sensitivity

A 6th-order Butterworth bandpass filter

• For cascade design,

H(s) = H1(s)H2(s) · · ·Hn(s)

SH(s)Hj (s) = 1 and S

H(s)x = S

Hj (s)x

The sensitivity of H(s) to x is as large assensitivity of sub-block Hj(s) to x.

• Feedback paths around low-order sectionsin a multiple-feedback (MF) filter topologycan reduce sensitivities in the passband.In the stopbands, where feedback pathslose their effectiveness, MF and cascadesensitivities are approximately the same.


Active-RC Filters

Jieh-Tsorng Wu

October 17, 2002

A

1896


Capacitor Integrators

oV

R CI

Vo

I=

1jωC + G

=1

jωC[1 − j G

ωC

] = 1

jωC[1 − j 1

QI (ω)

]QI(ω) =

ωC

G

The transfer function of an integrator can be expressed as

H(jω) =1

F (jω)=

1j Im[F (jω)] + Re[F (jω)]

=1

jωτ + q=

1

jωτ[1 − j 1

QI (ω)

]QI(ω) =

Im[F (jω)]

Re[F (jω)]=

ωτ

q

• QI is the quality factor of the integrator.

• For an ideal integrator, QI →∞ and q→ 0.

Active-RC Filters 21-2 Analog ICs; Jieh-Tsorng Wu

Active-RC Inverting Integrators

VoVi

C

A(s)

RVo

Vi(s) = − 1

sRC· 1

1 + 1A(s)

[1 + 1

sRC

]

Let A(s) = ωu/s, then

Vo

Vi(s) = − 1

sRC· 1

1 + s/ωu + 1/(ωuRC)≈ − 1

sRC· 1

1 + s/ωu

if ωu1RC

Vo

Vi(jω) = − 1

jωRC −ω2RC/ωu

= − 1jωτ + q

τ = RC q = −ω2RC

ωu

= − ωRC

|A(jω)|QI =

ωτ

q= −

ωu

ω= −|A(jω)|



VVi oA1

A2

C

R

Vo

Vi(s) = − 1

sRC

1+1/A2(s)+ 1+sRC

A1(s)

≈ − 1

sRC

(1 − 1

A2(s) +1

A22(s)− 1

A32(s)

+ · · ·)+ 1+sRC

A1(s)

Let A1(s) = ωu1/s, and A2(s) = ωu2/s,

Vo

Vi(jω) ≈ − 1

jωRC

(1 − jω

ωu2− ω2

ω2u2

+ jω3

ω3u2

+ · · ·)− ω2RC−jω

ωu1

≈ − 1

jωRC

(1 + 1

ωu1RC− ω2

ω2u2

)+ ω2RC

ωu2

(1 − ω2

ω2u2

− ωu2ωu1

)



Thus

τ ≈ RC q =ω

2RC

ωu2

(1 − ω

2

ω2u2

−ωu2

ωu1

)≈ ωRC

|A2(jω)|

(1 −

ωu2

ωu1

)

⇒ QI =ωτ

q=|A2(jω)|1 − ωu2

ωu1

If A1(s) = A2(s) = A(s) = ωu/s, then

τ ≈ RC q = −ω4RC

ω3u

= − ωRC

|A(jω)|3

⇒ QI = −(ω

ωu

)3

= −|A(jω)|3


Noninverting Integrator

Vi Voi VV o

R1

1

A

R

2

1

A2

R

1R

A1 A1

C

R

C

R

Let A1 = A2 = A

Vo

Vi=

1sRC

· 1

1 + 3A+ 1

sRCA+ 2

A2 +2

sRCA2

QI = −13|A(jω)|

Let A1 = A2 = A

Vo

Vi=

1sRC

· 1

1 + 1A+ 1

sRCA

QI = −|A(jω)|


Phase-Lead Noninverting Integrator

Vi V

1R

o

1R

C

A

2A

1

R

Vo

Vi(s) =

1

sRC[

11+2/A2(s)

+ 1A1(s) +

1sR1CA1(s)

]

If A1(s) = A2(s) = A(s) = ωu/s, then

QI ≈ +ωu

ω= +|A(jω)|


First-Order Filters

V oV

1sτ

i

oViViV

iV oV

V

i

1C

1C

1

R2

R

R

1R

2

R1

1C

C

C

Fully-Differential Active-RC Filter

C

R2Active-RC Filter

State-Variable Topology

1

α1s + α0

Vo

Vi= −

α1s + α0

sτ + 1= −±sC1 + G1

sC + G2= −

R2

R1·±sR1C1 + 1

sR2C + 1


Single-Amplifier 2nd-Order Filters —Sallen-Key LP Biquad

oo VViV Vi

(1-a)

a

2

1

C

C1

G2

RA

C

AR

G G1

R G1

2

B

G

1

C

BR

2AA

H(s) =Vo

Vi=

KG1G21

1+K/A

s2C1C2 + s[C2(G1 + G2) + C1C2

(1 − K 1

1+K/A

)]+ G1G2

K = a ·(

1 +RB

RA

)a ≤ 1



Let A =∞ and C1 = C2 = C, then

H(s) =KG1G2/C

2

s2 + s[G1 + G2(2 − k)]/C + G1G2/C2= K ·

ω2p

s2 + sωp/Q +ω2p

ω2p =

G1G2

C2Q =

√G1G2

G1 + G2(2 − K )K = a ·

(1 +

RB

RA

)

If a = 1, R1 = R2 = R, we have

ωp =1RC

Q =1

3 − KSQK= 3Q − 1

• Minimal use of opamp, at the expense of more passive components.

• Sensitive to parasitic capacitors.

• Widely used to realize the on-chip anti-aliasing and reconstruction filters.



Let a = 1, R1 = R2 = R, C1 = C2 = C, A = ωu/s,

H ′(s) = K ·ω

2p

11+K/A

s2 + sωp

(3 − K 1

1+K/A

)+ω2

p

≈ K ·ω

2p(1 − K/A)

s2 + sωp

[3 − K (1 − K/A)

]+ω2

p

⇒ H ′(s) ≈ K ·ω

2p(1 − sK/ωu)

s2(1 + ε) + sωp(3 − K ) +ω2p

= K ·ω′p

2(1 − K/ωu)

s2 + sω′p/Q′ +ω′p

2

ω′p =ωp√

1 + ε≈ ωp

(1 − ε

2

)= ωp − ∆ωp Q′ = Q

√1 + ε ≈ Q

(1 +

ε

2

)= Q + ∆Q

ε =ωp

ωu

K 2 =K

2

|A(jωp)|

• H′(s) has an additional positive zero at ωu/K .

• The Sallen-Key biquad is a good low-Q LP filter with small ωu-caused deviations.



1sτ

1sτV

V VlK

h Vbi

1

1/Q

Vh

Vi= +K · s

2

s2 + s/(Qτ) + 1/τ2= K · s

2

s2 + sωp/Q +ω2p

Vb

Vi= −K ·

s/τ

s2 + s/(Qτ) + 1/τ2= −K ·

sωp

s2 + sωp/Q +ω2p

Vl

Vi= −K ·

1/τ2

s2 + s/(Qτ) + 1/τ2= −K ·

ω2p

s2 + sωp/Q +ω2p

ωp =1√τ1τ2

=1τ



For integrators with finite quality factors, let

− 1sτ→ − 1

τ(sα1 + σ1)+

1sτ→ +

1τ(sα2 + σ2)

The new ωp and Q are

ω′p2 =

ω2p

α1α2

(1 +

1Q·σ2

ωp

+σ1σ2

ω2p

)

Q′ =ω′p

ωp

· Q

α2 +Q · α2σ1+α1σ2ωp



lVVi

bV

A1

R/K

A2 A3

C

R

RQC

R Rx

Rx

Vb

Vi= −K ·

ωps

s2 + sωp/Q +ω2p

Vl

Vi= −K ·

ω2p

s2 + sωp/Q +ω2p

ω =1RC

The sensitivities for any passive component x are

Sωp

x = −1/2∣∣SQ

x

∣∣ ≤ 1



Let A1 = ωu1/s, A2 = ωu2/s, and A3 = ωu3/s, then

− 1sτ→ − 1

τ(sα1 + σ1)α1 = 1 +

ωp

ωu1

(1 + K +

1Q

)σ1 = − ω

2

ωu1

+1sτ→ +

1τ(sα2 + σ2)

α2 = 1 +ωp

ωu2σ2 = − ω

2

ωu2− 2

ω2

ωu3

Assuming matched opamps and ωp ωu, we have

ω′p −ωp

ωp

=∆ωp

ωp

≈ −2 + K

2·ωp

ωu

= −2 + K

2· 1

|A(jωp)|Q′

Q≈ 1

1 − 4Q · ωp

ωu

← Q Enhancement



l

Rx

R

Vi

Vb

V

x

3

C

A

2A

R

A1

R/K C

RQ

R

Let A1 = ωu1/s, A2 = ωu2/s, and A3 = ωu3/s, then

− 1sτ→ − 1

τ(sα1 + σ1)+

1sτ→ +

1τ(sα2 + σ2)



where

α1 = 1 +ωp

ωu1

(1 + K +

1Q

)σ1 = − ω

2

ωu1α2 = 1 +

ωp

ωu2σ2 = +

(2ω2

ωu3− ω

2

ωu2

)

If Q 1, we have

ω′p −ωp

ωp

=∆ωp

ωp

≈ −12

[(1 + K )

ωp

ωu1+

ωp

ωu2

]Q′

Q≈

1 + ∆ωp/ωp

1 +ωp

ωu2+Q · D

D =2ωp

ωu3−

ωp

ωu1−

ωp

ωu2−

ω2p

ωu1ωu2+ω

2p(1 + K )

ωu1

(2

ωu3− 1ωu2

)

For matched opamps, we have

Q′

Q≈

1 −(1 + K

2

) ωp

ωu

1 +ωp

ωu+QK

(ωp

ωu

)2


Arbitrary Transmission Zeros by Summing

1sτ

1sτ

V

VVl

Vh

b

1

a

Vi

2

oa0

1

a

K

1/Q

Vo

Vi= a0 +

−a1 · Ksωp − a2 · Kω2p

s2 + sωp/Q +ω2p

=a0s

2 + s(ωp/Q)[a0 − a1(KQ)] +ω2p[a0 − a2K ]

s2 + sωp/Q +ω2p


Arbitrary Transmission Zeros by Voltage Feedforward

R/b

R/c

aC

o2

Vo1

x

V

R

Vi

Rx

3

C

A

2A

R

A1

C

RQ

RR/K

Vo1

Vi= −

as2 + sωp(K − b) + cω

2p

s2 + sωp/Q +ω2p



Vi VoVo,1 Vo,2

(s)T1 (s)T2 (s)Tn

m

M

Passbandjω

σ

ω

|t(jω)|

ωL ωU

ωmin ωmax



• Each stage is a biquad, i.e,

Ti(s) = ki ·a2,is

2 + a1,is + a0,i

s2 + sωp,i/Qp,i +ω2p,i

= ki · ti(s) |ti(jωp,i)| = 1

ki is defined as gain constant, such that |ti(jωp,i)| = 1.

• No interaction between stages, therefore

H(s) =Vo(s)

Vi(s)= T1(s) · T2(s) · T3(s) · · · =

n∏i=1

Ti(s) =n∏

i=1

kiti(s)

• Easy to tune.

• Sensitive to component variation in the passband for high-order filter, e.g., order > 8.



To maximize dynamic range want

max|Vo,i | < Vo,max 0 ≤ ω <∞ and min|Vo,i | → max ωL ≤ ω ≤ ωU

Vo,i(s) = Vi(s) ·i∏

j=1

Tj(s) = Vi(s) · Hi(s) Hi(s) =i∏

j=1

Tj(s) i = 1, · · · , n

• Vo,max is the maximum undistorted signal level, which is limited by power supply or bythe slew rate of the opamps.

• Large signal even outside the passband must not overload the opamps.

• Signal-to-noise ratio is of no interest in the stopband.



1. Pole-Zero Pairing. Every |ti(jω)| should be as flat as possible in the ω of interest, i.e.,

max

logM(ti)

m(ti)

← Minimize i = 1, · · · , n

• A good suboptimal solution is assigning each zero or zero pair to the closest pole.

2. Section Ordering. Every |Vo,i(jω)| or |Hi(jω)| should be as flat as possible in the ω ofinterest, i.e.,

max

logM(Hi)

m(Hi)

← Minimize i = 1, · · · , n

• The section sequence in the order of increasing Qp is often close to the optimum.

• It is often desirable to have a low-pass or bandpass biquad as the first section tominimize slew-rate problem.

• If possible, employ a high-pass or band-pass biquad as the last section to eliminatelow-frequency noise and dc offset.



3. Gain Assignment. Every Vo,i should be as large as possible, i.e.,

M(Vo,1) = M(Vo,2) = · · · = M(Vo)

Since

Hi(s) =i∏

j=1

kiti(s) =i∏

j=1

ki

i∏j=1

ti(s) Ki =i∏

j=1

kj Mi = max

∣∣∣∣∣∣i∏

j=1

tj(jω)

∣∣∣∣∣∣Filter Specification → H(s) = Hn(s) → K = Kn M = Mn

We have

Ki ·Mi = Kn ·Mn = K ·M i = 1, · · · , n − 1

⇒ k1 = K · MM1

and ki =Mi−1

Mi

i = 2, · · · , n − 1


High-Order Filter Using the Follow-the-Leader Feedback Topology

0

(s)T

i

nV2V1

Vi

Vo

(s)T1

V

2 (s)Tn

V

R

RF,n

RF,2

F,1R

RF,0

R

R

R

R

RA

o,0

o,1

o,2

o,n



RS

RS

V 1

V S

V S

RL

V 2

RL

V 2V 1

I 1

A Fifth-Order Elliptic Low-Pass Filter

Lossless LC Network

Y2

Z3

Y4

Z(n-2)

Y(n-1)

Z(n)Z1



• Minimum passband sensitivity to component tolerances.

• Can be implemented with

– Element substitution.– Operational simulation with signal-flow graph.

• Requires more opamps than the cascade and MF methods.


LC Ladder SimulationRS

V SRL

V k-1 V k

kZY k-1 Y k+1 Z k+2Z k-2

kZ

I k+1

V k

I k+3

Y 2 Y 4

V k+1I k IVIk-2V k-2 k+2 k+2

I k+1I k-1

I k-1

VV k-2 k+2

Y k+1k-2Z k-1Y k+2Z

1Z 3Z nZn-2Z

Y n-1


LC Ladder Simulation

I k+1

V k

I k+3

k-2Z Y k-1 kZ Y k+1 k+2Z

k-2Z Y k-1 kZ Y k+1

I k-1

VV k-2 k+2

Leapfrog (LF) Topology



RL

V 1

RSV in

V 2V 0

V 1

V 4

V 5V 3

V in V out

V in V 2

V 1

V 4

V outV 5

S C11+sR

SR

I 0 I 2 I 4 V 5V 3

C1L2

C3 C5L4

I 6

1/(sL L

V 6

S1/R 1/(sL2) -1/(sC 3) 4) -1/(sC 5) 1/R-1/(sC )1

S1/R

L C51+sR

LR

V out



V out

C1RS

RS

V 1

V in

V 2

V 5

V 4

V 3

L2 L4

C3

1

1 1

R CL 5

11

1 11

• Component scaling can be done by maintaining the RC values.

• Use both lossless and lossy integrators.

• Combining the phase-lag Miller inverting integrator with the phase-lead noninvertingintegrator can reduce phase errors.


Signal-Level Scaling in Ladder Filters

T3

1/

1/

(s)T1

V1V

V’0

2

(s)T0

V0

1/ 1V’

2

(s)T2

V2

3

(s)T3

VoV3K0

Vi

3V’

1V’

(s)T1

1

(s)

ViK1

T(s)T0

3 o

2

2 (s)

α α

α αα

α

Vj = Hj(s) · Vj−1 V ′j= αjHj(s) · V ′

j−1 ⇒ V ′j= Vj · αj ·

V′j−1

Vj−1

• The signal level of Vj can be scaled by αj .

• Signal-level scaling is to maximize dynamic range. Want

max|Vj(jω)| = Vo,max for j = 0, · · · , n 0 < ω <∞

• Scale Vj sequentially from j = 1 to j = n.


General Ladder BranchesShunt Branch

1I 3I

2

V

3L

4C

2L1CR0

2

I

3C1LR0

4L

V1 V3

Series Branch

C2

For the series branch

I2 = (V1 − V3) · Y (s) = (V1 − V3) · 1

R0 + sL1 +1

sC2+ 1

sC3+1

sL4

For the shunt branch

V2 = (I1 − I3) · Z(s) = (I1 − I3) · 1

G0 + sC1 +1

sL2+ 1

sL3+1

sC4


General Ladder Branches by Active-RC Implementation

4C

Rb

1C

R0

2C

3C

2V3V

aRV1

R=1

R=1

R=1

R=1 R=1

R=1

V2 = −(V1

Ra

−V3

Rb

)· 1

G0 + sC1 +1

sC2+ 1

sC3+1

sC4


Finite Transmission Zeros in the Series Branches

V3

1

1111

1 11

s

2

V

V1 V3I0 I4

C1 C3C2

L2

1

V0V

3C 2C1C 2C 2L

2C 2

I0 I4V1 V3I2

L2

C2V3s C2V1

C2C

C

C2C3

4

1

V

I0 = sC1V1 + (sC2 + Y2)(V1 − V3) = s(C1 + C2)V1 − sC2V3 − Y2(V1 − V3)

I4 = (sC2 + Y2)(V1 − V3) − sC3V3 = Y2(V1 − V3) + sC2V1 − s(C2 + C3)V3


MOST-C and Gm-C Filters

Jieh-Tsorng Wu

July 16, 2002

A

1896



Operating RangeAllowalbe

VB

VDV SV

DI

BVVQ

VKVG

0

VG VF B = Flat-Band Voltage

φ0 = Surface Band Bending ≈ 2φf

γ = Body Effect Coefficient

k = µCox

W

L

VK = VF B +φ0 −γ

2

2+ γ

√VGB − VF B +

γ2

4VQ← Model Accuracy Consideration

ID

k= (VGB − VF B −φ0)(VDB − VSB) − 1

2

(V 2DB− V 2

SB

)− 2

3γ[(VDB +φ0)

32 − (VSB +φ0)

32

]= (VGB − VF B −φ0)VDS − [f (VDB) − f (VSB)]

f (VXB) =12V 2XB

+23γ(VXB +φ0)

32 =

12

(VX0 + V0B)2 +23γ(VX0 + V0B +φ0)

32

Gm-C Filters 22-2 Analog ICs; Jieh-Tsorng Wu


Using Taylor’s series

f (VXB) ≈(

12V 2

0B + V0B · VX0 +12V 2X0

)+

23γ(V0B +φ0)

32 + γ(V0B +φ0)

12 · VX0

+14γ(V0B +φ0)−

12 · V 2

X0 −1

24γ(V0B +φ0)−

32 · V 3

X0 + · · ·

We have

ID

k= (VG0 − VT )VDS −

[g(VD0) − g(VS0)

]VT = VF B +φ0 + γ(V0B +φ0)

12

g(VX0) = ge(VX0) + go(VX0) ge(−VX0) = ge(VX0) go(−VX0) = −ge(VX0)

ge(VX0) =12· V 2

X0 +14γ(V0B +φ0)−

12 · V 2

X0 + · · ·

go(VX0) = − 124

γ(V0B +φ0)−32 · V 3

X0 + · · ·



Thus

ID = IL − IN IL = k(VG0 − VT ) × VDS = G × VDS IN = k[g(VD0) − g(VS0)

]• Both ge and go are independent of VG.

• go(VD0) − go(VS0) is very small comparing to IL (e.g., 0.1 percent of it or less).

• ge(VD0) − ge(VS0) can be large and its effect must be eliminated to obtain a linearresistor.

• If only IL is considered, the resistance between VD and VS is

G =ID

VDS

= k(VG0 − VT ) = µCox

W

L(VG0 − VT )



G

o2V

o1V

V

GV

0Vi2V

i1Vi VV o

I1

I2

C

R

C

C

M2

M1

Vi1 = +Vi

2+ V0 Vi2 = −

Vi

2+ V0 Vo1 = +

Vo

2+ V0 Vo2 = −

Vo

2+ V0

I1 = G ×(+Vi

2

)−[ge

(+Vi

2

)− ge (0)

]−[go

(+Vi

2

)− go (0)

]

I2 = G ×(−Vi

2

)−[ge

(−Vi

2

)− ge (0)

]−[go

(−Vi

2

)− go (0)

]

I1 − I2 = G × Vi − 2go

(Vi

2

)≈ G × Vi G = k(VG − V0 − VT )



Therefore

Vo(s)

Vi(s)=

I1(s) − I2(s)

Vi(s)·(− 1sC

)= − G

sC

• Even-order nonlinearities are eliminated.

• The common-mode voltage along the differential signal path must be maintained atV0.

• Linearities around 50 dB have been achieved.



V

V

GBV

GBV

GA

GA

o1V

i2V

i1V

Vo2

I1

I2

C

C

M1

M2

M3

M4

Vi1 = +Vi

2+ V0

Vi2 = −Vi

2+ V0

Vo1 = +Vo

2+ V0

Vo2 = −Vo

2+ V0

GA = k1,2 (VGA − V0 − VT )

GB = k3,4 (VGB − V0 − VT )

I1 = GA ×(+Vi

2

)−[g

(+Vi

2

)− g (0)

]+ GB ×

(−Vi

2

)−[g

(−Vi

2

)− g (0)

]

I2 = GA ×(−Vi

2

)−[g

(−Vi

2

)− g (0)

]+ GB ×

(+Vi

2

)−[g

(+Vi

2

)− g (0)

]



We have

I1 − I2 = (GA − GB) × ViVo(s)

Vi(s)=

I1(s) − I2(s)

Vi(s)·(− 1sC

)= −

GA − GB

sC

• Both even-order and odd-order nonlinearities are eliminated.

• Differential signals are not required to be fully balanced.

• Around 10 dB linearity improvement over the two-transistor MOST-C integrators.

• Linearity performance is limited by the deviation of the above device model andmismatches among the MOSTs.

• Reference: Ismail, JSSC 2/88, pp. 183–194.



V i1

V i2

R1

R2

R2

R1

V

V

V

V

M1

M2

CA

CB

CB

CA

M3

M4

C

C

V

V

o1

o2



Vo

Vi= −

R2/R1

sC[R2

(1 + RM1

R1‖R2‖RM2

)]+ 1

• The dc gain is not adjustable.

• The integrator’s time constant can be varied by changing RM1 and RM2

• At low-frequencies, the linear resistors, R1 and R2, dominate the transfer function,thus reducing distortion. A linearity of 90 dB has been achieved.

• In the criss-cross version, M3 and M4 reduce the effective dc gain and bandwidthof the integrator, enhance the unity-gain frequency sensitivity to componentmismatches, and increase noises.

• Reference: U-K Moon, et al., JSSC 12/93, pp. 1254–1264.


A MOST-C Tow-Thomas Biquad

R/K

GVGV

GV

GV

GV

MR/K

MRQ

MRQ

MR

MR

MR

MR

bV lViV

GV

GV

VG

M

C

C

C

C


Transconductors

I

go

o

g

oI

oIoI

iViViV

i

Io

oVi Vi V

oIo I

Ci

iC

Ideal Model Nonideal Model

mG

mG

Io = Gm × Vi


Transconductor Basic Circuits

iZ

V

i

iZ

i

Voltage Amplifier

Vi1

Vi2

Vo

Lossless IntegratorControlled Resistance

V

iV

o

VoVi1

Vi2

V oV

o

V

C

G

CG

2C

2C

m1G

m1

m1G

m1G

m1

m2

m3G

G

G

m1

m3m1

m2

G

G

G

Zi =1

Gm1Vo =

1Gm3· (Gm1Vi1 − Gm2Vi2)

Vo(s)

Vi(s)= −

Gm

sC


Gm-C Lossy Integrator

i oV

i

Vi

VoVoV

Vo

V Vi

C

C

m1G

= m2m1G G

m1

m2G

G

m2C

m1GG

m2m1 CG G

Vo(s)

Vi(s)= −

Gm1

sC + Gm2

• Since no feedback for the integrators, they can be wide-band.

• A transconductor’s output current should be linearly related to the input over the entireinput voltage range.


Fully-Differential Gm-C Integrators

oVVo iV

2C

Vi Vi

2C

Vo

Cp

p

mG

Cp

Cp

mG

CC

mG

C

Vo(s)

Vi(s)= −

Gm

s(C + Cp/2)

• Can use only grounded capacitors.

• The Cp can affect the integration time constant.

• Partially nonlinear Cp can also cause linearity problems.


Gm-C Opamp Integrators (Miller Integrators)

o

I

I oI

oV

V

o

BiV

oo

BVV

I

Cp

pC

VDD

VSS

VDD

VSS

mG

2C

2C

2C 2C

Vo(s)

Vi(s)= −

Gm

sC

• The effects of parasitic capacitances are reduced.

• The Gm’s output stage can be simplified, since no large voltage swing is required.

• The lower impedances at the Gm’s output nodes make those nodes less sensitive tocapacitive coupling of noise.


Gyrators

2

L

1L

1 II

VGm2Gm1 2V2V1V

I2

V1 V2

1

1

V2V1

I1V

2

V1

V1 V2

C

Floating Inductor

Grounded Inductor

C

Modelm2 m1G G

m2 m1 m1 m2G G G G

L1 =C

Gm1 · Gm2L2 =

C

Gm1 · Gm2


Gm-C Simulated Gyrators

V1 V2

Gyrator

V1

1

V1

V1V

Simulated Floating Inductor

Simulated Grounded Inductor

2

V1 V2

V

V

2

m1m2G G m1m2C

GG

m1m2G G m1m2 CGG

m1m2 m1 m2C

G G G G

m1m2 m1 m2CG G G G



o2

i2

Io1I Io1o2

i2Vi1Vi1V

I

V

VSSVSS

11

1/2 1/2

0.85 I 0.15 ITuningTuning



Adaptive Source Degeneration

Bias

/

mo

Vi2V

IiVG /

mo GmG

i1

Io1 Io2

VSS

Tuning

0

1

1-1

Bias Offset Linearization

o1I o2I

i2Vi1V

V BV B

VSS

M1 M2

M3 M4

Let M1=M2=M3=M4,

ID =12k (VGS − VT )2

Io1 = Io2 = kVB (Vi1 − Vi2)


MOST Transconductors with Source Degeneration

I

o2Io1I

CV

i1V’ i2V’

V i2V

a I

a

Vi1 Vi2

V’i1 V’i2

V’i1 V’i2

b

I

o2I

i1

Io1

VSSVSS

V

V

CA

CB

Double-MOST TypeFully Balanced Type

M1 M2

MA

M3 M4M2M1

MB

MA


MOST Transconductors with Source Degeneration

Let

V ′i1 = +

Vi

2+ V0 V ′

i2 = −Vi

2+ V0 G = k(VC − V0 − Vt)

For the fully balanced differential transconductor

Ia = G × Vi −[ge

(+Vi

2

)− ge

(−Vi

2

)]−[go

(+Vi

2

)− go

(−Vi

2

)]

Io1 − Io2 = 2Ia ≈ 2G × Vi − 2go

(+Vi

2

)≈ 2G × Vi

For the double-MOSFET differential transconductor

Ia = GA × Vi −[g

(+Vi

2

)− g

(−Vi

2

)]Ib = GB × Vi −

[g

(+Vi

2

)− g

(−Vi

2

)]Io1 − Io2 = 2(Ia − Ib) = 2(GA − GB) × Vi


BJT Transconductors

V

I

OSV

I

Vi1 Vi2

Io1 Io2

o2o1I

o2Io1

OS

i2V

OS

i1

V

Vi1 Vi2

Multi-tanh Doublet

V

VEE

VEEVEE VEE

V i

g m

Q1 Q2

R

Q1Q3

4x 4x1x 1x

Q2Q4

Q2Q1

Total

Q2-Q4

Q1-Q3

VOS = kTq

ln IS1IS2


Multi-Input Transconductors

V

oB2

o

V

B1Va

Vb

Io

I

B3VVa Vb

Io

Io

Vo

V

V

B4

M8

M10

M7

M9

VSS

mb

ma mb

G

G

G

M4

M6

M3

M5

VDD

G

ma

Io = Gma · Va + Gmb · Vb

• Need only one output common-mode feedback.

• Reference: Edited by Y.P. Tsividis and J.O. Voorman, “Integrated Continuous-TimeFilters”, IEEE Press, 1993.


Transconductor’s Imperfections

g oo

oV

oI

iV ViV

g

Voi

Ci iC C

Nonideal Model

m1G

C

Io = Gm(s) × Vi Gm(jω) =Gm

1 + jω/ω2

≈ Gme−jφ φ = tan−1 ω

ω2

For the Gm-C integrator

Vo

Vi=

Gm

1 + s/ω2

× 1sC + go

=Gm

sC(

1 + ωo

ω2

)+ go

(1 + s2

ωoω2

) ωo =go

C


The Effect of Non-Zero go on Gyrators

V

Vgo

i

Vi

og

1L

og

iRs

mG

mG

mGmG C

C

L =C

G2m

Rs =go

G2m


The Effect of Phase Shift on Gyrators

V

iL

Vi

1i

V

G

mG

m

pRmGmG C

C

If

Gm(jω) = Gme−jφ φ = tan−1

(ω

ω2

)≈ ω

ω2 1

We have

L =C

G2m

1Rp

≈ −2G2

m

ωC·φ ≈ −

2G2m

ω2C= − 2

ω2L


Gm-C First-Order Filters

i2o

V

1sτVi Vo

=

= =

VoVi1

Vi2

Vi1 Vm1

C

Gm3G

Gm1 Gm2Gm4Gm3 Gm5

1

m2C m3

m4

m5G

G

G

GGm1

α1s + α0

H(s) = −(

Gm1Vi1

sC + Gm2· Gm3 + Gm4Vi2

)· 1Gm5

= −sCGm4Vi2 + (Gm1Gm3Vi1 + Gm2Gm4Vi2)

(sC + Gm2) · Gm5

• The output requires another buffer to prevent loading effects.

• Use only grounded capacitors.



= 0=

1s

Vi3i2V

2

Vi1

Vi1

Vi2

i3V

Vo2

Vo1

Vo3

Vb Vl=

τ

C

2C

1sτVi

C

1C

b

1

VlVh V

K

1

G

1/Q

m3G m5

m1m2

m3

m4m5G

G

G

G

G

m1m2

m4G

GG

Vb =sC2Gm1

s2C1C2 + sC2Gm1 + Gm2Gm4

Vl = −Gm1Gm2

s2C1C2 + sC2Gm1 + Gm2Gm4



The transfer functions are

Vo1 = [1/D(s)] · [sC2Gm1(Gm5Vi1 − Gm4Vi3) + Gm1Gm2Gm4Vi2]

Vo2 = [1/D(s)] · [(sC1Gm2Gm5 + Gm1Gm2Gm3)Vi2Gm1Gm2(Gm4Vi3 − Gm5Vi1)]

Vo3 = [1/D(s)] · [s2C1C2Gm4Vi3 + s(C2Gm1Gm3Vi1 − C1Gm2Gm4Vi2) + Gm1Gm2Gm4Vi1]

D(s) = C1C2Gm5

(s2 + s

1C1

Gm1Gm3

Gm5+Gm1Gm2Gm4

C1C2Gm5

)

If Vi1 = Vi2 = 0, then

Vo1

Vi3= HBP(s) = −

sC2Gm1Gm4

D(s)

Vo2

Vi3= HLP(s) =

Gm1Gm2Gm4

D(s)

Vo3

Vi3= HHP(s) =

s2C1C2Gm4

D(s)



If Vi1 = Vi2 = Vi3 = Vi , then

Vo3

Vi=

s2C1C2Gm4 + s(C2Gm1Gm3 − C1Gm2Gm4) + Gm1Gm2Gm4

D(s)

• If C2Gm1Gm3 = C1Gm2Gm4, it is a band-reject biquad.

• If C1Gm2Gm4 = 2C2Gm1Gm3 and Gm4 = Gm5, it is an allpass biquad.

• There is one parasitic pole in the biquad.


Gm-C First-Oder Filters Using Miller Integrators

ViV

1sτVi Vo

iV o

o

V

Gm2

2CX

2C

CA

CX

m2GX

1

Gm1

2C

2CA

A

m1G

α1s + α0


Gm-C First-Oder Filters Using Miller Integrators

Without the Miller Integrator

Vo

Vi=

α1s + α0

s +ωo

=s(

CX

CA+CX

)+(

Gm1CA+CX

)s +(

Gm2CA+CX

)Gm1 = α0(CA + CX ) Gm2 = ωo(CA + CX ) CX = CA

α1

1 − α1where 0 ≤ α1 < 1

With the Miller Integrator

Vo

Vi=

α1s + α0

s +ωo

=s(CX

CA

)+(Gm1CA

)s +(Gm2CA

)

• The use of feed-in capacitors can simplify design, but requires inputs of low sourceimpedance.


Gm-C Second-Oder Filters Using Miller Integrators

s1Vi

1sτ Vo

iVi

1

oV

τ

V

2CA

2CA 2CB

2C

Gm3Gm4

2CX

2CX

B

1/Q

Gm1 Gm2

Gm5

α0

α1 + α2s


Gm-C Second-Oder Filters Using Miller Integrators

The transfer function is

Vo

Vi=

α2s2 + α1s + αo

s2 +(ωp

Q

)+ω2

p

=s

2(CX

CB

)+ s(Gm5CB

)+(Gm2Gm4CACB

)s2 + s

(Gm3CB

)+(Gm1Gm2CACB

)

ThusCX = α2CB

and

Gm1 = ωpCA Gm2 = ωpCB Gm3 =ωpCB

QGm4 =

α0CA

ωp

Gm5 = α1CB



C2

o

iV

iV

V

C2

V

V

i

C2

o

V

o

C2

RS RLC1L2

C3

m2m2

C1 C3

mi mS mLG G G m1 m1G G G G

C

m1 m1 m2

C3C1

mimLm2mS

GG G G G G G

C

Single-Ended Implementation

Fully Differential Implementation



• Inductors are replaced with Gm-C gyrators.

• Floating capacitors are required.

• Finite go of the transconductors results in lossy inductors and capacitor, i.e., Qdegradation; while phase shift causes Q enhancement.

• The Q-control automatic tuning circuits may be required.



RL

V 1

RSV in

V 2V 0

V 1

V 4

V 5V 3

V in V out

I 0 I 2 I 4 V 5V 3

GmS

V 0

V 1

V 2 V 4 V 6

V outV 5V 3V in

GmL

C1L2

C3 C5L4

I 6

1/(sL L

V 6

S1/R 1/(sL2) -1/(sC 3) 4) -1/(sC 5) 1/R-1/(sC )1

V out

C1 C2 C3 C4 C5



• Floating capacitors are not necessary.

• Finite go of the transconductors results in lossy inductors and capacitor, i.e., Qdegradation; while phase shift causes Q enhancement.

• Signal-level scaling is possible.


Gm-C Simulation of Ladder Branches (I)

Shunt Branch

1I 3I

C4

L

V

1V1V

C10R

L4 V

3

Series Branch

2

L

3

C1

V1 V3

I2

L C3

2

2

0R

C1

mi1

mi2m0

C3 C4

C2

G

GG


Gm-C Simulation of Ladder Branches (II)

V

1V1V

3

C3

mi1

mi2m0

C1

C4

C2

G

GG


Gm-C Simulation of Ladder Branches

The branch characteristics are

I2 = (V1 − V3) · Y (s) = (V1 − V3) · 1

R0 + sL1 +1

sC2+ 1

sC3+1

sL4

V2 = (I1 − I3) · Z(s) = (I1 − I3) · 1

G0 + sC1 +1

sL2+ 1

sL3+1

sC4

The Gm-C circuit’s transfer function is

V2 = (Gmi1 · V1 − Gmi2 · V3) · 1

Gm0 + sC1 +1

sC2+ 1

sC3+1

sC4

• Method 2 usually uses more transconductors than method 1, but may haveadvantages in terms of sensitivity to and compensation for parasitic effects.

• For better matching, use identical transconductors whenever possible.


Gm-C Resonators

V o

V i

V o

I i

C1

C2

m2 m3

m4

C1 RL

m1G

G G

G


Gm-C Resonators

• The inductor L is simulated by Gm2, Gm3, and C2. The resistor R is simulated by Gm4.

• The resonant frequency and the quality factor are

ωo =

√1

LC1=

√Gm2Gm3

C1C2Q = ωoRC1 =

√C1

C2×

√√√√Gm2Gm3

G2m4

The voltage gain at the resonant frequency is

Avo =vo

vi= Gm1R =

Gm1

Gm4

• Reference: Silva-Martinez, et al., JSSC 12/92, pp. 1843–1853.


Gm-C Quadrature Oscillators

1CGGL D

2C

V oV o

m2

m3 m4

m1GG

G G

I

V

L C

• The combination of Gm1, Gm2 and C1 simulates an inductor.

• The oscillation frequency is ωo =√Gm1Gm2/(C1C2).

• The oscillation condition is Gm4 = Gm3. In many cases, Gm3 and Gm4 are not required.

• The nonlinear resistor is used to control the output amplitude.

• Reference: Rodriguez-Vazquez, Transactions on Circuits and Systems, 2/90,pp. 198–211.


On-Chip Tuning Strategies

Direct Tuning

Indirect Tuning

LPF

S outS in

ref

LPF

S

cntrlU

S in

cntrl

S out

S ref

Filter to be Tuned (Slave)

Reference Circuit (Master)

Control Circuit

Filter B to be Tuned

Control Circuit

Filter A to be Tuned

U


Separate Frequency and Q Control

LPF

Ref Ckt 2

Control Ckt Control Ckt LPF

S in S out

S rf S rQ

Filter to be Tuned

QF

Ref Ckt 1

UU

Freq Tuning Loop Q Tuning Loop


Gm Tuning

R

CV

C

V

RV

Rext

1C

CVR

1

V

mG

Rext

Gm

• VC is automatically adjusted so that

Gm =1

Rext

• C1 is an integrating capacitor used to maintain loop stability.


Frequency Tuning Using Switched Capacitors

V R

CI

V F

C1

R1

I BI B

Cm

CI

V F

C1

R1

Gm

Cm

2

1 1

2

Gm

N

2

1

1

2

Gm =1

Req

= fsCm

⇒Gm

Cm

= fs

NIB ·1Gm

· 1Req

= IB

⇒Gm

Cm

= Nfs



Rb

Cb

DetectorPeak

DetectorPeak

Ra

Ca

MOST-C Filter

R1R2

V

V

1

2

Tuning System

C

R

V F

Vr sin(ωrt + θ)



For this amplitude-response detection scheme

V1 = Vr ·1

ωrRCV2 = Vr ·

R2

R1 + R2

The feedback adjusts VF so that V1 = V2, thus

R · C =1ωr

·(

1 +R1

R2

)

• The above tuning system is a magnitude locked loop (MLL).

• Usually use ωrRC 1 to place ωr in the filter stopband.

• Phase-response detection scheme can also be used.

• The reference circuit can be any filter.



Filter

Low-PassPhase-FreqDetector

FV

reff

C

mm

Variable-Frequency Oscillator

C

f oC

mGG

G

Gm-C Main Filter



The phase-locked loop (PLL) forces

fref = fo =1

2π·Gm

C⇒

Gm

C= 2πfref

• For best matching between the reference VFO and the main filter, it is best to choosefref at the upper passband edge. However, the reference signal may leak into the mainfilter’s output.

• If fref moves away from the upper passband edge, the matching will be poorer, but animproved immunity to the reference signal results.

• If the VFO is sensitive to supply variation, any power-supply noise can inject jitter intoVF .


Q-Factor Tuning Using MLL

PeakDetBiquad

Bandpass

PeakDet

Q d

V ref

SlaveFilter

V i V o

V Q

Hbq(s) =ωps

s2 +ωp

Qps +ω2

p

Vref = A sinωrt

• At s = jωr = jωp, the MLL forces Hbq(jωp) = Qp = Qd .

• For high Q biquad, mismatch between ωr and ωp results in large Q-tuning error.

• Distortion in Vref can also cause error.



BiquadBandpass

Q d

1

V Q

V i V o

V ref

SlaveFilter

Hbq(s) =ωps

s2 +ωp

Qps +ω2

p

Vref = A sinωrt

dVQ(t)

dt= µ ·

[Vref(t) − Vbq(t)

]· Vbq(t)

The modified continuous-time least-mean-squares (LMS) algorithm will force

[Vref(t) − Vbq(t)

]· Vbq(t) = Vref(t) · Vbq(t) − V 2

bq(t) = 0



If ωr = ωp,

Vbq(t) =Qp

Qd

· A sinωrt = B · sinωrt B =Qp

Qd

· A

LMS ⇒ A · B2

=B · B

2⇒ A = B ⇒ Qp = Qd

If ωr = ωp,

Vbq(t) =Qp

Qd

cosφ · A sin (ωrt +φ) = B · sin (ωrt +φ) B =Qp

Qd

cosφ · A

LMS ⇒ A · B · cosφ2

=B · B

2⇒ A cosφ = B ⇒ Qp = Qd

• Insensitive to mismatch between ωr and ωp.



• Require no peak detector.

• The scheme is also insensitive to Vref waveform shape.

• Square wave can be used for Vref(t).

• Reference: J.-M. Stevenson, et al., An Accurate Quality Factor Tuning Scheme for IFand High-Q Continuous-Time Filters, JSSC 12/1998, pp. 1970–1978.


Switched-Capacitor Filters

Jieh-Tsorng Wu

October 23, 2002

A

1896


Switched-Capacitor Equivalent Resistor

V1 V2

eqR

Ieq

V V2

C

V1 V2φ φ1

φ

1

fs

φ

Ts

1

2

2

C

Ieq =(∆Q

∆t

)=

C · V1 − C · V2

Ts= C · (V1 − V2) · fs Ts =

1fs

Geq =1

Req

=Ieq

V1 − V2= C · fs

SC Filters 23-2 Analog ICs; Jieh-Tsorng Wu

Switched-Capacitor Integrators

1

oViV sfiV

2

Vo

C2

C

1R

C

Vo

Vi= − 1

sR1C2= −1

s·Geq1

C2= −1

s·(fs ·

C1

C2

)

• Consist of analog switches, capacitors and opamps.

• Discrete-time (or sampled-data) analog filters.

• Time constant is determined by capacitance ratio and switching frequency.



sT

φ1

φ2

1C

C2

V2C1C

oVV

z 1

o

i

φ1

φ2

aφ1

aφ2

V

a

Vi

2Q

1Q n n+1n-1n+1/2n-1/2

CLK

21

Vo(z)

Vi(z)= −

C1

C2× z

−1

1 − z−1



At cycle n, i.e., t = nTs, we have Q1(n) = C1Vi(n) and Q2(n) = C2Vo(n)

At cycle n + 1/2, i.e., t = (n + 1/2)Ts,

Q1(n + 1/2) = 0 Q2(n + 1/2) = Q2(n) −Q1(n) = C2Vo(n) − C1Vi(n)

At cycle n + 1, i.e., t = (n + 1)Ts,

Q1(n + 1) = C1Vi(n + 1) Q2(n + 1) = C2Vo(n + 1) = Q2(n + 1/2) = C2Vo(n) − C1Vi(n)

Thus, the time-domain difference equation is

C2Vo(n + 1) = C2Vo(n) − C1Vi(n)

In the z-domain

zC2Vo(z) = C2Vo(z) − C1Vi(z) ⇒Vo(z)

Vi(z)= −

C1

C2× 1z − 1

= −C1

C2× z

−1

1 − z−1


SC Differential Integrators

oVo

C2

1R

C

V

i1V V

C1

i2

2

1RC2

Vi1

Vi21

Q2

Q

21

21

RC Integrator → Vo(s) = − 1sR1C2

(Vi1 − Vi2)

SC Integrator → Vo(z) = −C1

C2× z

−1

1 − z−1× [Vi1(z) − Vi2(z)]



V

A

Vo

C2

i2V

Cp1

1

Cp4Cp3

Cp2

C

i1Va21

21

Vo(z) =

[−C1

C2[Vi1(z) − Vi2(z)] −

Cp1

C2Vi1(z)

]× z

−1

1 − z−1



• Among the parasitic capacitors, only Cp1 contribute charge to C2 if A =∞.

• Consider a finite value of A, then Vo = −A · Va, and

C1[Vi1(n) − Vi2(n)] + C2[Va(n) − Vo(n)] + Cp1Vi1 + Cp3Va(n)

=(C1 + Cp1 + Cp3

)Va(n + 1) + C2[Va(n + 1) − Vo(n + 1)]

⇒ Vo(z) =

[−C1

C2[Vi1(z) − Vi2(z)] − Cp1

C2Vi1(z)

]× z

−1

1 + 1A

(1 + C1

C2+

Cp1C2

+Cp3C2

)− z−1

[1 + 1

A

(1 +

Cp3C2

)]

• Must keep Cp1 C1 and Cp1,p3 C2.

– Connect the top plates of the capacitors to the opamp’s input.– Let the bottom plates of the capacitors always be driven.


Parasitics-Insensitive SC Integrators

φ1

φ21

i2V i1

2

Vo

C

C

Vn

n+1/2n-1/2n-1 n+112

12

Vo(z) =

C1C2

[−Vi1 + z

−1Vi2

]1 + 1

A

(1 + C1

C2+

Cp1C2

+Cp3C2

)− z−1

[1 + 1

A

(1 +

Cp3C2

)]

• Insensitive to parasitics if A→∞.

• The two inputs have different delays.


Fully Differential SC Integrators

2

C

i1V

oV

i2V

i2V

CMIV

i1V

oV

C1

12

C

C

2 1

12

12

12

Vi1 = Vi1+ − Vi1−

Vi2 = Vi2+ − Vi2−

Vo = Vo+ − Vo−

Vo(z) =C1

C2×[− 1

1 − z−1· Vi1 +

z−1

1 − z−1· Vi2

]

• VCMI and VCMO can be different.



2

i

C

i

C

oV

V

V Ts

1C

2C

oVi ViVo Vo

s

1

V

TCMIVCMIVCMIV m

onR

C

MOST Switch Model

C

a

a

1 1

2 2

a

a

1

1

1

2 2

VDD

VSS

VDD

VSS

Ron = 1µCox(W/L)Vov

For good settling, want

mTs > 5RonC =5C

µCox(W/L)Vov



• When turning off the switch, the switching error is

∆V =αQCH

C=

αWLCoxVov

C

The maximum clock rate is

fs <m

α· µ∆V

5L2

• Realize switches connected to VSS or near VSS with nMOSTs.

• Realize switches connected to VDD or near VDD with pMOSTs.

• Turn off the switches near the virtual ground node of the opamps first.

• The thermal noise is proportional to kT/C.

• There are also noises from the power supplies.



A

1C

2C

oV

o

Vi1

2 2

1

If Ao =∞, then

Vo(n) = −kVi (n) + Vo(n − 1)

H(z) = − k

1 − z−1

k =C1

C2

If Ao = 1/µ is finite, then

Vo(n) = −kαVi (n) + βVo(n − 1) H(z) = − kα

1 − βz−1

α =1

1 + (1 + k)µ≈ 1 − (1 + k)µ = 1 + ∆α ∆α = −(1 + k)µ 1

β =1 + µ

1 + (1 + k)µ≈ 1 − kµ = 1 + ∆β ∆β = −kµ 1



The transfer function H(z) in s-domain is

H(ejωTs) ≈ − k

1 − z−1

∣∣∣∣z=ejωTs

× [1 +m(ω)]ejθ(ω)

m(ω) ≈ ∆α − ∆β

2≈ −(

1 +12

C1

C2

)· 1Ao

θ(ω) ≈ −∆β2· 1

tan(ωTs/2)≈ 1

2·C1

C2· 1Ao

· 1

tan(ωTs/2)≈

C1

C2· 1Ao

· 1ωTs

• At the unit-gain frequency ωi , where∣∣∣H(ejωiTs)

∣∣∣ = 1, we have

−m(ωi ) ≈ θ(ωi) ≈ 1/Ao if ωiTs/2 1

• In most applications, the magnitude error m(ω) has negligible effect, but the phaseerror θ(ω) can be detrimental in narrowband (high-Q) filters.


Effects of Opamp’s DC Offset

Vi

V

2C

o

OS

CV

11

2 2

1

Vo(z) = −C1

C2

1

1 − z−1· Vi(z) +

C1

C2

1

1 − z−1· VOS + VOS

• The VOS to Vo transfer function is also an integration.

• When the entire filter is considered, the VOS may cause finite dc level shift in this andother integrators.


An Offset Auto-Zeroing Scheme

φ1

φ

C

OS

Vi

C

V

C

o3

φ

2

1

2

3

V11

2 3

3

3

2

• During the φ3 auto-zeroing mode, opamp’s offset voltage is stored in C3.


Effects of Opamp’s Finite Settling Time

C φ1

φ2

Vo

1C

2

A

oVVi

t slew

t settle

1

1

2 2

1

T

• Let tslew = 0, A(s) = ωu/s, T1 = Ts/2, ωi is the unit-gain frequency of the integrator,and ωiTs 1. At ω = ωi , the magnitude error and phase error of the integrator are

m(ωi) ≈ θ(ωi) ≈ −ωiTse−ωuTs/2

• Want ωu ≥ 5 · ωs. However, to avoid unnecessary noise aliasing, ωu should not betoo much larger than necessary.



φ1

φ2

t1 t2 t3

C

C2 C2

A

OSV

OS

C’

o

V

Vo

i1

C

VOS

C1 C1 C’2C’2

V

2

2V

V

o

o

1

2 2

1 2

φ1 = 1 φ2 = 1



Consider the VOS effect only. Let

Vi = 0 Ao =∞ and ∆VOS(t) = VOS(t) − VOS(t − Ts/2)

At t = t2

Vo(t2) = Vo(t1) + VOS(t2) +

(1 +

C′2

C2

)∆VOS(t2)

At t = t3

Vo(t3) = Vo(t2) − VOS(t2) +(

1 +C1

C2

)∆VOS(t3)

= Vo(t1) + ∆VOS(t2) +(

1 +C1

C2

)∆VOS(t3)



2 2C’

C2 C2

1 C

ViV

aVo

CV

a

1 C’Vo

AoAo

φ1 = 1 φ2 = 1

Consider the finite dc gain effect only. Let VOS = 0, and

Ao =1µ

k =C1

C2j =

C′2

C2ε1 = (1 + k)µ ε2 = (1 + j )µ

At t = t2

Vo(t2) ≈ Vo(t1) − j (1 − ε2)Vo(t1) =[1 − jµ + (1 + j )µ2] Vo(t1)

• Note that Va is reset from −µVo(t1) to 0.



At t = t3, assuming Vi = 0, then

Vo(t3) = Vo(t2) + [µVo(t2) + Va] + kVa = −Ao [Va − µVo(t2)]

⇒ Vo(t3) =(

1 +1

1 + k + Ao

)Vo(t2) ≈

[1 + µ − (1 + k)µ2] Vo(t2)

Including Vi , we have

Vo(t3) ≈ −k(1 − ε1)Vi (t3) +[1 + µ − (1 + k)µ2] Vo(t2)

≈ −k(1 − ε1)Vi (t3) +[1 + (1 − j )µ − kµ2] Vo(t1)



If j = C′2/C2 = 1, the output difference equation becomes

Vo(n) = −k(1 + ∆α)Vi(n) + (1 + ∆β)Vo(n − 1)

∆α = −(1 + k)µ = −(

1 +C1

C2

)· 1Ao

∆β = −kµ2 = −C1

C2· 1

A2o

• Reference: W. Ki, el. al., “Offset-Compensated Switched-Capacitor Integrators,”ISCAS, 1990, pp. 2829–2832.


Discrete-Time Signal Processing

DACTimeDiscrete

ProcessingPrefilter

c (t)

Analog

d (t) ycx

Ts

Ts

c

y

x

T

(t)

2Ts3Ts

(t)

s

AnalogPostfilter

Sampling

y(n)x(n)

0

A

t0

2π0 4π

Ax(n)

0n

1 2 3

Ω

ω

Ωb Ωs 2Ωs

Xc(jΩ)

X(ejω)


Continuous-Time Signals

The Laplace transform and the continuous-time Fourier transform (CTFT) are

Xc(s) =∫ ∞−∞

xc(t)e−stdt Xc(jΩ) =∫ ∞−∞

xc(t)e−jΩtdt

If the region of convergence of Xc(s) includes the imaginary axis, then

Xc(jΩ) = Xc(s)|s=jΩ

Sampling Theorem: To avoid aliasing, want

Ωs > 2Ωb Ωs = 2πfs =2πTs

• Ωb is the bandwidth of xc(t), Ωs is the sampling frequency, and 2Ωb is called theNyquist rate.


Discrete-Time Signals

In discrete-time domain, the z transform is

X (z) =∞∑

n=−∞x(n)z−n

The discrete-time Fourier transform (DTFT) is

X(ejω)=

∞∑n=−∞

x(n)e−jωn

If the region of convergence of X (z) includes the unit circle, then

X(ejω)= X (z)|z=ejω



Want to approximate Hc(s) with H(z).

z = esTs s =1Ts· ln z ⇒ H(z) = Hc(s)|s=(1/Ts) ln z ≈ Hc(s)|s=T (z)

Transformation error of an Integrator can be written as

Hc(s) =1s=

1jΩ

⇒ H(z)|ejΩTs =1jΩ· [1 − ε(Ω)] · ejφ(Ω)

oiV ViVs to z

-1z

1/2 BL

FE

BE

LD



Backward Euler (BE) Transformation

s =1Ts·(1 − z−1) ⇒ 1

s= Ts ·

1

1 − z−1ε = 1 −

ΩTs/2

sin(ΩTs/2)φ = +

ΩTs

2

Forward Euler (FE) Transformation

s =1Ts· 1 − z

−1

z−1⇒ 1

s= Ts ·

z−1

1 − z−1ε = 1 −

ΩTs/2

sin(ΩTs/2)φ = −

ΩTs

2

Lossless Discrete (LD) Transformation

s =1Ts· 1 − z

−1

z−1/2⇒ 1

s= Ts ·

z−1/2

1 − z−1ε = 1 −

ΩTs/2

sin(ΩTs/2)φ = 0


Bilinear s-to-z Transformation

The transformation is

s =2Ts· 1 − z

−1

1 + z−1⇒ 1

s=

Ts

2· 1 + z

−1

1 − z−1ε = 1 −

ΩTs/2

tan(ΩTs/2)φ = 0

let z = ejω, then

s =2Ts· e

jω − 1

ejω + 1=

2Ts· j tan

(ω2

)= jΩ Ω =

2Ts

tan(ω

2

)

• The unit circle in the z-plane is mapped to the jΩ axis in the s-plane.


Hc(s) to H(z) Design Procedures for Bilinear Transformation

0

0

|H(z = ejΩTs)|

|H(s′ = jΩ′)|

Ω

Ω′

ΩpΩc

Ωz

Ω′p

Ω′c

Ω′z

Ωs/2 Ωs


Hc(s) to H(z) Design Procedures for Bilinear Transformation

• Prewarp the filter specifications from Ω to Ω′.

Ω′p =2Ts

tanΩpTs

2Ω′c =

2Ts

tanΩcTs

2Ω′z =

2Ts

tanΩzTs

2

• Find Hc(s′).

• The H(z) is obtained by

H(z) = Hc

(s′ =

2Ts· 1 − z

−1

1 + z−1

)


Switched-Capacitor Filter Systems

oX (t)Xi(t)

Anti-AliasingFilter

(Limits BW)

FilterReconstruction

(Smooths output)Sampled Data Filter

• Discrete-time (or sampled-data) analog filters.

• Filters consist of analog switches, capacitors and opamps.

• Filter response is determined by ratios of capacitance.


Design Constraints

• Switched-C “resistor” cannot be the only feedback around an opamp. Since the pathis not continuous, it won’t stabilize the opamp.

• No floating node. Otherwise charge can accumulate.

• Capacitor bottom plate must always be driven from a low impedance (voltage sourcesor ground).

• Connect non-inverting opamp input to a dc bias. Otherwise response is sensitive toparasitic capacitances.


Periodic Time-Variance in Biphase SC Filters

V

1C

0oV

1i2

2

1i1V

2oV

1oV

0oV

1i2V

1i1V 2φ

1φ

C

C

1

2 2

1

2

1

1

2

2

1

n n+1/2 n+1

The circuit is periodic time-variant if

V 1o [n · Ts] = V 2

o

[(n +

12

)· Ts]


Periodic Time-Invariance in Biphase SC Filters

2

V

1i2V

1i1V

0

φ

1φ

2C

1C

2oV

1oV

0oV

1i2V

1i1V

o

C

1

2 2

1 2

11

12

2

n n+1/2 n+1

The circuit is periodic time-invariant if

V 1o [n · Ts] = V 2

o

[(n +

12

)· Ts]

• SC filters are more robust when designed to be time-invariant.



1

φ2

i11

Vi31

C3

)( 1-3C 1z

1C

1z2C 1C 1z1-

Vi21

C2

1

Vo1

Vo2

C

1oV1

i2V

i3V

1i1V

1

φ1

V

n n+1/2 n+1

11

C

1

1 2

2

2

1

2

11

2

V 1o =

1

C(1 − z−1

) · [−C1V1i1 + C2z

−1V 1i2 − C3

(1 − z−1) V 1

i3

]V 2o = V 1

o · z−1/2



• V1i1 to V

1o is a Backward Euler (−BE) integrator.

• V1i1 to V

2o is a Lossless Discrete (−LD) integrator.

• V1i2 to V

1o is a Forward Euler (+FE) integrator.

• V2i2 to V

1o is a Lossless Discrete (+LD) integrator.


SC First-Order Filters

1-z 1C1 1

A1i

CB1

z 11-( )CA2

Vi1

Vi1 Vo

1

A1C

oV

1oV

ViV τs1

iV

C

A2C

1V

o

1

B1

C

2

C

1

2 2

1

1

2 2

1

1 1

1

2

1

α1s + α0

Vo(s)

Vi(s)= −

α1s + α0

sτ + 1

V1o

V 1i

= −CA1 ± CA2(1 − z

−1)

CB1 + C(1 − z−1)= −

(CA1C± CA2

C

)∓ CA2

Cz−1

(CB1C

+ 1)− z−1


Switch Sharing

V

CA1

C

oV

1oV

2oV

1oV

B1C

A2C

A1C

1iV

i

1iV

C

A2

2

Vi

1

1

B1

1

C2

1

1

2

C

1

2 2

1

1

2 2

1

1

2

1 12

1

2

1


Bilinear SC First-Order Filters

1-z 1C1 1

1

CB1Vi1

Vo11zA1C

A1C

1iV

iV

C1iV 2

oV

CB1

Vo

1

A1 1

C

2

1

2

2

1

2

1V

1o

V 1i

= −CA1 + CA1z

−1

CB1 + C(1 − z−1)

= −CA1C

+ CA1Cz−1(

CB1C

+ 1)− z−1



1

VVhV

lV1τs

1

B2

1oV

K2C

B1C

1C 2C

A2C

A1C1iV

Ki s

C

τb

11

1/Q

2

12 2

1

21

21

2

1

2

V1o

V 1i

=

(CA1C1

CK2C2

)z−1 −

(CA2C1

CK2C2

)z−2

(CB1C1

+ 1)+(CB2C1· CK2

C2− CB1

C1− 2)z−1 + z−2



z 1C

iV

oV

B2C

2C 1z1-K2C 1z11

1C 1z1-

A1C

A2

1B1C

oV

Vi1

CA2

C1

CK2 1

1 1

B2C

B1C

2C

A1C

1

11 2

12 2

21

2

1

2

1

21


A Low-Q SC Biquad

K3

K6

iV

K2

K4

K51

K1

1 = 1

V

2CC = 1

o11

1 2

2

1

2 2

1

1

2 2

1

1

2 2

1

1

2 2

1

H(z) =Vo(z)

Vi(z)= −

(K2 + K3)z2 + (K1K5 − K2 − 2K3)z + K3

(1 + K6)z2 + (K4K5 − K6 − 2)z + 1= −

a2z2 + a1z

1 + a0

b2z2 + b1z + 1


A Low-Q SC Biquad

We have

K3 = a0 K2 = a2 − a0 K1K5 = a0 + a1 + a2 K6 = b2 − 1 K4K5 = b2 + b1 + 1

• Additional constraint can be made by

K5 = 1 or K4 = K5 =√b2 + b1 + 1

Let z = ejΩTs = cos(ΩTs) + j sin(ΩTs), and

z1/2 = cos(ΩTs

2

)+ j sin

(ΩTs

2

)z−1/2 = cos

(ΩTs

2

)− j sin

(ΩTs

2

)

Then

H(ejΩTs

)= −

K1K5 + jK2 sin(ΩTs) + (4K3 + 2K2) sin2(ΩTs/2)

K4K5 + jK6 sin(ΩTs) + (4 + 2K6) sin2(ΩTs/2)


A Low-Q SC Biquad

Assume ΩTs 1, we have

H(ejΩTs

)≈ −

K1K5 + jK2(ΩTs) + (K3 + K2/2)(ΩTs)2

K4K5 + jK6(ΩTs) + (1 + K6/2)(ΩTs)2= −

α2s2 + α1s + α0

s2 +ωp

Qp· s +ω2

p

Let K4 = K5, then

K4 = K5 ≈ ωpTs K6 ≈ωpTs

Qp

• Usually, ωpTs 1.

• The largest capacitors are the integrating capacitors, C1 and C2.

• If Qp < 1, the smallest capacitors are K4 and K5.

• If Qp > 1, the smallest capacitors is K6.


A High-Q SC Biquad

o1

K1

VK2

K6

K4

1C = 12C

V

K3

K5

= 1

i1

1

1 2

2

1

2 2

11

2 2

1

H(z) =Vo(z)

Vi(z)= −

K3z2 + (K1K5 + K2K5 − 2K3)z + (K3 − K2K5)

z2 + (K4K5 + K5K6 − 2)z + (1 − K5K6)= −

a2z2 + a1z

1 + a0

z2 + b1z + b0


A High-Q SC Biquad

We have

K1K5 = a0 + a1 + a2 K2K5 = a2 − a0 K3 = a2 K4K5 = 1 + b1 + b0 K5K6 = 1 − b0

• Additional constraint can be made by

K4 = K5 =√

1 + b1 + b0

• Less capacitance spread.

In general,

• For the SC biquad, it is important that the two-integrator loop have a single delayaround the loop. A delay-free loop may have an excessive settling time behavior,while two delays around the loop cause difficulties in designing high-Q circuit.


Time-Staggered SC Stages

Cascaded SC Stages

1

1

1 1

1

12

2

1

2

2

1

2

2

2

1

2

2

1

2

11

Staggered Cascaded Stages

1

1

1

12

2

1

2

2

1

2

2

2

1 1

2 1

2 1

2

2

1


Capacitor Scaling

31

C

4Q

3Q

2V

1V

4C

C

2

o

C

AC

iQV

2 1

2 1

21

21

For each switching cycleQi = C1V1 + C2V2

∆Vo = −Qi

CA

Q3 = C3Vo Q4 = C4Vo


Output Capacitor Scaling

If C′A = kCA, C′3 = kC3, C′4 = kC4, C1 and C2 unchanged, then

Q′i= C1V1 + C2V2 = Qi

∆V ′o = −Q′i

C′A

= −Qi

kCA

=∆Vo

k

Q′3 = C′3V′o = kC3

Vo

k= Q3 Q′4 = Q4

• If the values of all capacitors (including feedback capacitors) connected or switchedto the output terminal of an opamp in an SCF are multiplied by the same constant k,then the output voltage of this opamp will be divided by k; all other opamp outputvoltages remain unchanged. This follows since the described changes leave allcharges flowing to and from the affected opamp unchanged.

• The output capacitor scaling technique can be used to achieve optimum scaling formaximum dynamic range.


Input Capacitor Scaling

If C′A = kCA, C′1 = kC1, C′2 = kC2, C3 and C4 unchanged, then

Q′i= C′1V1 + C′2V2 = kC1V1 + kC2V2 = kQi

∆V ′o = −Q′i

C′A

= −kQi

kCA

= ∆Vo

Q′3 = C3V′o = C3Vo = Q3 Q′4 = Q4

• If the values of all capacitors (including feedback capacitors) connected or switchedto the inverting input terminal of an opamp are multiplied by the same constant, thenall voltages in the SCF remain unchanged. This is true since all voltages are affectedonly by the ratios of these capacitances.

• The input capacitor scaling technique can be used to achieve optimum scaling forminimum capacitance.



RL

V 1

RSV in

V 2V 0

V 1

V 4

V 5V 3

V in V out

V in V 2

V 1

V 4

V outV 5

S C11+sR

SR

I 0 I 2 I 4 V 5V 3

C1L2

C3 C5L4

I 6

1/(sL L

V 6

S1/R 1/(sL2) -1/(sC 3) 4) -1/(sC 5) 1/R-1/(sC )1

S1/R

L C51+sR

LR

V out


An All-Pole Low-Pass SC Ladder Filter

2

1

2

1

C

C

C

LC

21

SC

V in

V 3 V 5

C

V 1

V 4V 2

V out

C1

V out

C1RS

RS

V 1

V in

V 2

V 5

V 4

V 3

L2 L4

C3

C5

C 2

1

C3

1

2

1

2

SC CC2 4

CC C

1

1

2

2

1 2 1

2 1 2

1

1 1

R CL 5

11

1 11


SC Ladder Filter Using Signal-Flow Graph

iKK

V1 1V 1oV1

iVo11

1

2

2

C = 1Noninverting FE Integrator

1

2 2

1 1

C = 1Inverting BE Integrator

HBE (z) = −K · 1

1 − z−1HFE (z) = +K · z

−1

1 − z−1

• HBE (z) is a Backward-Euler (BE) integrator. HFE (z) is a Forward-Euler (FE) integrator.

• The phase errors of the integrators are cancelled in the ladder topology, while themagnitude errors can cause deviations in the frequency response when ωTs 1 isno longer true.

• The SC ladder filters are inherently time-staggering.


SC Ladder Filters Design Methodology

It is possible to realize the SC ladder filters with exact frequency response, using onlythe BE and FE integrators. The design procedures involves bilinear transformationprewarping and frequency-dependent impedance scaling.

λ =s′Ts

2=

z1/2 − z

−1/2

z1/2 + z−1/2= tanh

sTs

2

γ =12

(z1/2 − z−1/2

)= sinh

sTs

2µ =

12

(z1/2 + z−1/2

)= cosh

sTs

2

⇒ λ =γ

µµ2 − γ2 = 1 z1/2 = µ + γ

• λ↔ z is the bilinear (BL) transformation.

• γ ↔ z is the lossless discrete (LD) transformation.

• The design goal is to implement H(z = e

sTs)

with H(γ). H(γ) can then be realized

with SC integrators.


SC Ladder Filters Design Procedures

1. Prewarp the filter specifications from ω to ω′ with bilinear transformation.

ω′ =2Ts

tanωTs

2

2. Find H(s′). Renormalize H(s′) into H(λ) by setting s′Ts/2 = λ.

3. Realized H(λ) as an LC ladder filter in λ domain.

4. Scale the impedance level,

Y (γ) = µY (λ) Z(γ) = Z(λ)/µ

to obtain the γ-domain LC ladder circuit.

5. Implement the γ-domain circuit with SC circuits.


Nyquist-Rate Digital-to-Analog Converters

Jieh-Tsorng Wu

July 16, 2002

A

1896



fs

fs

fs

DigitalProcessor

A/DInterface

D/AInterface

y(t)x(t) x(n) y(n)

WorldAnalog

D/A Deglitcher Inverse-Sinc / Low-PassFilter

y(n) y(t)

Converter

Digital-to-Analog Interface

FilterLow-Pass DecoderQuantizerSampling

Circuit

x(t) x(n)

Analog-to-Digital Interface

DACs 24-2 Analog ICs; Jieh-Tsorng Wu


DACTimeDiscrete

ProcessingPrefilter

c (t)

Analog

d (t) ycx

Ts

Ts

c

y

x

T

(t)

2Ts3Ts

(t)

s

AnalogPostfilter

Sampling

y(n)x(n)

0

A

t0

2π0 4π

Ax(n)

0n

1 2 3

Ω

ω

Ωb Ωs 2Ωs

Xc(jΩ)

X(ejω)



0

1

Ts

d (t)

T

y

2Ts3Ts

s s3Ts2T

t0

A

0

A

t0

y (t)c

Ω

Ω

Ω

Ωs

Ωs

Ωs

2Ωs

2Ωs

2Ωs

Yd (jΩ)

Yc(jΩ)

sinc(π ΩΩs

)



The digital-to-analog converter (DAC) usually performs the discrete-to-continuoussample-and-hold translation, i.e.,

yd (t) =∞∑

n=−∞y(n) · (t − nTs) where (t) =

1 if 0 < t < Ts0 otherwise

The continuous-time Fourier transform (CTFT) of yd (t) can be expressed as

Yd (jΩ) = Yd (z)|z=ejΩTs × Hda(jΩ) = Yd(ejω)∣∣

ω=ΩTs× Hda(jΩ)

The discrete-to-continuous sample-and-hold transfer function is

Hda(s) =1 − e

−sTs

sHda(jΩ) = e−jπΩ/Ωs · Ts · sinc

(πΩ

Ωs

)

Ωs = 2πfs =2πTs

sinc(x) =sinx

x


Imperfections in Discrete-to-Continuous Conversion

The D/A conversion of y(n) can be expressed as:

yd (t) =∞∑

n=−∞y(n) · C[t − nTs + ε]

• The y(n)→ y(n) conversion may contains gain error, offset, and nonlinearity.

• C(t) has transient behavior. Its pulse width can be larger than Ts.

• C(t) may contain y(n) dependency.

– A return-to-zero C(t) can reduce the y(n) dependency.

• The timing jitter ε can be random or deterministic.



bN-1 b1 b0

Ao

AFS

AFS

Ao

Din000 100

2

111

D/A

(Analog Output)

(Digital Input)

0

AF S = Full-Scale Output

∆ = LSB = Step Size =AF S

2N

Ao = ∆ × Din

= ∆ ×[bN−12N−1 + · · · + b121 + b020]

= AF S ×[bN−12−1 + · · · + b12−(N−1) + b02−N

]

• In some applications, relationship between Din and Ao can be nonlinear.

• Din may use other coding scheme such as offset binary or 2’s complement.



Din

00

Nonmonotonic Offset Gain Error

Din

Ao Ao

Din

Ao

0

AOS

Ideal Ideal

Offset Error =AOS

∆AOS = Ao|Din=0

Gain Error =Ao,max − AOS

∆ · (2N − 1)=

Ao,max − AOS

AF S · (1 − 2−N)


D/A Nonlinearity

Din

Aoo

0

Large INLLow DNL

0

DNL=-1LSB

0Din

Ao

Din

A

DNL

INL

• Measure of deviation from straight line with offset and gain error corrected.

• Differential nonlinearity (DNL): Maximum deviation of the analog output step fromthe ideal value of 1 LSB (= ∆).

• Integral nonlinearity (INL): Maximum deviation of the analog output from the idealvalue.


D/A Performance Metrics — Static Characteristics

• Resolution: number of bits (N), analog 1 LSB step (∆).

• Offset error.

• Gain error.

• Integral nonlinearity (INL).

• Differential nonlinearity (DNL).

• Monotonicity.

– Monotonicity can be assumed if the DNL > −1 LSB.

• Stability.

– Variation with time, temperature, and supply voltage.


D/A Performance Metrics — Dynamic Characteristics

• Sampling rate.

• Settling time.

– Settling time is the time taken by the D/A output to settle within some specifiederror band (typically ±1

2 LSB).– The settling time is primarily dominated by the settling of the MSB contribution.

• Glitch impulse area (glitch energy).

– Glitches is the output transient spikes during the conversion process.– Glitches are caused by the unequal delays in switching various signal sources

within the converter.

• Dynamic range: SNRmax, SFDR, SINAD.


Dynamic Range

N-Bit DACN-Bit y(t)

Measured

Input Level Relative to Full Scale

dB

Ideal

0

(dB)

if i2f i3f

sf

SINAD

f

dBm/Hzy(t) Power Spectrum

SFDR

Probability Density Function (pdf)

e/2

y(k)x(k)

/2

Quantizer

e(k)

y(k)x(k)


Dynamic Range

e(k) is a quantization noise due to the quantization process.

e(k) ≡ y(k) − x(k) Noise Power = Pn =∫e2pdf(e)de =

112

∆2

Let the input x(k) be a sinusoidal waveform

x(k) = A sin(2πfi · kTs) Signal Power = Ps =12A2

The signal-to-noise ratio of y(k) is

SNR ≡Ps

Pn= 6 · A

2

∆2

When the input’s amplitude A = AF S/2, the SNR reaches its maximum value.

AF S = 2N∆ Ps =18· 22N∆2 SNRmax = 22N × 3

2= N × 6.02 dB + 1.76 dB


Dynamic Range

• The ratio between fs and fi should be irrational.

• In the discrete-time domain, noise power of e(k) is assumed to be uniformlydistributed between −Ωs/2 and +Ωs/2. The power density is ∆

2/(12Ωs).

• The spurious free dynamic range (SFDR) is the ratio of the fundamental signalcomponent to the largest distortion component when A = AF S/2.

• The signal-to-noise plus distortion ratio (SINAD) is the ratio of power of thefundamental signal to the total power of noise and distortion when A = AF S/2.

• The total harmonic distortion (THD) is the ratio of the total power of the 2nd and higherharmonic components to the power of the fundamental signal.

• In finding the total noise power, the noise bandwidth need to be specified.


Resistor-String DACs with Digital Decoding

oV

refV inD

N1

of

2D

eco

der

R

R

R

N

• Inherently monotonic.

• DNL depend on local matching of neighboring R’s.

• INL depends on global matching of the R-string.

• No resistive load at Vo.

• The worst-case time constant occurs a themidpoint of the R-string.

• Large capacitive loading at Vo.


Folded R-String DACs with Digital Decoding

oV

inD

refV

1 of 2 N-M Decoder

1 o

f 2

MD

eco

der

M

N-M N

(MS

Bs)


R-String DACs with Binary-Tree Decoding

Vref

Vo

R

R

R

R

R

R

R

R

00b b 1 1b b 2 2b b

• Require no digital decoder.

• Speed is limited by the delay throughthe resistor string as well as thedelay through the switch network.


Intermeshed Resistor-String DACs (One-Level Multiplexing)

Vref

Vo


Intermeshed Resistor-String DACs (Two-Level Multiplexing)

refV

oV



VBBBV

oI

V

N-1 I 0 I2 N-2 I2 2

N-2 0b b bN-1

Io = I ·(bN−1 · 2N−1 + bN−2 · 2N−2 + · · · + b1 · 21 + b0 · 20)



• Fast.

• Monotonicity is not guaranteed.

• Potentially large glitches due to timing skews.

• Latches are often used to synchronize bN−1, bN−2, . . . .

• Ro of the current sources can cause nonlinearity.

Io

in = 0111 Din = 1000D

Glitch

t


Binary-Weighted R-2R Networks

I2I4I8I

BV

I

2R 2R 2R 2R

2RRRR

8 I 4 I 2 I 1 I 1 I

16 I

16 I

x2x8 x4 x1 x1

VEE

R RR2R 2R 2R 2R 2R

• No wide-range scaling of resistors.

• BJT emitter-area scaling can be confined to the first few MSBs; and the voltage dropsin the emitter resistors should dominate the VBE (on) mismatches of the less significantbits.


Equally-Weighted Current-Steering DACs

V B

1 2

III

I

Din

-1N2

B

o

BV V

Binary- to-Thermometer DecoderN

• Inherently monotonic.

• Glitches are reduced. Synchronizing latches may be still required.


The Matrix Floorplan

N

M

Io

in

Ri

D

jC

DecoderRi

Cj

Local

Ro

w D

eco

der

Column Decoder

MSBs

LSBs

• Rj is a 2M − 1 thermometer code, and Cj is a 2N−M − 1 thermometer code.

• One example of the local decoding is S = Ri+1 + Ri · Cj .

• INL may exhibit the gradient of the unit cell’s variations.

• INL can be dithered by jumping selection of unit cells.


A Current Cell Example

tM3

SEL

SEL

CLK

M2M1V1

V

Io1 Io2

VB1V2

Va

2

V1

VSS

C

LocalDecoderi+1R

iR

j

• The current switch MOSTs, M1 and M2, are in the triode region when fully turned on.

• To minimize voltage fluctuation at Va, the inverters are sized so that the cross-overvoltage of the V1 and V2 transient waveforms can turn on both M1 and M2.

• Reference: C-H Lin and K Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2,”JSSC, 12/1998, pp. 1948–1958.



1

1

2

o

b

b

V

b

Vo

ref

2

V

V

b bb

b b

222

ref

2 2 2

2

C 2 C 1C 0C

N-1 C 2 C 1C 0C

NC

12 0

2 1 0

N-1

N-1

N-1 CpC



During φ1 = 1,Cap Bottom Plate @ GND Vo = 0

During φ2 = 1,

bi =

1 → Cap Bottom Plate @Vref0 → Cap Bottom Plate @GND

Vo = Vref ×C

2NC + Cp

×N−1∑i=0

bi2i

• Binary-weighted or equally-weighted capacitor array.

• Cp is top plate parasitic capacitance, and introduces a gain error.

• Opamp can be used to provide voltage gain and mitigate the effects of Cp.

• DACs at resolutions of 10 bits or above usually requires some kind of trimming orcalibration.


Segmented DAC Architecture

M-Bit DAC

L-Bit DAC

Din

A

N

Ao

AM

L L

M Din =N−1∑i=0

bi2i =

M−1∑i=0

bi+L2i+L +L−1∑j=0

bj2j

AM = ∆M ×M−1∑i=0

bi+L2i AL = ∆L ×L−1∑j=0

bj2j

N = M + L ∆M = 2L × ∆L

Ao = AM + AL = ∆L ×M−1∑i=0

bi+L2i+L + ∆L ×L−1∑j=0

bj2j = ∆L ×

N−1∑i=0

bi2i

• The M-DAC need to have ±∆L/2 accuracy.

• Signal path delay mismatch between the M-DAC and the L-DAC can cause glitch.

• Can have more than two segments.



Ro

w D

eco

der

Ro

w D

eco

der

Ro

w D

eco

der

Column Decoder Column Decoder

Column Decoder Column Decoder

Ro

w D

eco

der

Io

Io

B7-B9

B7-B9

8 x 8

8 x 8

8 x 8

8 x 8

B7-B9

B7-B9

B4-B6B4-B6 B0-B3

B4-B6B4-B6



• Segmented 6-2-2 architecture with common-centroid layout.

• Each current cell in the matrix contains 4 LSB current.

• Reference: J. Bastos, et. al., “A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC,”JSSC 12/1998, pp. 1959–1969.


A Segmented Current-Steering DAC

LM

C

N

I

Din

BV BV BV

o

VI I I4X 1X1X2X

L-DAC Binary DecoderM-DAC Thermometer Decoder

• Greatly reduces area for large N while ensuring monotonicity (at least for MSBs).

• The L-DAC can be a binary-weighted DAC if its glitches can be tolerated.

• Reference: H. Schouwenaar, et al., JSSC 12/88, pp. 1290–1297.



IB1

Cbr

MS1

Iref

VB1MS1D

MC1

M4

Out

M3

M2M1

B1I

Iref

OutIoIref

Out

V

Iref

Iref

Cbr

B2

C Cs C Css s

VSS

sVSS

VSS

VSS

sC

S1M1

Calibration

S1M1

Operation

Switch Array

C



• The bias voltage for the current sources is stored in each individual Cs. The voltageon Cs is refreshed periodically by means of calibration.

• A spare current source can be added to facilitate uninterrupted operation.

• Cs can be just the Cgs of M1.

• The switching error of MS1 as well as gm1 must be minimized.

• By adding M2 with a constant current, gm1 can be reduced.

• 16-bit resolution can be achieved using this technique.

• Reference: D. Groeneveld, et al., JSSC 12/89, pp. 1517–1522.


A Segmented Charge-Redistribution DAC

M-DAC

ib

V

V refV

222

ref

L-DAC

jb

Vx o

0C2 C1C

L

C

M

C C

Din =N−1∑i=0

bi2i N = M + L Vx =

Vref

2L·L−1∑j=0

bj2j

Vo =Vref

2M·M−1∑i=0

bi+L2i +1

2M· Vx =

Vref

2M+L·

M−1∑

i=0

bi+L2i+L +L−1∑j=0

bj2j

=

Vref

2N·N−1∑i=0

bi2i


A Capacitor-Resistor Hybrid DAC

M

M-DAC

L-DAC

b

22

oV

22

2

Vref

b refV

2

L

2 CC0C C

j

1 0CM-1

MC

i

Vo =Vref

2M×

M−1∑i=0

bi+L2i +1

2M×Vref

2L×

L−1∑j=0

bj2j =

Vref

2N×

N−1∑i=0

bi2i N = M + L


A Resistor-Capacitor Hybrid DAC

1

2

1

L-DAC

M

M-DAC

L

2V

b

oV

2

V

ref

2

V

22

b

L-1

j

C2 1C 0CC

i

L C

V1 = ∆M ×M−1∑i=0

bi+L2i V2 = V1 + ∆M ∆M =Vref

2MN = M + L


A Resistor-Capacitor Hybrid DAC

During φ1 = 1,Cap Bottom Plate @ GND Vo = 0

During φ2 = 1,

bi =

1 → Cap Bottom Plate @V2

0 → Cap Bottom Plate @V1

Vo = V1 +∆M

2L×

L−1∑j=0

bj2j =

Vref

2M×

M−1∑i=0

bi+L2i +Vref

2M+L×

L−1∑j=0

bj2j =

Vref

2N×

N−1∑i=0

bi2i

• The capacitor array interpolates the voltages between V1 and V2.

• Reference: J.-W. Yang, et al., JSSC 10/89, pp. 1458–1461.


Nyquist-Rate Analog-to-Digital Converters

Jieh-Tsorng Wu

November 13, 2002

A

1896



fs

fs

fs

DigitalProcessor

A/DInterface

D/AInterface

y(t)x(t) x(n) y(n)

WorldAnalog

D/A Deglitcher Inverse-Sinc / Low-PassFilter

y(n) y(t)

Converter

Digital-to-Analog Interface

FilterLow-Pass DecoderQuantizerSampling

Circuit

x(t) x(n)

Analog-to-Digital Interface

ADCs 25-2 Analog ICs; Jieh-Tsorng Wu


DACTimeDiscrete

ProcessingPrefilter

c (t)

Analog

d (t) ycx

Ts

Ts

c

y

x

T

(t)

2Ts3Ts

(t)

s

AnalogPostfilter

Sampling

y(n)x(n)

0

A

t0

2π0 4π

Ax(n)

0n

1 2 3

Ω

ω

Ωb Ωs 2Ωs

Xc(jΩ)

X(ejω)


A/D Quantization Characteristic

N-1 b 0

A i

A

b

1/2 i

1/2

A i

Do

b 1

Quantizer

(Analog Input)

(Digital Output)Quantization Error Q

100

111

000/ 2A FS A FS

Ai,tran = ∆ ×N−1∑i=0

bi2i − 1

2∆

AFS = Full-Scale Output ∆ = LSB = Step Size =AF S

2N


Imperfections in A/D Quantization Characteristic

NonlinearityGain ErrorOffset

A i

Do

A

o o

A ii

DIdeal Ideal IdealD

• Differential nonlinearity (DNL) : Maximum deviation in step width (width betweentransitions) from the ideal value of 1 LSB (= ∆).

• Integral nonlinearity (INL) : Maximum deviation of the step midpoints from the idealstep midpoints. Or the maximum deviation of the transition points from ideal.

• If DNL = −1 LSB⇒ missing code.


Quantization Noise

e

sf

/2

QuantizerN-Bit

/2

Probability Density Function (pdf)x(k)

y(k)x(t)

x(k) y(k)

e(k)

e(k) is a quantization noise due to the quantization process.


112

∆2


Quantization Noise

Let the input x(k) be a sinusoidal waveform

x(k) = A sin(2πfi · kTs) Signal Power = Ps =12A2

The signal-to-noise ratio of y(k) is

SNR ≡Ps

Pn= 6 · A

2

∆2

When the input’s amplitude A = AF S/2, the SNR reaches its maximum value.

AF S = 2N∆ Ps =18· 22N∆2 SNRmax = 22N × 3

2= N × 6.02 dB + 1.76 dB



2/(12Ωs).



t

V

fs

kTs

tx(t) x(k)

x(k) = x (kTs + ∆t) Ts =1fs

For a full-scale sinusoidal input

x(t) =12AF S sin(2πfit) AF S = 2N∆

∆V ≈ dx

dt× ∆t < AF S · πfi × ∆t <

12∆ ⇒ ∆t <

1

2N· 12πfi



Let x(t) = 12AF S sin (2πfit) and ∆t be a random variable, then

x(k) = x (kTs + ∆t) ≈ 12AF S sin(2πfikTs) +

dx(t)

dt

∣∣∣∣t=kTs

× ∆t

≈ 12AF S sin(2πfikTs) + AF Sπfi cos(2πfikTs) × ∆t

x2(k) =18A2F S

+12A2F S

π2f 2i× ∆t2 = Ps + Pn

The signal-to-noise ratio of x(k) is

SNR =Ps

Pn=

1

4π2f 2i· ∆t2

= −20 log (2πfi · ∆trms) dB

• If fi = 1 MHz, N = 14, SNR = 86 dB, want ∆trms < 8.0 psec.

• If fi = 100 MHz, N = 10, SNR = 62 dB, want ∆trms < 1.26 psec.



fif

dBm/Hzy(t) Power Spectrum

i

SFDR

fs

2f i3f

y(k)

Quantizer

x(k)DFTx(t) N-Bit

45

50

55

60

-15-20 -5-10-25

10 Bit

9 Bit

8 Bit

SINAD (dB)

040

Input Level Relative to Full Scale (dB)





2/(12Ωs).

• The spurious free dynamic range (SFDR) is the ratio of the fundamental signalcomponent to the largest distortion component when A = AF S/2.

• The signal-to-noise plus distortion ratio (SINAD) is the ratio of power of thefundamental signal to the total power of noise and distortion when A = AF S/2.

• In finding the total noise power, the noise bandwidth need to be specified.



t

fs

x(t)

W(i)

QuantizerD

o

o

D

iA

N-Bitx(k)x(t) Histogram

y(k)

H(i)



Let Nt be the total number of samples, H(i ) the number of counts in the i -th Do, and P (i )the ideal probability for the i -the Do. We have

W (i )

∆=(Ai+1,tran − Ai,tran

)· 1∆

=H(i )

Nt

· 1P (i )

• For high precision, sinusoidal waveform is usually for the input. The probability densityp(V ) for A sin(ωt) is

p(V ) =1

π√A2 − V 2

• To test a 12-bit ADC, for 99 percent confidence and 0.10 bit precision, 4.2 millionsamples are needed.

• Reference: Doernberg, JSSC 12/84, pp. 820–827.



x

iV

fV

RCiV

RCrefV

TT

VrefVx Logic

Control

1 2

c

Do

Counter

R1

C1

S2

S1

t



The output isDo

fc= T2 = T1 ·

Vi

Vref

• Linear search of possible subregions.

• Integrating types: single slope, dual slope, quad-slope.

• Low conversion rate. Requires 2 × 2N clock cycles for a full-scale conversion.

• The input is integrated in the T1 period, resulting in a filer transfer function of

|H(f )| =∣∣∣∣sin(πT1f )

πT1f

∣∣∣∣



N221

V

-2 2

oD

refV

N-1

i

2N-1( ) - to - N Encoder

N



• All subregions are examined simultaneously. One comparator per subregion.

• Using 2N−1 comparators, the input is simultaneously compared with 2N−1 referencevoltages derived from resistor string.

• High speed. Requires only one comparison cycle per conversion.

• Large size and power dissipation for large N.

• Design issues: input capacitive loading, clock jitter and dispersion, slew-dependentsampling point, nonlinear input capacitance, resistor-string dc and ac bowing,substrate and power-supply noises, kickback noises, sparkles in thermometer code.

• Gray encoding is often used as an intermediate step between thermometer and binarycodes.



N

Do

Vi

Vref

VDA

FS

CLK

DA

V

V

N-1 =1 b =1N-3b

=1=0N-2 b N-4

V

Control

b

i

Logic

DAC 1/2 3/4 5/8 7/16

t



• Binary search of possible subregions.

• Fraction of VF S corresponding to each bit is successively (starting with MSB) addedto fraction corresponding to already determined bits and sum is compared to input.

• N comparisons per conversion.

• Requires a high-speed DAC with precision on the order of the converter itself.

• Excellent trade-off between accuracy and speed.


Charge-Redistribution ADC

2

S

SSSSS

S

i

V

V

22 2

1

2

refrefV

xV

2

pC

C1 C0A C0BC2

x

LSBMSB

N-1 2 1 0A 0B

i

00 CC1C2CN-1 CCN-1

Ctot =N−1∑i=1

2iCi + C0A + C0B = 2NC


Charge-Redistribution ADCs

Sample Mode

• Sx → GND. Vx = 0.

• S0A, S0B, S1, S2, · · · , SN−1, Si → Vi .

Hold Mode

• Sx open.

• S0A, S1, S2, · · · , SN−1→ GND.

• S0B → −12Vref , sets transition offset to 1

2∆.

Vx = −Vi −C0B

Ctot

·Vref

2= −Vi −

12·Vref

2N∆ =

Vref

2N



Redistribution Mode

• Si → Vref .

• Test bits one at a time in succession, beginning with bN−1.

Bit bN−1 Test

• SN−1→ Vref

Vx = −Vi −12

Vref

2N+CN−1

Ctot

· Vref = −Vi −12·Vref

2N+Vref

2

• If Vx < 0, bN−1 = 1, SN−1→ Vref .If Vx > 0, bN−1 = 0, SN−1→ GND.



Bit bi Test, i = N − 2, N − 3, · · · ,0

• Si → Vref

Vx = −Vi −12

Vref

2N+Vref

2N

N−1∑j=i+1

bj2j +

Ci

Ctot

· Vref = −Vi −12·Vref

2N+Vref

2N

N−1∑

j=i+1

bj2j + 2i

• If Vx < 0, bi = 1, Si → Vref .If Vx > 0, bi = 0, Si → GND.

The effect of parasitic capacitance, CP

• The voltage on the summing node becomes V′x = Vx ·

Ctot

Ctot+Cp.

• Cp has no effect on the A/D quantization characteristic, if the comparator is ideal.

• CP does attenuate Vx, thus requiring higher comparator gain.


C-R ADCs Using Input O ffset Storage Technique

S

OSV

xV

x

A

Capacitor Array

• Non-zero comparator offset can be cancelled by referencing Vx to the offset, ratherthan GND during sampling.



M-12 12 02

x

C

S

CC

x

Do

C

xVV

20

V

ControlApproximation

Successive

x

M-1 1 0 0C

Calibration DACL-DAC

ControlCalibration

RegisterData

EN-i

(b) Switch(a) Initialize

CC C C

<

=

>

A B A B

C C

C C

C C

A B

A B

A B

V Vref ref

Calibration Basic Concept

M-DAC

t



• The error voltage Vx, thus the capacitor mismatch, can be digitized by the CalibrationDAC.

• During the calibration, the capacitor mismatches in CM−1, CM−2, · · · , C0 are measuredsequentially, and stored in the data register.

• During the normal operation, the calibration DAC generate a correction voltage thatcompensates the error voltage caused by the mismatches in the capacitor array

• The binary-weighted capacitor array has an accuracy of about 10 bits. With self-calibration, 16-bit resolution is possible.

• Reference: H-S Lee, JSSC 12/84, pp. 813–819.



LetCtot = CM−1 + CM−2 + · · · + C1 + C0 + C0C + Cp

Capacitor CM−1 calibration

CA = CM−1 ≡12Ctot + ∆CM−1

CB = CM−2 + · · · + C1 + C0 + C0C =12Ctot − ∆CM−1

Vx = −Vref ·CA − CB

Ctot

= −Vref ·2∆CM−1

Ctot

• Using the C-DAC to digitize Vx, we obtain Dx.

• Store EM−1 in the data register as

EM−1 =12Dx = −Vref ·

∆CM−1

Ctot



Capacitor CM−2 calibration

CA = CM−2 ≡14Ctot + ∆CM−2

CB = CM−3 + · · · + C1 + C0 + C0C =14Ctot − ∆CM−1 − ∆CM−2

Vx = −Vref ·CA − CB

Ctot

= −Vref ·∆CM−1 + 2∆CM−1

Ctot


• Store EM−2 in the data register as

EM−2 =12

(Dx − EM−1

)= −Vref ·

∆CM−2

Ctot



Capacitor Ci calibration, i = M − 2,M − 3, · · ·

CA ≡1

2M−iCtot + ∆Ci

CB =1

2M−iCtot −

M−1∑j=i+1

∆Cj − ∆Ci

Vx = −Vref ·∑M−1

j=i+1 ∆Cj + 2∆Ci

Ctot


• Store Ei in the data register as

Ei =12

Dx −

M−1∑j=i+1

Ej

= −Vref ·

∆Ci

Ctot



During normal operation, the Vx generated by the M-DAC is

Vx = Vref

M−1∑0

(bi+L ·

Ci

Ctot

)

The Vx is corrected by the C-DAC as

V cx = Vx +

M−1∑i=0

(bi+L · Ei) = Vref

M−1∑0

(bi+L ·

Ci

Ctot

)− Vref

M−1∑i=0

(bi+L ·

∆Ci

Ctot

)

= Vref

M−1∑i=0

(bi+L ·

Ci − ∆Ci

Ctot

)

=Vref

2M

M−1∑i=0

(bi+L · 2i

)


Quantized-Feedforward (Subranging) Architectures

DjAj )(

jA j+1A

jD

jG

da

(+2)adA(+1)adA(-1)adA

1D

oD

D

PStage

P2D

21StageStage

0

0

ADC

MSBs LSBs

Encoder

A i

jA

j+1A

DAC



The relationship between Aj and Aj+1 is

Aj+1 =[Aj − Ada

j(Dj)]· Gj ⇒ Aj = Ada

j(Dj) +

Aj+1

Gj

The input Ai can be expressed as

Ai = Ada1 +

Ada2

G1+

Ada3

G1G2+ · · · +

AdaP

G1G2 · · ·GP−1+

AP+1

G1G2 · · ·GP

• If Adaj (Dj) and Gj are known, Ai can be computed from D1, D2, · · · , DP .

• The term, Q = AP+1/(G1G2 · · ·GP ), is the conversion error (quantization error).

• Aadj has no effect on the A/D result.

• Gj may include sample-and-hole function for pipeline or cyclic operation.



If the Gj amplifier has dc offset, i.e.,

Aj+1 =[Aj − Ada

j(Dj) − Aos

j

]· Gj ⇒ Aj = Ada

j(Dj) + Aos

j+Aj+1

Gj

The input Ai can be expressed as

Ai = Ada1 +

Ada2

G1+

Ada3

G1G2+ · · · +

AdaP

G1G2 · · ·GP−1+

AP+1

G1G2 · · ·GP

+ Aos

The entire system has an dc offset of

Aos = Aos1 +

Aos2

G1+

Aos3

G1G2+ · · · +

AosP

G1G2 · · ·GP−1

• Ref: E. Soenen and R. Geiger, “An Architecture and An Algorithm for Fully DigitalCorrection of Monolithic Pipelined ADC’s,” IEEE CAS II, pp. 143–153, March 1995.


Quantized-Feedforward Minimal Design

A jA j

A j+1 A j+1+1

0

-1

G = 2

ADC

+1

-1ADC

-1/2

+1/2

0

G = 4

DAC -1 +1DAC +1-1 0

+1/2

-1/2

0

G = G1 = G2 = · · · = GP = integer ∆A =2G

Q =AP+1

G1G2 · · ·GP

<1

GP

Effective Number of Bit = N = log21

Qmax

= P × log2 G

• There are M = G − 1 comparators in the ADC. G is preferred to be power of 2.

• Dj has M + 1 different values, and the DAC has corresponding M + 1 different outputvalues.


Over-Range in the Minimal Design

Assume nonideal ADC, DAC, and G, as

Aadj

= Aadj

+ εadj

Adaj

= Adaj

+ εdaj

Gj = Gj ×(

1 + εgj

)

Then we have

Aj+1 =[Aj − Ada

j(Dj) + (εad

j− εda

j)]· Gj =

[Aj − Ada

j(Dj )]· Gj + OR

The over range, OR, is

OR =[Aj − Ada

j(Dj)]ε

gjGj + (εad

j− εda

j) · Gj ≤ ε

gj+ (εad

j− εda

j) · Gj

• Nonideal ADC, DAC, and G, can cause Aj+1 in minimal design stretching over thenominal input range of the j + 1 stage.


Quantized-Feedforward Redundant Design

A j A j

A j+1 A j+1+1

-1

-1/2

+1/2

0

Minimal+2

+1

Minimal+1

DAC

-3/4

-1/4

+1/4

+3/4

ADC DAC ADC+1-1 0 -1 0

• To increase the nominal input range, one can increase M, the number of comparatorsin the ADCs, and the corresponding output levels in the DACs.

• The minimal+2 design provides an over-range capability of ±∆A. The minimal+1design provides an over-range capability of ±∆A/2.

• It is also possible to avoid the over-range phenomenon by decreasing Gj .



Table

P+1

D1

1C

G1d

2A AA

3

3

C

Table

D

2Stage

P

P

Gd2

3

C

Table

D

Stage

2C

Table

2D

2Stage

P1Stage

iA

oD

Ai = Ada1 +

Ada2

G1+

Ada3

G1G2+ · · · +

AdaP

G1G2 · · ·GP−1+ Q

(Ai − Q) · Gd1 G

d2 · · ·G

dP−1

=

(((Ada

1

)Gd

1 + Ada2

Gd1

G1

)Gd

2 + Ada3

Gd1 G

d2

G1G2

)Gd

3 + · · · + AdaP

Gd1 G

d2 · · ·G

dP−1

G1G2 · · ·GP−1



Let

Cj = Adaj

(Dj ) ·G

d1 G

d2 · · ·G

dj−1

G1G2 · · ·Gj−1

The digital output can be obtained by

Do =((

(C1)Gd1 + C2

)Gd

2 + · · · + CP−1

)Gd

P−1 + CP

• Nonlinear A/D conversion occurs, if

Cj = Adaj

(Dj) ·G

d1 G

d2 · · ·G

dj−1

G1G2 · · · Gj−1


A Radix-2 1.5 Bit SC Pipeline Stage

Vj

1

1

2Vr x D j

2

1Vj+1

Vj

Vr x D j

Vj+1

Vj+1

A j

Vr0.25Vr0.25Vr0.75 Vr0.75

A j+1

Vr0.25

Vr0.5

Vr0.5

Vr0.25

D j

Vr0.25 Vr0.25

= −1, 0, +1D j

Conversion Phase 2

Conversioin Phase 1

C

0

0 0

1

1

DACADC

Minimal+1

C

C

f

g C

C

C

Cf

g

g

f

L

Encoder


A Radix-2 1.5 Bit SC Pipeline Stage

During phase 2

Vj+1 = Vj +C

g

Cf(Vj − Vr × Dj) =

(1 +

Cg

Cf

)(Vj −

Vr

1 + Cf/Cg× Dj

)

= 2 ×(Vj −

Vr

2× Dj

)if Cf = Cg

• The full range of the input/output is ±0.5Vr .

• The pipeline stage has input over-range capability of ±0.25Vr .


Multi-Bit Switched-Capacitor Pipeline Stage

Vj

g0

g1

C

1jD

0jDx

1f

rV

C

xrV

C

BankComparator

2

1j+1V

1

D

2

2

j

1

Dj = D0j· 20 + D1

j· 21 + · · ·DK

j· 2K−1 Dk

j∈ −1,0,+1

Cf

20=

Cg0

20=

Cg1

21= · · · = C

g(K−1)

2N−1= C

Vj+1 = Gj ×(Vj − ∆V × Dj

)Gj = 1 +

Cg0 + C

g1 + · · · + Cg(K−1)

Cf= 2K ∆V =

Vr

2K



The SC stage has a voltage gain of

G = 1 +C

g

CfCg = Cg0 + Cg1 + Cg2 + · · ·

The settling time requirement can be expressed as

Ts =C

f + CL

Gm

(1 +

Cg

Cf+

Ci

Cf

)· ln 2y+1 ⇒ Gm =

Cf + C

L

Ts

(G +

Ci

Cf

)· (y + 1) ln 2

Other constraints are

Total Power ∝ Gm,1 + Gm,2 + · · · + Gm,P

Total Input Referred Thermal Noise Power = Pθ ∼ kT

[1

Cs1

+1

(G1)2Cs2

+1

(G1G2)2Cs3

· · ·]



• Gm is the opamp’s transconductance.

• Ci is the opamp’s input capacitance.

• Csj = C

fj + C

g

jis the j -stage sampling capacitances.

• CL includes C

sj+1 and input loading of the comparator bank in the j + 1 stage.

• y (bits) is the resolution requirement of the j stage.

• Use capacitor scaling, α = Csj /C

sj+1, total power dissipation can be minimized while

maintaining noise performance. It can be shown that αopt ∼ G.

• Increasing G (and M) per stage generally reduces total power dissipation.

• Reference: D. Cline and P. Gray, “A Power Optimized 13-b 5Ms/s Pipelined ADC,”JSSC, March 1996, pp. 294–303.


Single-Stage Calibration and Digital Correction

0

1

CAL

c

ADC

Ajda

A

0

1

CAL

jA

jG

cD

jD

j+1A

zD

Z

DACADC

The signal Aj+1 is quantized the following Z-ADC with

Aj+1 = Gj ·[Aj − Ada

j(Dj) − Aos

j

]=

G

G· Dz + Qos + Q

• G/G is the gain error, Qos is the offset, and Q is the quantization error.



During calibration, Aj is disabled and Adaj (Dc) is quantized by measuring

Gj ·[Ac − Aos

]=

G

G· Dz1 + Qos + Q1

Gj ·[Ac − Ada

j(Dc) − Aos

]=

G

G· Dz2 + Qos + Q2

Subtracting the above two equations, we have

Gj · Adaj

(Dc) =G

G· (Dz1 − Dz2) + Q1 −Q2 =

G

G· Dz(Dc) + 2Qc(Dc) Dc ∈ Dj

⇒ Adaj

(Dc) =GjG

GjG· Tj(Dc) +

2Qc(Dc)

Gj

Tj(Dc) =Dz(Dc)

Gj

Dc ∈ Dj



The combined ADC with j-Stage and Z-ADC has the following characteristic:

Aj = Adaj

(Dj) + Aosj+Aj+1

Gj

=GjG

GjG· Tj(Dj) +

2Qc(Dj)

Gj

+ Aosj+Aj+1

Gj

=GjG

GjG

[Tj(Dj) +

Dz

Gj

]+

(Aosj+Q

os

Gj

)+

2Qc(Dj) +Q

Gj

=G′

G′· D′z + Q′os +Q′

Digital Output = D′z = Tj(Dj) +Dz

Gj

Gain Error =G′

G′=

GjG

GjG

Offset = Q′os = Aosj+Q

os

Gj

Quantization Error = Q′ =2Qc(Dj)

Gj

+Q

Gj

• Nonideal Adaj and Gj have no effect on the A/D linearity.


Multi-Stage Calibration and Digital Correction

DP-1D1

1T

G1d

X

x

xTTP-1T

P-1

Table

D

Stage

P

P

P

Table

AP+1

GdP-1 Gd

P

StageAP

D

Stage

T

Table

2A

2

Table

2D

2Stage

1Stage

Table

D

i Q xA

o

Assume the stage X ADC has a characteristic of

AP+1 =Gx

Gx

· Tx + Qosx + Qx

• Calibration is performed stage-by-stage, from Stage P to Stage 1.



Use the X ADC to calibrate stage P . Then, the P + X ADC can be expressed as

AP =GPGx

GP Gx

[TP +

Tx

GP

]+

(AosP+Q

osx

GP

)+

2Qcx,P + Qx

GP

Use the P + X ADC to calibrate stage (P − 1). Then, the (P − 1) + P + X ADC can beexpressed as

AP−1 =GP−1GPGx

GP−1GP Gx

[TP−1 +

TP

GP−1+

Tx

GP−1GP

]

+

(AosP−1 +

AosP

GP−1

+Q

osx

GP−1GP

)+

2Qcx,P−1 + 2Qc

x,P +Qx

GP−1GP

Repeat the calibration procedures for stage (P − 2), (P − 3), . . . , 2, and 1.



The full calibrated ADC can be expressed as

Ai =GT

GT

[T1 +

T2

G1+ · · · +

TP

G1G2 · · ·GP−1+

Tx

G1G2 · · ·GP

]+Qos

T+QT

where

GT

GT

=G1G2 · · ·GPGx

G1G2 · · · GP Gx

QosT

= Aos1 +

Aos2

G1

+ · · · +A

osP

G1G2 · · · GP−1

+Q

osx

G1G2 + · · · GP

QT =2Qc

x,1 + 2Qcx,2 + · · · + 2Qc

x,P + Qx

G1G2 · · · GP

≤(2P + 1) × |Qx|max

G1G2 · · · GP



• The scaling factor GT/GT and offset QosT can be determined by quantizing two known

input, e.g., Ai = 0 and Ai = Aref .

• The effects of noise can be suppressed by averaging a number of successivemeasurements during calibration.

• During j stage calibration, to avoid overloading the Aj+1 port, different Adaj (Dc)

measurement may need different Ac value.

• On the circuit level, the effectiveness of calibration is limited by noises, interferences,nonlinear Gj , and amplifier transient behavior.


Calibration of A Radix-2 1.5 Bit SC Pipeline Stage

Vj

1

1

2Vr x D j

2

1Vj+1

Vc Vj+1

Vj+1

Vr x Dc

Vr0.25 Vr0.25

= −1, 0, +1D j

C

C

f

g

Calibration Phase 1

C

C

g

f

CC

Cf

g

Calibration Phase 2

L

Encoder

• To calibrate Adaj (Dj = 1). Obtain Dz1 by letting Vc = 0.25Vr and Dc = 0, and obtain Dz2

by letting Vc = 0.25Vr and Dc = 1. Then Tj(Dj = 1) = (Dz1 − Dz2)/Gj .

• To calibrate Adaj (Dj = −1). Obtain Dz1 by letting Vf = −0.25Vr and Dc = 0, and obtain

Dz2 by letting Vc = −0.25Vr and Dc = −1. Then Tj(Dj = −1) = (Dz1 − Dz2)/Gj .


A Radix-2 Cyclic ADCs

jD

Vi

VR VR

j+1 VjVx 2S/H

Vj+1 = 2 × Vj − Dj × VR = 2 ×(Vj + Dj ·

VR

2

)Dj ∈ +1,−1

• Start with j = 1 and V1 = Vi .

• For each cycle, j is increased by 1.



S2

S1Vi

C1

1A

C6

S4

2

VR C3C5

2

C S6

S3 4

Dj

C

3A

S5

A

C1 = C2 = C3 = C4 = C

C5 = 2C

Dj ∈ 1,0

Vi = VR ×

N∑

j=1

(Dj · 2−j

)− 1

2



Dj+1

j-Cycle (2)j-Cycle (1)

Input Sampling (2)Input Sampling (1)

C1

1A

C6

C3C5

3A

D1

C2

C1

A

1A

C6

3

V

4C C

V

x RVj

C3C5

5

2

3A

Dx RVjD

3

Vi

3

3C

A

2A

C

1

6

A

C

j

2A

1

2A

A

5C

6

C

A

C

2

C1

C

1 j+1


A CMOS Subranging Flash ADC — Dingwall

M-ADC

Comparator BankL-ADC

RV

KV KV

iV

Comparator Bank

11

2

3 1

1

3 1

1

3 1

1

3 1

1

1

2

1

1

2

1


A CMOS Subranging Flash ADC — Dingwall

• Two-Stage quantized-feedforward architecture.

– The first-stage M-ADC has 2M − 1 comparators, and G1 = 1.– The second-stage L-ADC has 2L − 1 comparators.– For minimal design, Do has N = M + L bits.

• The S/H and the subtractor function is embedded in every comparator. Require noadditional subtractor or DAC.

• Comparators in both M-ADC and L-ADC need to have N-bit accuracy.

• The input range of the L-ADC can be extended to prevent over-loading. The accuracyrequirement for the M-ADC can then be relaxed.

• Reference: A. Dingwall, et. al., “An 8-MHz CMOS Subranging 8-Bit A/D Converter,”JSSC 12/1985, pp. 1138–1143.


A CMOS Subranging Flash ADC — Brandt


Interpolated Di fferential Comparator Bank


A CMOS Subranging Flash ADC — Brandt

• Two-stage quantized-feedforward differential architecture.

• The voltage ranges are Cin+ − Cin− = [−2↔ +2] and Fin+ − Fin− = [0↔ +2].

• The absolute-value processing reduces the number of switches in the AMUXs by half.In addition, the settling time of the AMUX outputs is also reduced due to the reductionin output voltage swing and output capacitive loading.

• The interpolation scheme can reduce the number of “taps” from the reference ladderand reduce the number of preamplifiers. It also attenuates front-end sources of DNL,such as mismatches in the input sampling switches and resistor mismatch in thereference ladder.

• Reference: B. Brandt, et. al., “A 75-mW, 10-b 20-MSPS CMOS Subranging ADC,”JSSC 12/1999, pp. 1788–1795.


Flash Quantization Architecture

7530 1

Thermometer Code

11111111

11111110

11111100

11111000

11110000

11100000

11000000

10000000

00000000

7

6

5

Vi

VRB VRT

oDN

V2 V4 V6V0

V0 V6

Vi

V2 V4

4

3

2

4

1

6

1

2

0

0 2 3 4 5 6 7

Thermometer-to-Binary Encoder


Resistor-String Interpolation

Thermometer Code

11111111

11111110

11111100

11111000

11110000

11100000

11000000

10000000

00000000

7

6

5

4

3

2

1

0

Thermometer-to-Binary Encoder

7

Vi

VRB6543210

60 42

VRT

oDN

V2 V4 V6V0

V0 V6

Vi

V2 V4


Folding

0000

0001

0011

0111

1111

1110

1100

1000

0000

Circular Code

7

6

5

4

3

2

1

0

NCircular-to-Binary Encoder

Vi

VRTVRB

0 65 3 7

oD

4

8

V2V1V0 V3

V0 V1 V2 V3

Vi

7654

1 2

0 1 2 3


Interpolation and Folding

• The number of latch comparators is reduced by folding, while the number of foldingblocks is reduced by interpolation.

• The interpolation can reduce the input capacitances for Vi , VRT , and VRB, since thenumber of the preamplifers is reduced.

• The interpolation can improve the DNL, due to the redistribution of mismatch errors.

• The interpolation technique can also be used with other types of signals, such ascurrents and charges.

• The folding circuit need only to be accurate near the zero-crossing points.


Averaging Preamplifiers

I

R R R R

R RRR

I I

VSS VSS VSS

VDDVDD VDD

• The outputs are connected by interpolating resistor string.

• Gain is determined by R × I .

• Speed is determined by R × C.


Effects of Averaging

Input and Reference R-String

m = 5

Input Range

I o

Vi

Averaging R-String

• Differential nonlinearity (DNL) improves with m.

• Integral nonlinearity (INL) improves with√m.


Bending at the Edges Due to Averaging

Vi

Do

Averaging R-String


Use Resistor-Ring to Mitigate Edge Effect


Cascaded Folding

Vi

Dc


Averaging Resistor Ring and 3X Folding

Averaging Resistor Ring and 3X Folding

M-ADC

• Too many folding in one stage can cause gain-loss.

• Require odd number of single-stage folding to maintain continuity.


Differential Preamplifier

M7

M2M1

oV

M6M5 M4M3

BNV

Vi

VSS

VDD

Adm = gm1 ·1

gm3 − gm5

Acm =gm1

1 + 2gm1ro7· 1gm3 + gm5

• Additional common-mode feedback is not required.


A CMOS 10-Bit Folding ADC — Bult

• Reference: K. Bult, et. all, “An Embedded 240-mW 10-b 50-MS/s CMOS ADC in1-mm2,” JSSC 12/1997, pp. 1887–1895.


Time-Interleaved Architectures

φ

φ

1

φ

φ2

Nt

φφ

m

S/H21

Do

A i

S/H

m

S/H

cT

m

N N

Multiplexer

ADC ADC

1

N

ADC

2

• The equivalent sampling rate is m/Tc.

• Clock phase as well as clock jitter need to satisfy N-bit accuracy.

• Any mismatch among the converter characteristics, including offset and gain, canappear as noises and/or spurious tones in Do.


Oversampling Converters

Jieh-Tsorng Wu

July 16, 2002

A

1896


Sampling and Quantization

e(k)f s

f Bf B

S e (f)

f s /2f s /2

Quantizer

N−Bit

x(k)

x(k) y(k)

e(k)

x(t)

/2 /2

pdf of e(k)

0f

y(k)D(z)

D(z)

| D(f) |

e(k) is a quantization noise due to the quantization process. With an ideal quantizer withstep size ∆, The pdf of e(k) is assumed to be uniformly distributed over −∆/2 and +∆/2.


112

∆2

Oversampling 26-2 Analog ICs; Jieh-Tsorng Wu

Oversampling

Assume the noise e(k) is white and is independent of fs, then the noise spectral densityis

Sn(f ) =Pn

fs=

112

∆2 × 1fs

For a full-scale sinusoidal input

x(k) =12A sin(2πfi · kTs) A = 2N∆ Signal Power = Ps =

18· A2 =

18· 22N∆2

Assume the bandwidth of x(k) is limited to fB. The oversampling ratio, OSR, is definedas

OSR =fs

2fBThe noise at the output of D(z) filter is

P ′n =∫ +fB−fB

Sn(f ) · df =112

∆2 ×2fBfs


Oversampling

The signal-to-noise ratio of y(k) becomes

SNRy,max ≡Ps

P ′n=

32× 22N ×

fs

2fB= 1.76 + 6.02 ·N + 10 log(OSR) dB

• Oversampling gives a SNR improvement of 3 dB/octave or 0.5 bit/octave.

• High-speed digital filters, D(z), are required.

• Oversampling also eases the anti-alias filter design for x(t).

• Oversampling does not improve linearity. Linear quantizers are still required.

• One-bit quantizers and one-bit DACs are inherently linear. Therefore, they are oftenused in oversampling converters.


First-Order ∆Σ Modulator

y(k) y(k)Integratorx(t)

D/A

x(k) 1zu(k)

e(k)

Signal Transfer Function = STF (z) =Y (z)

X (z)= z−1

Noise Transfer Function = NTF (z) =Y (z)

E (z)= 1 − z−1

The noise transfer function in frequency domain is

NTF (f ) = NTF (z)|z=ej2πf /fs = sin(πf

fs

)× 2j × e−jπf /fs

• Noise power is small near f = 0 and becomes large near f = fs/2.


First-Order ∆Σ Modulator

The quantization noise power in the fB frequency band is

P ′n =∫ +fB−fB

Se(f )|NTF (f )|2df =∫ +fB−fB

∆2

121fs

[2 sin

(πf

fs

)]2

· df

If OSR 1, then

P ′n ≈∆

2

12· π

2

3

(2fBfs

)3

=∆

2π

2

361

OSR3

SNRy,max ≡Ps

P ′n=

9

2π2× 22N ×OSR3 = −3.41 + 6.02 · N + 30 log(OSR) dB


• The integrator’s output is u(k +1) = x(k)−e(k). If x is a dc input and bounded by thefull range of D/A, then |e| < ∆/2 and |u|max = |x| + ∆/2.


First-Order ∆Σ Modulator with SC Circuit Implementation

V R

CAC1

C2

V i2

2

1

2

1

y(n)

12,

1, 2

• One-bit ∆Σ modulator. VR = ∆/2.

• The comparator latches on the falling edge of φ2. The output y(n) ∈ +1,−1.

• C1 and C2 can be combined into one capacitor.



For an ideal integrator H(z), we have

H(z) =z−1

1 − z−1STF (z) =

H(z)

1 + H(z)= z−1 NTF (z) =

11 + H(z)

= 1 − z−1

• If the integrator includes a gain factor G, then

H(z) = G × z−1

1 − z−1STF (z) =

Gz−1

1 − (1 − G)z−1NTF (z) =

1 − z−1

1 − (1 − G)z−1

– Small deviations of G from unity have little effect on the overall performance,provided the net gain in the feedback loop is large.

– 10% gain accuracy of G is tolerable.



• If the opamp has a finite gain of Ao, then

H(z) ≈ z−1

1 − βz−1where β = 1 − 1

Ao

STF (z) =z−1

1 + (1 − β)z−1NTF (z) =

1 − βz−1

1 + (1 − β)z−1

– NTF (f ) is flat for 2πf /fs < 1/Ao.– Want fB fs/(2πAo) or Ao OSR/π.– Usually want Ao > 2OSR.

• Noises or harmonics arising from the quantizer’s nonlinearity are suppressed byNTF (z), making the quantizer less critical.

• The linearity of the D/A is very important.


Second-Order ∆Σ Modulator

z 1

z 1

u 1

u 2x(k) y(k)

D/A


STF (z) =Y (z)

X (z)= z−1 NTF (z) =

Y (z)

E (z)=(1 − z−1)2

The noise transfer function in frequency domain is

|NTF (f )| =[

2 sin(πf

fs

)]2


Second-Order ∆Σ Modulator

If OSR 1, the quantization noise power is

P ′n ≈∆

2π

4

601

OSR5

And

SNRy,max =15

2π4× 22N ×OSR5 = −11.14 + 6.02 ·N + 50 log(OSR) dB



Integration Range in a Second-Order ∆Σ Modulator

The outputs of the integrators are

u1(k + 1) = x(k) − e(k) + e(k − 1) u2(k + 1) = x(k − 1) − 2e(k − 1) + e(k − 2)

For multi-bit quantization:

• For small |x|, e is bounded by ±∆/2.

• If |e| < ∆/2, then

|u1| ≤ |x(k)| + |e(k)| + |e(k − 1)| ≤ |x| + ∆

|u2| ≤ |x(k)| + 2|e(k = 1)| + |e(k − 2)| ≤ |x| + 32∆


Integration Range in a Second-Order ∆Σ Modulator

• One-bit quantization.

• D/A output levels are ±1.

• The integrators are boundedby

|u1|max = |x| + 2

|u2|max =(5 − |x|)2

8(1 − |x|)

• In practice, the first accumulation is often clipped at ±2, and the second effectively±4.


Overloading in a Second-Order ∆Σ Modulator

• D/A levels are ±0.5,±1.5, and ±2.5.

• ∆ is the same for allthree cases.

• For large x, the input to the quantizer can be so large that |e| > ∆/2. The excessnoise can degrade the SNR of y .

• In the two-level case (1-bit quantization), the comparator is theoretically overloadedfor all conditions, except zero input with zero initial conditions.


Oversampling ADCs

Sampling

x c (t)

x c (t)

yp (n)y(n)x(n)

AliasingAnti−

Filter Modulator∆Σ Digital

Low−PassFilter

Decimation Filtersf

0t

0 sss2T 4T 6T

y (n)b

L

0 2π

x(n)

0n

1 2 3 4 5 6

Ω

ω

Ωb Ωs

Xc(jΩ)

X(ejω)


Oversampling ADCs

yp (n)

0 2π

0 2π 4π

0n

0n

1 2 3 4 5 6

321

y (n)b

y(n)

0 2π

n

ω

ω

ω

Y(ejω)

Yp

(ejω)

Yb

(ejω)


Oversampling DACs

D/A

(n)xp

x b (n)

Digital

FilterAnalog

yc (t)y (t)y(n)

Modulator∆Σ

Filter

InterpolationLow−Pass

x(n)

00n

321

(n)xb

2π

0 2π 4π0

x (t)p

1 2 3 4 5 6n

d

L

sf

ω

ω

Xb

(ejω)

Xp

(ejω)


Oversampling DACs

s2T s4T s6T

0n

x(n)

1 2 3 4 5 6 0 2π

0 2π

0

t

d (t)y

0

n

y(n)

Ω

ω

ω

X(ejω)

Y(ejω)

Ωb Ωs

Yd (jΩ)


Oversampling DACs

s2T s4T s6T

0 2π

0t

0

c (t)y

0

t

d (t)y

0

n

y(n)

Ω

Ω

ω

Y(ejω)

Ωb

Ωb

Ωs

Ωs

Yd (jΩ)

Yc(jΩ)


General Single-Stage ∆Σ Modulator

y(k)x(k) G(z)

F(z)

Y (z) =G(z)

1 + F (z)G(z)· X (z) +

11 + F (z)G(z)

· E (z) = STF (z) · X (z) +NTF (z) · E (z)

• OSR is typically between 16 and 256.

• The loop gain, L(z) = F (z)G(z), need to be high in the band of interest.

• The poles L(z) are the zeros of NTF (z).

• Both STF (z) and NTF (z) generally share the same poles, the roots of 1 + L(z) = 0.


General Single-Stage Error-Feedback Coder

y(k)x(k)

e(k)N(z) − 1

Y (z) = X (z) + N(z) · E (z)

• A slight coefficient error can degrade noise-shaping significantly.

• Not suitable for analog modulators, only appropriate for digital modulators.



z 1z 1

1 z 1z 1

1 z 1z 1

1

5a

z 1z 1

1z 1z 1

1x(k)

aaaa 1 2 3 4

1 2

y(k)

c c

• An Nth-order noise-shaping modulator improves the SNR by (6N + 3) dB/octave, orequivalently, (N + 0.5) bits/octave.



If c1 = c2 = 0,

L(z) = G(z) =a1

(z − 1)1+

a2

(z − 1)2+

a3

(z − 1)3+ · · ·

NTF (z) =1

1 + L(z)=

(z − 1)n

D(z)STF (z) = 1 − NTF (z)

• L(z) has all its poles at z = 1 (or f = 0).

• NTF (z) has all its zeros at z = 1 (or f = 0).

• Butterworth high-pass filters are often used for NTF (z).

• STF (z) contains peaking at high frequencies.

If c1 = 0 and c2 = 0, the poles of L(z) can be moved away from z = 1 along the unitcircle.



z 1z 1

1 z 1z 1

z 1z 1

1z 1z 1

c 1

z 1z 1

1

c 2

1b b 2 b 4 b 5b 3

a 1 a 2 a 3 a 4 a 5

1 1

y(k)

x(k)



If c1 = c2 = 0,

L(z) =a1

(z − 1)n−0+

a2

(z − 1)n−1+

a3

(z − 1)n−2+ · · ·

G(z) =b1

(z − 1)n−0+

b2

(z − 1)n−1+

b3

(z − 1)n−2+ · · ·

NTF (z) =1

1 + L(z)=

(z − 1)n

D(z)STF (z) =

b1 + b2(z − 1) + b3(z − 1)2 + · · ·D(z)

• The numerator of STF (z) is arbitrary, but has an order that is one less than D(z).

• The STF (z) does not contain significant peaking.

• Each integrator output contain significant amounts of the input signal as well asfiltered quantization noise.

If c1 = 0 and c2 = 0, the poles of L(z) can be moved away from z = 1 along the unitcircle.


Stability of Single-Stage High-Order Modulators

αG(z)

F(z)

e(k)

Quantizer

x(k)

Re(z)

Im(z)

y(k)

Y (z) =αG(z)

1 + αG(z)F (z)· X (z) +

11 + αG(z)F (z)

· E (z)

• A modulator is called stable, if the input to the quantizer does not become overloaded,i.e., e(k) ≤ ±∆/2.

• All high-order modulators (N > 2) are conditionally stable.

• Modulators with multi-bit quantizer and DAC exhibit improved stability.


Stability of Single-Stage High-Order Modulators

For single-stage modulators with one-bit quantizer and DAC:

• As a general rule of thumb, stability can be achieved by keeping∣∣∣NTF

(ejω)∣∣∣ ≤ 1.5.

• A modulator can be made more stable by placing the poles closer to the zeros inNTF (z). But, the SNR is also degraded since the out-of-band gain of NTF (z) is alsoreduced.

• Stability is also related to the input signal level. Typically want 50–80% of ∆ for stableinput range.

• “Signal overload” and “power on” may cause a conditionally stable modulator tooscillator. Need additional mechanism to detect instability and force the loopbecoming stable.



D/A

y1 (k)

D/A

y (k)2H (z)2

1 (k)e

H 1 (z)x(k)

ErrorCancel y(k)

Y1(z) = S1(z) · X (z) +N1(z) · E1(z) Y2(z) = S2(z) · E1(z) +N2(z) · E2(z)



The error cancellation logic is

Y (z) = S ′2(z) · Y1(z) − N ′1(z) · Y2(z)

If S2(z) = S′2(z) and N1(z) = N

′1(z), then Y (z) = S1(z)S2(z) · X (z) −N1(z)N2(z) · E2(z).

• Also called multi-stage noise shaping (MASH) architecture.

• Individual loop can be low-order and stable. The resulting noise shaping functionN1(z)N2(z) · · · is high-order.

• Sensitive to mismatches between the analog and digital circuitry.

• For low-order loop, the finite opamp gain can cause noise leak-through.

• y(k) has more than one bit, thus complicates the output DAC design in D/Aapplications or the decimation filter design in A/D applications.



D/A

D/A

1z

D/A

1z

y1 (k)

y (k)2

q 2 (k)

q 1 (k)

z 1

1z

1z

1z

x(k) y(k)

y (k)3

y (k)4z 2

z 2



The outputs of the quantizers are

Y1 = z−1X +(1 − z−1)E1 Q1 = Y1 − E1 = z−1(X − E1)

Y2 = z−1Q1 +(1 − z−1)E2 Q2 = Y2 − E2 = z−1(Q1 − E2)

Y3 = z−1Q2 +(1 − z−1)E3 = z−2Q1 − z−2E2 +

(1 − z−1)E3

We have

Y4 = z−2Y2 +(1 − z−1) Y3 = z−2Q1 +

(1 − z−1)2

E3 = z−3X − z−3E1 +(1 − z−1)2

E3

and

Y = z−3Y1 +(1 − z−1) Y4 = z−3X +

(1 − z−1)3

E3



For a 1st-order 1-bit modulator and ±∆ = ±1,

y(k) = sgn[u(k)] = u(k) + e(k) u(k + 1) = u(k) + x(k) − y(k)

If x(k) = 0 and u(0) = 0, then

y(k) = (+1,−1) · · · e(k) = (+1, 0) · · ·

If x(k) = 1/3 and u(0) = 0, then

y(k) = (+1,−1,+1) · · · e(k) = (+1,−1/3,+1/3) · · ·

If x(k) = 1/2 and u(0) = 0, then

y(k) = (+1,−1,+1,+1) · · · e(k) = (+1,−1/2,0,+1/2) · · ·



• In above examples, e is periodic and nowhere near white. Different initial states justshift the sequence and the values of e.

• For bounded input |u| < 1, x is rational⇔ y is periodic.

• Low-frequency tones cannot be filtered out by the following decimation filter.

• Tones also exists in higher-order modulators. The tones might not lie at a singlefrequency but instead be short-term periodic patterns.

• Nearly all types of modulators can produce very high-powered tones near fs/2. Clocknoise near this frequency can couple and demodulate these tones down into thebaseband.

• For ac input, strong peaks and dips in the output noise power may be seen for certaininput frequencies and amplitudes.


Noise-Shaped Dithering for Single-Stage Modulators

x(k) G(z)

F(z)

y(k)

d(k)

• d (k) is a pseudo-random noise. It is usually generated by a PN sequence generator.

• The power d (k) must be comparable to that of e(k). The pdf of d (k) usually spansmore than ∆/2.

• d (k) may require 3–8 quantization levels for effective dithering.


Noise-Shaped Dithering for Multi-Stage Cascaded Modulators

1z

2 (k)d

D/A

1z 1 1z 1 1z

z 1

y (k)2

1 1z

1z

D/A

y1 (k)

1 (k)e

x(k)

(k)d 1

y(k)

Y1 = z−1X +(1 − z−1)2

E1 +(1 − z−1)3

D1 Y2 = z−1E1 +(1 − z−1)E2 +

(1 − z−1)D2

Y = z−1Y1 −(1 − z−1)2

Y2 = z−2X + z−1 (1 − z−1)3D1 −

(1 − z−1)3

D2


Multi-Bit ∆Σ Modulator

x(k) G(z)

F(z)

A/D Converter

y(k)

D/A

n(k)

e(k)

x(k) G(z)

F(z)

y(k)

D/A Converter

D/A y(t)

n(t)

e(k)


Multi-Bit ∆Σ Modulator

For the A/D converter

Y (z) =G(z)

1 + F (z)G(z)X (z) +

11 + F (z)G(z)

E (z) − F (z)G(z)

1 + F (z)G(z)N(z)

≈ STF (z)X (z) +NTF (z)E (z) − N(z)

• Out-of-band noise is reduced. Requirements for the analog circuitry are less severe.

• Since they have better stability, more aggressive noise transfer functions may beused.

• The DAC linearity errors are not shaped. The DAC must be nearly as linear as thecomplete converter.


Multi-Bit DAC — Dynamic Element Matching

Unit Elements

A o

A oAnalogOutput1

2

M

MRandomizer

v

0 1 2 3 4

v


Multi-Bit DAC — Dynamic Element Matching

freq

Signal Signal

nfreq

n

Random ScramblingNo Scrambling

• For any value of v , the averaged error in Ao is zero.

• Whitens the mismatch noise.

• The randomizer may consists of a thermometer-type encoder, a random-numbergenerator, and a switchbox. Butterfly structure is often used to simplified theswitchbox design.

• Reference: Ian Galton, “A Rigorous Error Analysis of D/A Conversion with DynamicElement Matching,” Tran. on Circuits and Systems–II, pp. 763–772, 12/95.


Multi-Bit DAC — Data-Weighted Averaging

A oAnalogOutput1

2

M

MDWASelector

v(k)

freq

Signaln

DWA Scrambling

v(1)=3 v(2)=4 v(3)=2


Multi-Bit DAC — Data-Weighted Averaging

• Once every element in the array has been used, the cumulative error is zero. Theerrors induced by the use of each element are averaged out as soon as possible.

• Reference: R. Baird and T. Fiez, “Linearity Enhancement of Multibit ∆Σ A/D andD/A Converters Using Data Weighted Averaging,” Tran. on Circuits and Systems–II,pp. 753–762, 12/95.


Multi-Bit DAC — Noise-Shaped Scrambler

A oAnalo gOutpu t

Unit Elements

1

2

3

4

Therm.Code

v(k)

Swapper Cells

• Each swapper tries to equalize the activity of each of its outputs. Each output fromthe scramble is a first-order noise-shaped sequence.

• Reference: R. Adams, et al, “A 113dB SNR Oversampling DAC with SegmentedNoise-Shaped Scrambling,” ISSCC, pp. 62–63, 2/98.



min()

QuantizerVector

M Unit Elements A o

H2 (z) − 1

su

Element Selection Logic

se

sy

sv

v

M

Mde

sx



• The element selection logic (ESL) is a collection of M digital ∆Σ modulators, eachpossessing a NTF (z) equal to H2(z), implemented with the error feedback structureand supplied with a common input.

• The vector quantizer uses information in the sy vector to select which v elements toenable. Want to minimize se = sv − sy .

• The sy = sx −min(sx ) · [11 · · · 1] function is a shifting operation which set the minimumcomponent in sy to zero. The purpose is to reduce the magnitude of sy vector, in amanner that does not disturb the noise-shaping property of the selection logic.



Let de = [e1, e2, · · · , eM] be the DAC error vector.

• By definition, de · [0]T = 0 and de · [1]T = 0, where [0] = [00 · · ·0] and [1] = [11 · · ·1].

• de · (sv1 + sv2)T = de · sv T1 + de · sv T

2

• de · sv T + de · svT= 0

For the error-feedback structure, we have

SV(z) = SU(z) · [1] + H2(z) · SE(z)



The vector quantizer obeysSV(z) · [1]T = V (z)

The analog output is

Ao(z) = SV(z) · ([1] + DE)T

= SV(z) · [1]T + SV(z) · DET

= V (z) + SU(z) · [1] · DET + H2(z) · SE(z) · DET

= V (z) + H2(z)(

SE(z) · DET)


General Mismatch-Shaping DAC — First-Order Example

M = 4 H2(z) = 1 − z−1

sv (k) = VQ[sy (k)] se(k) = sv (k) − sy (k) sx (k) = −se(k − 1)

k v(k) sy (k) sv (k) se(k) sx (k)0 1 1,1,1,1 1,0,0,0 +0,−1,−1,−1 −0,+1,+1,+11 1 0,1,1,1 0,1,0,0 +0,+0,−1,−1 −0,−0,+1,+12 1 0,0,1,1 0,0,1,0 +0,+0,+0,−1 −0,−0,−0,+13 2 0,0,0,1 1,0,0,1 +1,+0,+0,+0 −1,−0,−0,−04 0 0,1,1,1 0,0,0,0 +0,−1,−1,−1 −0,+1,+1,+15 4 0,1,1,1 1,1,1,1 +1,+0,+0,+0 −1,−0,−0,−06 2 0,1,1,1 0,1,1,0 +0,+0,+0,−1 −0,−0,−0,+1

• Since de · sv T = −de · svT, we can add [1] to sy at any time.

• The first-order algorithm is similar to the data-weighted averaging algorithm.


General Mismatch-Shaping DAC — Second-Order Example

M = 4 H2(z) =(1 − z−1)2

sv (k) = VQ[sy (k)] se(k) = sv (k) − sy (k) sx (k) = −2se(k − 1) + se(k − 2)

k v(k) sy (k) sv (k) se(k) sx (k)0 1 1,1,1,1 1,0,0,0 +0,−1,−1,−1 −0,+2,+2,+21 1 0,2,2,2 0,1,0,0 +0,−1,−2,−2 −0,+1,+3,+32 1 0,1,3,3 0,0,1,0 +0,−1,−2,−3 −0,+1,+2,+43 2 0,1,2,4 0,0,1,1 +0,−1,−1,−3 −0,+1,+0,+34 0 0,1,0,3 0,0,0,0 +0,−1,+0,−3 −0,+1,−1,+35 4 1,2,0,4 1,1,1,1 +0,−1,+1,−3 −0,+1,−2,+36 2 2,3,0,5 0,1,0,1 −2,−2,+0,−4 +4,+3,+1,+5


General Mismatch-Shaping DAC — Second-Order Example

• The element selection logic (ESL) is stable, i.e, se is bounded, for H2(z) =(

1 − z−1)2

,

as long as v stays away from the extremes of its range.

• When a binary modulator is unstable with an NTF (z) equal to H2(z), the correspondingESL algorithm must also be unstable.

• Adding dither to sy may be necessary to whiten the noise caused by a deterministicselection algorithm.


Multi-Bit Unit Elements

• If polarity reversal or repeated use of an unit element in one period is allowed, thecomponents of sv need not be restricted to 0,1.

• Multi-bit can enhance the stability of the ESL in the same manner that multi-bitfeedback enhances the stability of a regular ∆Σ modulator.

• The key circuit constraint is the need to ensure that each usage of an element resultsin the same error.



f sf s f s /M

2M π

f s f sL f sL

h(n)

w(n)x(n) y(m)

M

0 2ππ

0 2ππ/M

0 2ππ

Decimationx(n) y(m)w(m)

h(n)L

0 2ππ/L

0 2π 2π/Lπ/L

0 2ππ

Interpolation

ωω

ω ω′

ω′

ω′

X(ejω)

X(ejω)

Y(ejω′)

Y(ejω′)

W(ejω)

W(ejω′)



Decimation Filter = y(m) =∞∑

k=−∞h(k)x(Mm − k)

Interpolation Filter = y(m) =∞∑

k=−∞h(m − kL)x(k)

• The processes of decimation and interpolation are in effect duals.

• A filter defined for one process can often be used for other if the same parametersare used.

• An architecture that is efficiently defined for one process can often be transposed forused as an efficient architecture in the dual process.



LPF

N2

1+ δ1

ωp

δ2

N1

LPF

44.1 kHz

y(m)

kHz44.1

x(n)

2822.4 kHz

LPF

N 44.1 kHz

y(m)

20 22.05

64

δ11−

πωs

ω

0

1411.2kHz

20 22.05

20 66.15 1411.2kHz

x(n)

2822.4 kHz 88.2 kHz32 2



• The order N of an equiripple FIR filter is

N ≈f (δ1, δ2) − g(δ1, δ2)(∆ω)2

∆ω≈−10 log10(δ1δ2) − 13

14.6∆ω

f (δ1, δ2) = (0.005309x21 + 0.07114x1 − 0.4761)x2 − (0.00266x2

1 + 0.5941x1 + 0.4278)

g(δ1, δ2) = 11.012 + 0.51244(x1 − x2)

∆ω =ωs −ωp

2πx1 = log10 δ1 x2 = log10 δ2

• For the single-stage design, δ1 = 0.001, δ2 = 0.00001, then N = 6250. For thetwo-stage design, δ1 = 0.001/2, δ2 = 0.00001, then N1 = 291 and N2 = 205.

• Practical considerations sometimes lead to the conclusion that a two-stage design isbest.

• For most cases, the choice of 2 : 1 for the last stage is both the theoretically bestoption as well as the most practical one.


sinc k Filters

z 1 z 1f s

x(n)z 1

f s

/M2π /M4π /M8π

sinc

1f s

x(n)

f s

f s

x(n)

f s

x(n)

f s

f s /M

y(m)

z 1 z 1

z 1 z 1

z 1 z 1

1 2 M−1

/M

y(m)M

sinc

0 πω

1

/M

y(m)sinc sinc

2 k

z M/M

y(m)

M

z M M

M


sinc k Filters

The sinc filter transfer function is

H1(z) =1M

M−1∑i=0

z−1 =1M

(1 − z

−M

1 − z−1

)

H1

(ejω)=

1M·sin(ωM/2)

sin(ω/2)=

sinc(ωM/2)

sinc(ω/2)sinc(x) =

sin(x)x

The sinck filter transfer function is

H(z) = [H1(z)]k =1

Mk

(1 − z

−M

1 − z−1

)k

=1

Mk·(

1

1 − z−1

)k·(1 − z−M

)k

• The integrator-differentiator architecture is inherently stable, when 2’s-complementarithmetic is used due to its wrap-around characteristic.


Phase-Locked Loops

Jieh-Tsorng Wu

July 16, 2002

A

1896



A Vi c

oAFilter

PhaseDetector

LoopVFO

Ai = g1 (ωit + θi) Ao = g2 (ωot + θo) ωo = ωoo + Kc · Vc

• g1 and g2 are periodic functions with 2π period.

• When the loop is locked, the frequency of the VCO is exactly equal to the averagefrequency of the input.

• The loop filter is a low-pass filter that suppresses high-frequency signal componentsin the phase difference.

PLLs 27-2 Analog ICs; Jieh-Tsorng Wu


Applications:

• Automatic frequency control.

• Frequency and phase demodulation.

• Data and clock recovery.

• Frequency synthesis.

References:

• Roland E. Best, “Phase-Locked Loops,”, 2nd Edition, McGraw-Hill, Inc., 1993.

• Dan H. Wolaver, “Phase-Locked Loop Circuit Design,” Prentice-Hall, Inc., 1991.

• Floyd M. Gardner, “Phaselock Techniques,” 2nd Edition, John Wiley & Sons, 1979.


Basic Model

Vd VcPD

DetectorPhase VFO

F(s)

Filter

θi θo

Vd = Kd (θi − θo) ωo = ωoo + Ko × Vc

Ko/s

When the PLL is locked,

Vd (s) = Kd · [θi(s) − θo(s)] = Kdθe(s) θe = θi − θo

Vc(s) = F (s) · Vd (s)∫ωodt = ωoot +

∫KoVcdt = ωoot + θo ⇒ θo(s) = Vc(s) ·

Ko

s

• θe is the phase error, Kd is the phase-detector gain factor, and Ko is the VCO gainfactor.


Basic Model

System equations are

Vd = Kd · (θi − θo) = Kd · θe Vc = F (s) · Vd θo = Vc ·Ko

s


θo

θi

=KoKdF (s)

s + KoKdF (s)= H(s)

θe

θi

=s

s + KoKdF (s)= 1 − H(s)

Vc

θi

=sKdF (s)

s + KoKdF (s)=

s

Ko

· H(s)

⇒ H(s) =∆ωo

∆ωi

= Ko ·Vc

∆ωi

∆ωi = ωi −ωoo ∆ωo = ωo −ωoo

• H(s) is the closed-loop transfer function.


Second-Order PLL — Active Lag-Lead Filter

Vi Vo

R2

1R

C

F (s) = −sτ2 + 1

sτ1

τ1 = R1C

τ2 = R2C

H(s) =2ζωns +ω

2n

s2 + 2ζωns +ω2n

ωn =

√KoKd

τ1ζ =

ωn

2· τ2

• ωn is the pole frequency of the loop.

• ζ is the damping factor. Qp = 1/(2ζ ) is the pole quality factor.


Second-Order PLL — Passive Lag-Lead Filter

Vi Vo1R

R2

C

F (s) =sτ2 + 1

sτ1 + 1

τ1 = (R1 + R2)C

τ2 = R2C

H(s) =s[2ζωn −ω

2n/(KoKd )

]+ω

2n

s2 + 2ζωns +ω2n

ωn =

√KoKd

τ1ζ =

ωn

2

(τ2 +

1KoKd

)

• If R2 = 0, then

τ1 =1

R1C=

1ωLF

ωn =√KoKdωLF ζ =

ωn

2KoKd

H(s) =ω

2n

s2 + 2ζωns +ω2n


High-Gain Second-Order PLL Frequency Response

If KoKdτ2 1 in the passive filter, then

Hpassive(s) ≈ Hactive(s) =2ζωns +ω

2n

s2 + 2ζωns +ω2n

And the −3 dB bandwidth of H(s) is

ω−3dB = ωn

[2ζ2 + 1 +

√(2ζ2 + 1)2 + 1

]1/2

• Usually choose ωn < ωi/10 to remove the high-frequency components at ωi , 2ωi ,. . . , existing in the phase detector’s output.

• The PD output’s high-frequency components can show up as spurious tones in thefrequency spectrum of the PLL’s output.


High-Gain Second-Order PLL Frequency Response

ω| H

( j

) |

(d

B)

0.1 1 10

10

5

0

-5

-10

-15

-20

Frequency (ω/ωn)

ζ = 5.0

ζ = 2.0

ζ = 0.707

ζ = 0.5

ζ = 0.3



Consider the following two-pole transfer function

H(s) =ω

2n

s2 + 2ζωns +ω2n

Poles = s1,2 =(−ζ ±

√ζ2 − 1

)ωn

• If ζ > 1, the system is overdamped, and both poles are real.

Step Response = 1 − 1

2√ζ2 − 1

(1k1

e−k1ωnt − 1k2

e−k2ωnt

)

k1 = ζ −√ζ2 − 1 k2 = ζ +

√ζ2 − 1

• If ζ = 1, the system is critically damped, and both poles are at −ωn.

Step Response = 1 − (1 +ωnt)e−ωnt ≈ 1 − e−ωnt/(2ζ ) if 4ζ2 1



• If ζ < 1, the system is underdamped.

Step Response = 1 −(ζωn

ωd

· sinωdt + cosωdt

)e−ζωnt ωd =

√1 − ζ2 ·ωn

% Overshoot = 100e−π/√

1/ζ2−1

1

Overshoot

Error Band

t

Ste

p R

esp

on

se

• For PLL, choose ζ > 1/√

2 = 0.707 to avoid excessive ringing.


Phase Jitter

ProbabilityDensity

Vs nc

nt

VN

θn θn

pdf = 1√2πσn

e−θ2

n/(2σ2n)

v(t) = s(t) + n(t) = Vs sin(2πfot) + n(t)

n(t) = nc(t) sin(2πfot) + nt(t) cos(2πfot)

The phase jitter is

θn(t) = tan[

nt(t)

Vs + nc(t)

]≈

nt(t)

Vs


Phase Jitter

Assume that

n2 =12· n2

c +12· n2

tn2c = n2

t

Then, we have

σ2n = θ2

n =n2t

V 2s

=n2

V 2s

=12· 1SNR

• SNR is the signal-to-noise ratio, and can be expressed as

SNR ≡V

2s /2

n2


Phase Noise

PowerSpectralDensity

Freq

Ps

Pssb

L(fm)

fo

fm

v(t) = Vs sin [2πfot + θn(t)]


Phase Noise

• The phase noise L(fm), usually in dBc, is the ratio of the single-sideband (SSB) powerin a 1-Hz bandwidth fm Hz away from the carrier to the total signal power, i.e.,

L(fm) ≡Ps

Pssb

• Let Sθn(f ) be the power spectral density of θn(t) in frequency domain, it can be shown

that

Sθn(fm) ≈ 2L(fm) and θ2

n =∫ ∞0

Sθn(f )df


PLL Noise Response

F(s)θi θo

θn,i θn,vf onvc

Kd Ko/s

Let θn,o be the phase noise in θo, we have

Sθn,o

Sθn,i

=

∣∣∣∣ KoKdF (s)

s + KoKdF (s)

∣∣∣∣2

s=jω

= |H(jω)|2

Sθn,o

Sθn,vf o

=

∣∣∣∣ s

s + KoKdF (s)

∣∣∣∣2

s=jω

= |1 − H(jω)|2

Sθn,o

Snvc

=

∣∣∣∣ Ko

s + KoKdF (s)

∣∣∣∣2

s=jω

=

∣∣∣∣[1 − H(jω)] ·Ko

jω

∣∣∣∣2


PLL Noise Response

Consider only a white noise Sθn,i(f ) in θi ,

θ2n,o =

∫ ∞0

Sθn,i(f )|H(j2πf )|2df = Sθn,i

(f ) × BL

BL is the noise bandwidth of H(j2πf ), i.e.,

BL ≡∫ ∞0|H(j2πf )|2df

For the 2nd-order PLL with active lag-lead filter

BL =12ωn

(ζ +

14ζ

)

• BL,min occurs at ζ = 0.5.

• BL < 1.25BL,min for 0.25 < ζ < 1.0.



V1

V2

Vd

Vd

θe

12π

π

32π 2π

−12π

-π

−32π

−2π

V1(t) = V1 sin(ωt + θ1) V2(t) = V2 cos(ωt + θ2)

Vd (t) = kV1(t)V2(t) =12kV1V2 [sin(θ1 − θ2) + sin(2ω + θ1 + θ2)]



The 2ω component will be filtered out by the loop filter, hence consider the dc componentonly

Vd =12kV1V2 sin(θ1 − θ2) = Kd · sin(θe) θe = θ1 − θ2

• Kd is the phase-detector gain factor, and θe is the phase error.

• If θe 1, vd ≈ Kdθe.

• V1(t) and V2(t) are 90 out of phase when θe = 0.


PLL Tracking Performance — Hold-In Range

From the final value theorem

limt→∞

θe(t) = lims→0

sθe(s) = lims→0

s2θi(s)

s + KoKdF (s)

The hold-in range, ∆ωH , is the frequency range in which a PLL can maintain lockstatically.

ωi = ωo + ∆ωH θi(t) = ∆ωH · t θi(s) = ∆ωH/s2 ⇒ lim

t→∞θe(t) =

∆ωH

KoKdF (0)

• For a sinusoidal PD, the criterion becomes

limt→∞

sinθe(t) =∆ωH

KoKdF (0)< 1 ⇒ ∆ωH = KoKdF (0)

For a 2nd-order PLL with active filter, F (0)→∞, thus ∆ωH →∞.


PLL Tracking Performance — Pull-Out Range

The pull-out range ∆ωPO is the frequency-step limit below which the PLL does not skipcycles but remains in lock.

• For a sinusoidal PD

∆ωPO = 1.8ωn(ζ + 1) for 0.5 < ζ < 1.4


Noisy PLL Tracking Performance

Define the SNR of a PLL as

SNRL ≡1

2θ2n,o

• As a rule of thumb, SNRL > 6 dB is required for stable operation.

For low SNRL, the VFO phase occasionally slips one or more cycles as compared to theinput. Define TAV as the average time between cycle slips.

• For a 1st-order loop TAV ≈ π4BL

e4SNRL, where BL is the PLL noise bandwidth.

• For a 2nd-order loop with ζ = 0.707 TAV ≈ 1BLeπSNRL.

• The slips of a 1st-order loop are almost always single, isolated events.

• The slips in a 2nd-order loop tend to bunch in bursts.


PLL Acquisition Behavior

i VoV F(s)Phase

Detector

VFOLoop Filter

• The process of bringing a PLL into lock is called acquisition.

• Acquisition is inherently a nonlinear phenomenon.

• An nth-order PLL contains n integrators (VFO, capacitors, . . . ). With each integratorthere is associated a state variable of the loop: phase, frequency, frequency rate,and so on. To force the loop into lock, it is necessary to bring each of the statevariables close to the corresponding parameters of the input signal. Therefore, weshould speak of phase acquisition, frequency acquisition, and so forth.


Phase Acquisition of a First-Order Loop

ViVd

VoPhase

Detector

VCO

θe

θeKoKd

∆ωKoKd− sinθe

Vd = Kd · sinθe ωo = ωoo + Ko · Vd θe = θi − θo

θe = θi − θo = ωit −ωoot −∫ t

0KoKd sinθedt − θo(0)

⇒dθe

dt= θe = ∆ω − KoKd sinθe ∆ω = ωi −ωoo

• The loop is locked when θe = 0.

• There is no cycle skipping in the acquisition process.


Phase Acquisition of a Second-Order Loop

The lock-in range, ∆ωL, is the frequency range over which the PLL can acquire lockwithout cycle slipping.

By practical considerations, the lock-in process of a higher-order loop isso fast that it can be approximated bythe phase acquisition process of a 1st-order loop with gain K = KoKdF (∞).

log f

log |F (j f )|

F (∞) = τ2τ1

• For a PLL with with sinusoidal PD,

Lock-In Range = ∆ωL ≈ KoKdF (∞) = 2ζωn Lock-In Time = TL ≈1ωn


Frequency Acquisition — The Pull-In Process

The pull-in range, ∆ωP , is themaximum initial frequencyoffset for the pull-in processto occur.

t

∆ω

ωi

ωo

Tp

• For a 2nd-order PLL,

Pull-In Range = ∆ωP ≈8π

√ζωnKoKd −ω2

n ≈8π

√ζωnKoKd if KoKd ωn

Pull-In Time = Tp ≈∆ω

2

2ζω3n


Aided Frequency Acquisition — Frequency Sweeping

Vi LoopFilter

PhaseDetector

DetectorLock Sweep

Generator

VFO

• Use sweep to bring the VFO close to the frequency of locking.


Aided Frequency Acquisition — Loop Filter Switching

Vi PhaseDetector

DetectorLock

VFO

Low R if unlocked; High R if locked

Loop Filter

Low R

High R

• The frequency pull-in can be painfully slow in a narrowband loop. Sometimes, a widerloop bandwidth is preferred.


Aided Frequency Acquisition — Dual Loops

iV LP

LP

Detector Filter 1

Filter 2

Phase

VFO

DetectorFrequency

• Contains a phase-locked loop (PLL) and a frequency-locked loop (FLL).

• The FLL should dominate during frequency acquisition.

• The PLL should dominant when the phase is locked.


Digital Phase-Locked Loops (DPLLs)

oVViVd VcF(s)

1/N

PD

Loop Filter

VFO

Frequency Divider

To calculate loop dynamics, combine the VFO and the frequency divider as a new VFO.

ωo = ωoo + Ko · Vd ⇒ ω′o =ω

N=

ωoo

N+Ko

N· Vd = ω′oo + K ′o · Vd

ω′oo =ωoo

NK ′o =

Ko

Nθ′o =

θo

N

• θi and θo are not available except during the rising and falling transitions.


XOR Phase Detector

u1

u2

Q

u1

u2Q

0

u1

u2

Q

u1

u2

Q

Averaged Q

θeπ2

π−π2

−π

• The PD characteristic is strongly dependent on the duty-cycle of u1 and u2.



S

RQ

u1

u2

Q

u1

u2

Q

u2

u1u1

u2

Q

Frequency Discrimination Capability

0

Averaged Q

u1

u2

Q

u1

u2

Q

θeπ 2π−π−2π



• The PD is edge-sensitive, the duty-cycle of u1 and u2 is irrelevant.

• If f1 f2 or f1 f2, the PD has frequency discrimination capability, which canimprove frequency acquisition speed of the PLL.

• However, when f1 ≈ f2, the frequency-sensitive behavior is lost, and the PLL relys onthe pull-in process for frequency acquisition.



RQD

u1

u2

UP

0

u1

u2

UP

Averaged (UP-DW)

RD Q

1

1

u1

u2

UP

DNDN

DN

θe

π 2π−π−2π



• The PFD is edge-sensitive, the duty-cycle of u1 and u2 is irrelevant.

• The PFD can discriminate the frequency difference for even the smallest f1 − f2.

• A PLL with the PFD can have infinite pull-in range. The frequency acquisition aidprovided by the PFD is akin to frequency sweeping.

• When using the PFD, a missing transition or an extra one in either u1 or u2 can causea large error signal to appear. The effects will propagate for more than one cycle.Great caution is required to use the PFD in a noisy environment.



ViVo

Vc

IP

IP

IeUP

PFD

R

C

VFO

DN

u1

u2

The “on” time of either UP or DN is tp = |θe|/ωi for each period 1/fi of the input signal.The average error current Ie over a cycle is

Ie = IP ×tp

Ti= IP ×

θe

2πωi = 2πfi =

2πTi



The voltage Vc can be expressed as

Vc(s) = Ie(s)(R +

1sC

)= θe(s) ×

IP

2π

(R +

1sC

)Vc(s)

θe(s)= KdF (s) =

IP

2π

(R +

1sC

)

The VFO has the following characteristic:

ωo = ωoo + Ko · Vc ⇔ fo = foo + K ′o · Vc K ′o =Ko

2π

Using the continuous-time approximation, we have

θe(s)

θi(s)= He(s) =

s2

s2 + 2ζωns +ω2n

θo(s)

θi(s)= H(s) = 1 − He(s)

ωn =(K ′o ×

IP

C

)1/2

ζ =12

[K ′o × (IP R) × (RC)

]1/2



• The PLL behaves as a 2nd-order loop with active lag-lead filter.

• Discrete-time model can be used for more accurate analysis. Reference: Hein, z-Domain Model for Discrete-Time PLLs, Trans. CAS, 11/88, pp. 1393–1400.

• During the pump interval tp, a voltage step of IP R occurs at the VFO input. Thisgranularity effect may be intolerable in some systems.

• The voltage step IP R may overload the VFO, making the previous linear analysisinvalid.

• The granularity effect can be mitigated with an additional capacitor Cp in parallel withthe earlier RC network, thus forming a 3rd-order PLL.

• Reference: Floyd Gardner, “Charge-Pump Phase-Lock Loops,” IEEE Trans. Commun.,Nov. 1980, pp. 1849–1858.



IP2

IP1

Dead ZoneDN

UPS1

S2 C

RQD

RD Q

1

1

u2

u1

Vc

∆Vc

θe

• The dead zone is caused by the slowness of the S1 and S2 switches.



• When θe falls in the dead zone, the PFD’s conversion gain is decreased, causing areduction in ωn and ζ , and the degradation of θo phase noise.

• The dead zone can be eliminated by allowing UP and DN to be activatedsimultaneously for a short time even if the phase difference is zero. Then, anymismatch between IP 1 and IP 2 can cause a phase offset and consequently spursin the output spectrum.

• The finite output impedance of the IP 1 and IP 2 current sources can also cause phaseoffset.

• Charge sharing in the S1 and S2 switches can also cause glitches at Vc.


PFD with Delayed Reset

DN

UP

u2

u1

Delay



IP

IP

Ie VcUP

DN 0R1

C1C2

ωωz

ωtωp

|L(jω)| (dB)

The loop filter transfer function is

Vc(s)

θe(s)= KdF (s) =

IP

2π

[(R1 +

1sC1

)‖ 1sC2

]=

IP

2πs(C1 + C2)×

sR1C1 + 1

sR1(C1‖C2) + 1

ωz =1

R1C1ωp =

1

R1(C1‖C2)



The loop gain of the 3-order PLL is

L(s) =Ko

s× KdF (s) =

K′oIP

s2(C1 + C2)×

s/ωz + 1

s/ωp + 1

Let ωt/ωz = α > 1 and ωp/ωt = β > 1, then

ωt ≈K′oIP

(C1 + C2)ωz

= K ′o · IP R1 ·C1

C1 + C2

R1 =1

K ′oIP·ωt C1 = K ′oIP ·

α

ω2t

C2 = K ′oIP ·1

β ·ω2t

• α = 4 and β = 4 gives a phase margin ≈ 60.



V aV b

V c

Ca

Rb Cb

V c

V a

V b

Ie1

Ie2

ωωz ωt ωp

Ie1 = IP 1 ×θe

2πIe1 = IP 2 ×

θe

2π



The loop filter transfer function is

Vc(s)

θe(s)= KdF (s) =

IP 1

2π· 1Ca

+IP 2

2π

(Rb‖

1sCb

)=

IP 1

2πsCa

×sRb

(Cb + Ca ·

IP 2IP 1

)+ 1

sRbCb + 1

1ωz

= Rb

(Cb + Ca ·

IP 2

IP 1

)≈ RbCa ·

IP 2

IP 1

1ωp

= RbCb

The loop’s unity-gain frequency is

ωt ≈K′oIP 1

Caωz

= K ′o · IP 2Rb

• ωz, ωp, and ωt, can be set using smaller capacitors and resistors.

• Reference: J. Craninckx and M. Steyaert, A Fully Integrated CMOS DCS-1800Frequency Synthesizer, JSSC, 12/98, pp. 2054–2065.


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