AN113 - Power Conversion, Measurement and Pulse...

Application Note 113

AN113-1

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Power Conversion, Measurement and Pulse CircuitsTales From the Laboratory Notebook, 2005-2007

Jim Williams

August 2007

all with outputs below 600mV, are typical power sources for such a converter.

Figure 1, an N-channel JFET I-V plot, shows drain-source conduction under zero bias (gate and source tied together) conditions. This property can be exploited to produce a self-starting DC/DC converter that runs from 0.3V to 1.6V inputs.

Figure 2 shows the circuit. Q1 and T1 form an oscillator with T1’s secondary providing regenerative feedback to Q1’s gate. When power is applied, Q1’s gate is at zero volts and its drain conducts current via T1’s primary. T1’s phase inverting secondary responds by going negative at Q1’s gate, turning it off. T1’s primary current ceases, its secondary collapses and oscillation commences. T1’s primary action causes positive going “fl yback” events at Q1’s drain, which are rectifi ed and fi ltered. Q2’s ≈ 2V

Figure 1. Zero Volt. Biased JFET I-V Curve Shows 10mA Conduction at 100mV, Rising Above 40mA at 500mV. Characteristic Permits DC/DC Converter Powered From 300mV Supply.

INTRODUCTION

This ink marks LTC’s eighth circuit collection publication.1 We are continually surprised, to the point of near mys-tifi cation, by these circuit amalgams seemingly limitless appeal. Reader requests ascend rapidly upon publication, remaining high for years, even decades. All LTC circuit collections, despite diverse content, share this popular-ity, although just why remains an open question. Why is it? Perhaps the form; compact, complete, succinct and insular. Perhaps the freedom of selection without com-mitment, akin to window shopping. Or, perhaps, simply the pleasure of new recruits for the circuit afi cionados intellectual palate. Locally based electrosociolgists, spin-ning elegantly contrived theories, offer explanation, but no convincing evidence is at hand. What is certain is that readers are attracted to these compendiums and that calls us to attention. As such, in accordance with our mission to serve customer preferences, this latest collection is presented. Enjoy.

JFET-Based DC/DC Converter Powered From 300mV Supply

A JFET’s self-biasing characteristic can be utilized to construct a DC/DC converter powered from as little as 300mV. Solar cells, thermopiles and single-stage fuel cells,

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

Note 1. Previous efforts include References 4, 6, 7 and 23-26.

Figure 2. JFET-Based DC/DC Converter Runs From 300 Millivolt Input. Q1-T1 Oscillator Output Is Rectifi ed and Filtered. Load Is Isolated Until Q2 Source Reaches ≈2V, Aiding Start-Up. Comparator and Q3 Close Loop Around Oscillator, Controlling Q1’s On-Time to Stabilize 5V Output.

0.3VIN-1.6VIN

5VOUT,2mA MAX

1.21M*

3.83M*T1

7

5

6

3

6.8µF 100µF

100Ω

–

+

++

* = 1% METAL FILM RESISTOR T1 = COILTRONICS VP1-1400

TIE WINDINGS (1, 12) (2, 4) (8, 10) (9, 11) Q1 = PHILIPS BF-862, 2 DEVICES IN PARALLEL

BAT-85

Q3VN2222L

Q2TP0610L

C1LTC1440

1.18VREF. OUT

1N5817

AN113 F02

0.01µF

0.001µF

Q1


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turn-on potential isolates the load, aiding start-up. When Q2 turns on, circuit output heads towards 5V. C1, powered from Q2’s source, enforces output regulation by comparing a portion of the output with its internal voltage reference. C1’s switched output controls Q1’s on-time via Q3, form-ing a control loop.

Waveforms for the circuit include the AC coupled output (Figure 3, trace A), C1’s output (trace B) and Q1’s drain fl yback events (trace C). When the output drops below 5V, C1 goes low, turning on Q1. Q1’s resultant fl yback events continue until the 5V output is restored. This pat-tern repeats, maintaining the output.

The 5V output can supply up to 2mA, suffi cient to power circuitry or furnish bias to a higher power switching regulator when larger current is required. The circuit will start into loads of 300µA at 300mV input; 2mA loading requires a 475mV supply. Figure 4 plots minimum input voltage versus output current over a range of loads.

Q3’s shunt control of Q1 is simple and effective, but results in 25mA quiescent current drain. Figure 5’s modifi ca-tions reduce this fi gure to 1mA by series switching T1’s secondary. Here, Q3 switches series connected Q4, more effi ciently controlling Q1’s gate drive. Negative turn-off

Figure 3. JFET-based Converter Waveforms. When Supply Output (Trace A) Decays, C1 (Trace B) Switches, Allowing Q1 to Oscillate. Resultant Flyback Events at Q1 Drain (Trace C) Restore Supply Output.

Figure 4. JFET-Based DC/DC Converter Starts and Runs into 100µA Load at VIN = 275mV. Regulation to 2mA Is Possible, Although Required VIN Rises to 500mV.

Figure 5. Adding Q3, Q4 and Bootstrapped Negative Bias Generator Reduces Quiescent Current. Comparator Directed Q3 Switches Q4, More Effi ciently Controlling Q1’s Gate Drive. Q2 and Zener Diode Isolate All Loading During Q1 Start-Up.

0.3VIN-1.6VIN

5VOUTT1

7

5

6

3

6.8µF

470k

100µF

1µF

10M

1M

3.83M*

1.21M*

–

+ 0.01µF

+

+

+

= 1N4148 * = 1% METAL FILM RESISTOR Q1, Q4 = PHILIPS BF-862 Q1 = 2 DEVICES IN PARALLEL T1 = COILTRONICS VP1-1400

TIE WINDINGS (1, 12) (2, 4) (8, 10) (9, 11)

≈ –12V

Q4

Q1

51Ω

Q2TPO610L

6.8V1N4692

Q3TP0610L

C2LTC1440

1.18VREF. OUT

1N5817

AN113 F08

OUTPUT CURRENT (µA)0

MIN

IMUM

INPU

T VO

LTAG

E TO

MAI

NTAI

NV O

UT =

5V 0.3

0.4

0.5

0.2

0.1

0.0250 500 750 1000 1250 1500 1750 2000

AN113 F04

START AND RUN

C = 5V/DIV

A = 0.1V/DIVAC COUPLED

B = 5V/DIV

HORIZ. = 5ms/DIV AN113 F03


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bias for Q4 and Q1 is bootstrapped from T1’s secondary; the 6.8V zener holds off bias supply loading during initial power application, aiding start-up. Figure 6’s plot of mini-mum input voltage versus output current shows minimal penalty (versus Figure 4’s data) imposed by the added quiescent current control circuitry.

Bipolar Transistor-Based 550mV Input DC/DC Converter

Bipolar transistors may be used to obtain higher output currents, although their VBE drop raises input supply re-

quirements to 550mV. Figure 7’s curve tracer plot shows base-emitter conduction just beginning at 450mV (25°C) with substantial current fl ow beyond 500mV. Figure 8’s circuit operates similarly to FET-based Figure 2, although the bipolar transistor’s normally off characteristic allows more effi cient operation. Figure 9’s operating waveforms are similar to Figure 3, except the comparator’s output state is reversed to accommodate the bipolar transistor. Figure 10’s start-run curves show 6mA output current at 550mV input—3 times the FET circuit’s capacity. The “run” curve

Figure 6. Start/Run Curve for Low Quiescent Current JFET-Based DC/DC Converter. Quiescent Current Control Circuitry Slightly Increases Input Voltage Required to Support Load.

Figure 7. Bipolar Transistor Base Emitter Junction I-V Curve Shows Conduction Beginning at 450 Millivolts (25°C). Characteristic Forms Basis of DC/DC Converter Powered From 550 Millivolts.

Figure 9. Converter Waveforms. When Output (Trace A) Decays, C1 (Trace B) Switches, Allowing Q1 to Oscillate.Resultant Flyback Events at Q1 Collector (Trace C) Restore Output.Figure 8. Bipolar Transistor-Based DC/DC Converter Runs From

500 Millivolt (25°C) Input. Q1-T1 Oscillator Output is Rectifi ed and Filtered. Load is Isolated Until Q2’s Source Reaches ≈2V, Aiding Start-Up. Comparator Closes Loop Around Oscillator, Controlling Q1’s On-Time to Stabilize 5V Output.

0.5VIN-1.6VIN

5VOUT

1.21M*

3.83M*

T1

7

5

6

3

6.8µF 100µF

1k

–

+

++

* = 1% METAL FILM RESISTOR T1 = COILTRONICS VP1-1400

TIE WINDINGS (1, 12) (2, 4) (8, 10) (9, 11)

Q1ZTX-849

BAT-85

5.1V1N751

Q2TP0610L

C1LTC1440

1.18VREF. OUT

BAT-85

1N5817

AN113 F08

0.01µF

OUTPUT CURRENT (µA)0

MIN

IMUM

INPU

T VO

LTAG

E TO

MAI

NTAI

NV O

UT =

5V 0.3

0.4

0.5

0.2

0.1

0.0250 500 750 1000 1250 1500 1750 2000

AN113 F06

START AND RUN

C = 5V/DIV

A = 0.1V/DIVAC COUPLED

B = 5V/DIV



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indicates that, once started, the circuit will run at input voltages as low as 300mV depending on loading.

When considering these circuits’ extremely low input volt-ages and output power limits it is worth noting that the transformer specifi ed is a standard product. A transformer specifi cally optimized for these applications would likely enhance performance.

5V to 200V Converter for APD Bias

BEFORE PROCEEDING ANY FURTHER, THE READER IS WARNED THAT CAUTION MUST BE USED IN THE CONSTRUCTION, TESTING AND USE OF THIS CIRCUIT. HIGH VOLTAGE, LETHAL POTENTIALS ARE PRESENT IN THIS CIRCUIT. EXTREME CAUTION MUST BE USED IN WORKING WITH, AND MAKING CONNECTIONS TO, THIS CIRCUIT. REPEAT: THIS CIRCUIT CONTAINS DANGEROUS, HIGH VOLTAGE POTENTIALS. USE CAUTION.

Avalanche photodiodes (APD) require high voltage bias. Figure 11’s design provides 200V from a 5V input. The circuit is a basic inductor fl yback boost regulator with a major important deviation. Q1, a high voltage device, has been interposed between the LT1172 switching regulator and the inductor. This permits the regulator to control Q1’s high voltage switching without undergoing high voltage stress. Q1, operating as a “cascode” with the LT1172’s in-ternal switch, withstands L1’s high voltage fl yback events.2 Diodes associated with Q1’s source terminal clamp L1 originated spikes arriving via Q1’s junction capacitance. The

Figure 10. Bipolar Transistor-Based DC/DC Converter Requires ≈550mV (25°C) Input to Start into 0mA to 6mA Loading. Once Running, Converter Maintains Regulation Down to 300mV Inputs for 100µA Load.

Figure 11. 5V to 200V Output Converter for APD Bias. Cascoded Q1 Switches High Voltage, Allowing Low Voltage Regulator to Control Output. Diode Clamps Protect Regulator from Transient Events; 100k Path Bootstraps Q1’s Gate Drive from L1’s Flyback Events. Output Connected 300Ω-Diode Combination Provides Short-Circuit Protection.

Note 2. See References 1 (page 8), 2 (Appendix D), and 3.

+

+

SW

GND

LT1172

1N58191N5256B30V 5%

15V1N4702

5V

E1E2

1k

1M* BAS521

OUTPUT200V

6.19k*

AN113 F11

1µF

1µF

33µF

0.1µF

1µF = 2 –0.47µF250V

5V

BAS521 300Ω

L1

Q1IRF840

VC

VIN FB

1N5712100k

DANGER! Lethal Potentials Present — See Text

+

* = 1% METAL FILM RESISTOR L1 = 33µH, COILTRONICS UP2B

0.47µF = PANASONIC ECW-U2474KCV

OUTPUT CURRENT (mA)0

MIN

IMUM

INPU

T VO

LTAG

E TO

MAI

NTAI

NV O

UT =

5V

0.3

0.4

0.6

0.5

0.2

0.1

0.01 2 3 4 5 6 7

AN113 F10

START AND RUN

RUN


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Note 3. This circuit is not a fresh contribution but, rather, a belated mea culpa. The original version suffered temperature dependent output error due to its gate bias bootstrap scheme. See Reference 4.

high voltage is rectifi ed and fi ltered, forming the circuit’s output. Feedback to the regulator stabilizes the loop and the RC at the VC pin provides frequency compensation. The 100k path from L1 bootstraps Q1’s gate drive to about 10V, ensuring saturation.3 The output connected 300Ω-diode combination provides short-circuit protection by shutting down the LT1172 if the output is accidentally grounded.

Figure 12 shows operating waveforms. Traces A and C are LT1172 switch current and voltage, respectively. Q1’s drain is trace B. Current ramp termination results in a high voltage fl yback event at Q1’s drain. A safely attenuated version of the fl yback appears at the LT1172 switch. The sinosoidal signature, due to inductor ring-off between conduction cycles, is harmless.

Battery Internal Resistance Meter

It is often desirable to determine a battery’s internal resistance to evaluate its condition or suitability for an application. Accurate battery resistance determination is complicated by inherent capacitive terms which corrupt results taken with AC-based milliohmmeters operating in the kHz range. Figure 13, a very simplistic battery model, shows a resistive divider with a partial shunt capacitive term. This capacitive term introduces error in AC-based measurement. Additionally, the battery’s unloaded internal resistance may signifi cantly differ from its loaded value. As such, a realistic determination of internal resistance must be made under loaded conditions at or near DC.

Figure 12. Waveforms for 5V to 200V Converter Include LT1172 Switch Current and Voltage (Traces A and C, Respectively) and Q1’s Drain Voltage (Trace B). Current Ramp Termination Results in High Voltage Flyback Event at Q1 Drain. Safely Attenuated Version Appears at LT1172 Switch. Sinosoidal Signature, Due to Inductor Ring-Off Between Current Conduction Cycles, is Harmless. All Traces Intensifi ed Near Center Screen for Photographic Clarity.

Figure 13. Simplistic Model Shows Battery Impedance Terms Including Resistive and Capacitive Elements. Capacitive Component Corrupts AC-Based Measurement Attempts to Determine Internal DC Resistance. More Realistic Results Occur if Battery Voltage Drop Is Measured Under Known Load.

AN113 F13

INTERNALIMPEDENCETERMS

USERTERMINALS

C = 20V/DIV

A = 0.5A/DIV

B = 100V/DIV

2µs/DIV AN113 F12


AN113-6

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Figure 14’s circuit meets these requirements, permitting accurate internal resistance determination of batteries up to 13V over a range of 0.001Ω to 1.000Ω. A1, Q1 and associated components form a closed loop current sink which loads the battery via Q1’s drain. The 1N5821 provides reverse battery protection. The voltage across the 0.1Ω resistor, and hence the battery load, is determined by A1’s “+” input voltage. This potential is alternately switched, via S1, between 0.110V and 0.010V derived from the 2.5V reference driven resistor string. S1’s 0.5Hz square wave switching drive comes from the CD4040 frequency

divider. The result of this action is a 100mA biased 1A 0.5Hz square wave load applied to the battery. The battery’s internal resistance causes a 0.5Hz amplitude modulated square wave to appear at the Kelvin-sensed S2-S3-A2 synchronous demodulator. The demodulator DC output is buffered by chopper stabilized A2 which provides the circuit output. A2’s internal 1kHz clock, level shifted by Q2, drives the CD4040 frequency divider. One divider output supplies the 0.5Hz square wave; a second 500Hz output activates a charge pump, providing a –7V potential to A2. This arrangement allows A2 output swing to zero volts.

Figure 14. Battery Internal Resistance Is Determined by Repetitively Stepping Calibrated Discharge Current and Reading Resultant Voltage Drop. S1-Based Modulator, Clocked From Frequency Divider, Combines with A1-Q1 Switched Current Sink to Generate Stepped, 1 Ampere Battery Discharge Cycles. S2-S3-A2 Synchronous Demodulator Extracts Modulated Voltage Drop Information, Provides DC Output Calibrated in Ohms.

237k1%

0.110V

0.010V

MODULATOR

9VS1

S3

10k1%

1k1%

REFERENCE

–

+

–

A1LT1077

Q1IRLR-024

AN113 F14

IN2.5VOUT

LTC6943

SWITCHEDCURRENT SINK

1N5821SYNCHRONOUSDEMODULATOR

2.7k

10k

0.001µF

BATTERYUNDER TEST

FORCE

SENSE

1µF = MYLAR SINGLE POINT GROUND AT 0.1Ω RESISTOR = LTC6943 PIN #

Q1 = HEAT SINK

+

10k1µF

10µF

FORCE

SENSE

10k1µF

1µF

S2

9V

–

+A2

LT1150

Q22N3904

100k

CLK

CLK

÷ 2÷ 2048

R

+V

NC9V

9V

9V

9V

1V –

CD4040

+

BAT-85

BAT-85

FREQUENCY DIVIDERAND CHARGE PUMP

≈–7V≈0.5Hz SQUARE WAVE

200pF

200k

≈1kHzSquare Wave

OUTPUT0V-1.000V =0Ω-1.000Ω

51

4

16

13

3

6

7 9

15

#

14 2

LTC17982.5V

0.1Ω1%

+10µF


AN113-7

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The circuit pulls 230µA from its 9V battery power supply, permitting about 3000 hours battery life. Other specifi ca-tions include operation down to 4V with less than 1mV (0.001Ω) output variation, 3% accuracy and battery-under-test range of 0.9V to 13V. Finally, note that battery discharge current and repetition rate are easily varied from the values given, permitting observation of battery resistance under a variety of conditions.

Floating Output, Variable Potential Battery Simulator

Battery stack voltage monitor development (Reference 5) is aided by a fl oating, variable potential battery simulator. This capability permits monitor accuracy verifi cation over a

wide range of battery voltage. The fl oating battery simulator is substituted for a cell in the stack and any desired voltage directly dialed out. Figure 15’s circuit is simply a battery powered follower (A1) with current boosted (A2) output. The LT1021 reference and high resolution potentiometric divider specifi ed permits accurate output setting within 1mV. The composite amplifi er unloads the divider and drives a 680µF capacitor to approximate a battery. Diodes preclude reverse biasing the output capacitor during supply sequencing and the 1µF -150k combination provides stable loop compensation. Figure 16 depicts loop response to an input step; no overshoot or untoward dynamics oc-cur despite A2’s huge capacitive load. The battery monitor

Figure 15. Battery Simulator Has Floating Output Settable within 1mV. A1 Unloads Kelvin-Varley Divider; A2 Buffers Capacitive Load.

Figure 16. 150k-1µF Compensation Network Provides Clean Response Despite 680µF Output Capacitor.

Figure 17. Battery Simulator Output (Trace B) Responds to Trace A’s Monitor Current Pulse. Closed Loop Control and 680µF Capacitor Maintain Simulator Output within 30µV. Noise Averaged, 50µV/Division Sensitivity Is Required to Resolve Response.

18V

18V

18V

–9V

–9V

+

–

680µF

1k

OUTPUTA2

LT1010

A1LT1012

50k

AN113 F15

= 1% METAL FILM RESISTOR= ESI DP-1311 KELVIN-VARLEY DIVIDER

***

IN LT1021TRIM TRIM THIS VALUE

OUT

150k

10.000V

FOR THIS VOLTAGE

2X9V

1X9V

BAT-85

IN4001

75k*

100k**

+

1µF

6

VERT. = 0.5V/DIV


A = 200µA/DIV

B = 50µV/DIVNOISE

AVERAGEDAC COUPLED

HORIZ. = 2µs/DIV AN113 F17


AN113-8

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determines battery voltage by injecting current into the battery and measuring resultant clamp voltage (again, see Reference 5). Figure 17 shows battery simulator response (trace B) to trace A’s monitor current pulse into the output. Closed loop control and the 680µF capacitor limit simulator output excursion within 30µV. This error is so small that noise averaging techniques and a high gain oscilloscope preamplifi er are required to resolve it.4

40nVP-P Noise, 0.05µV/°C Drift, Chopped FET Amplifi er

Figure 18’s circuit combines the LTC6241’s rail-to-rail performance with a pair of extremely low noise JFETs confi gured in a chopper-based carrier modulation scheme to achieve extraordinarily low noise and DC drift. This circuit’s performance suits demanding transducer signal conditioning situations such as high resolution scales and magnetic search coils.

The LTC1799’s output is divided down to form a 2-phase 925Hz square wave clock. This frequency, harmonically unrelated to 60Hz, provides excellent immunity to harmonic beating or mixing effects which could cause instabilities. S1 and S2 receive complementary drive, causing the FET-A1 based stage to see a chopped version of the input voltage. A1’s square wave output is synchronously demodulated by S3 and S4. Because these switches are synchronously driven with the input chopper, proper amplitude and po-larity information is presented to DC output amplifi er A2. This stage integrates the square wave into a DC voltage, providing the output. The output is divided down (R2 and R1) and fed back to the input chopper where it serves as a zero signal reference. Gain, in this case 1000, is set by the R1-R2 ratio. The AC coupled input stage’s DC errors do not affect overall circuit characteristics, resulting in the extremely low offset and drift noted.

Note 4. This may be viewed as a historic event in some thinly populated circles. Figure 17 marks the author’s fi rst published use of a digital oscilloscope (Tektronix 7603/7D20), updating him to the 1980s.

Figure 18. Chopped FET Amplifi er Has 40nVP-P Noise and 0.05µV/°C Drift. DC Input Is Carrier Modulated, Amplifi ed by A1, Demodulated to DC and Fed Back From A2. 925Hz Carrier Clock Prevents Interaction with 60Hz Line Originated Components.

+

–

+

–

BIAS

10M

1µF

141516

32

1

S4S3 240k

1µF

OUTPUT

A11/2 LTC6241HV

A11/2 LTC6241HV

1µF

0.001µF

1µFINPUT

10k

8

7

11

S1S2

9

6

10

R210k

R110Ω

NOISEOFFSET

DRIFT

OPEN-LOOP GAINI

= 40nVP-P 0.1Hz TO 10Hz= 1µV= 0.05µV/°C R2 R1= 10= 150pA

+ 1GAIN =9

0.47µF

100k

Ø1

Ø1

Ø2

Ø2

AN113 F18

= 0.1% METAL FILM RESISTOR= 1% METAL FILM RESISTOR

***

= LTC201 QUAD

= LSK389= LINEAR INTEGRATED SYSTEMS FREMONT, CA

1µF

DIVRSET

LTC1799

V+

74C90 ÷ 10

18.5kHz

OUT 74C74 ÷ 2

TOØ1

POINTS

TOØ2

POINTS

Q Q54.2k*

TO LTC201 V+ PIN

5V

5V –5V

5V 5V

925Hz

TO LTC201 V– PIN

1µF

909Ω**

5V

–5V

909Ω**

LSK389

300Ω

499Ω**

100k

+

+


AN113-9

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Figure 19, measured over a 50 second interval, shows 40nVP-P noise in a 0.1Hz to 10Hz bandwidth. This is spec-tacularly low noise for a JFET-based design and is directly attributable to input pair area and current density.

Wideband, Chopper Stabilized FET Amplifi er

The previous circuit’s bandwidth is limited because the chopping occurs within the signal path. Figure 20’s circuit circumvents this restriction by placing the stabilizing ele-ment in parallel with the signal path. This maintains DC performance although noise triples to 125nV in a 0.1Hz to 10Hz bandpass.

FET pair Q1 differentially feeds A2 to form a simple low noise op amp. Feedback, provided by R1 and R2, sets closed loop gain (in this case 1000) in the usual fashion. Although Q1 has extraordinarily low noise characteristics, its offset and drift are relatively high. A1, a chopper stabi-lized amplifi er, corrects these defi ciencies. It does this by measuring the difference between the amplifi er’s inputs and adjusting Q1A’s channel current to minimize the difference. Q1’s drain values ensure that A1 will be able to capture the

Figure 21. Figure 20 Responds to a 1mV Input. 12µs Rise Time Indicates 29kHz Bandwidth at A = 1000.

Figure 22. Chopper Stabilized FET Pair Noise Measures 125nV in 0.1Hz to 10Hz Bandpass.

Figure 20. Placing Stabilizing Amplifi er Outside Signal Path Permits Bandwidth Increase over Previous Circuit. Noise Triples to 125nV in 0.1Hz to 10Hz Bandpass.

Figure 19. Amplifi er 0.1Hz to 10Hz Noise Measures 40nVP-P in 50 Second Sample Period.

+

–A1

LTC2050HV

–5V

+

–0.22µF

Q1LSK-389

0.02µF

A2LT1797

AN113 F20

2k 2k*

R210k

R110Ω

499Ω*

499Ω*

5V

IN

1k*

499Ω*

100k

100k

0.02µF

* = 1% METAL FILM RESISTOR

VOS = 3µV TCVOS = 0.05µV°/C NOISE = 125nV

0.1Hz -10Hz Ib = 500pA

GAIN =

AVOL = >106

BW = 29kHz

R2R1

+ 1

A B

VERT. =20nV/DIV

HORIZ. = 5sec/DIV AN113 F19

VERT. =0.2V/DIV


VERT. =50nV/DIV

HORIZ. = 1sec/DIV AN113 F22


AN113-10

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offset. A1 supplies whatever current is required to Q1A’s channel to force offset within 5µV. Additionally, A1’s low bias current does not appreciably add to the overall 500pA amplifi er bias current. As shown, the amplifi er is set up for a noninverting gain of 1000, although other gains and inverting operation are possible.

Placing the offset correction in parallel with the signal path permits high bandwidth. Figure 21 shows response to a 1mV input. The 12µs risetime indicates 29kHz bandwidth at A = 1000.

Figure 22’s photo measures noise in a 0.1Hz to 10Hz bandwidth. The performance obtained is almost 6 times

better than any monolithic chopper stabilized amplifi er, while retaining low offset and drift.

Submicroampere RMS Current Measurement for Quartz Crystals

Quartz crystal RMS operating current is critical to long-term stability, temperature coeffi cient and reliability. Ac-curate determination of RMS crystal current, especially in micropower types, is complicated by the necessity to minimize introduced parasitics, particularly capacitance, which corrupt crystal operation. Figure 23’s high gain, low noise amplifi er combines with a commercially available

Figure 23. A1 to A4 Furnish Gain of >200,000 to Current Probe, Permitting Submicroamp Crystal Current Measurement. LTC1563-2 Bandpass Filter Smooths Residual Noise While Providing Unity Gain at 32.768kHz. LTC1968 Supplies RMS Calibrated Output.

+

–

LTC1440

39pF

AN113 F23

1.2M

32.768kHz

CRYSTAL OSCILLATORTEST CIRCUIT

A = 224,000

A = 1120 (CT-1 GAIN ERROR AT32.768 kHz ≈12%; SEE TEXT)

A = 200

32.7kHzBANDPASS FILTER

OUT0V-1V = 0µA-1µA

RMS

TEKTRONIX CT-1CURRENT PROBE5mV/mA (5µV/µA)

2M

49.9Ω*

49.9Ω*

1740Ω*

CI

2V

2V

5V

1µF

–5V

1M

+

–

A1LT1028

10pF

1.5k*

825Ω*

61.9Ω*

49.9Ω*

1k

+

–

A2LT1222

RCAL39Ω

(SEE TEXT)

+

–

A3LT1222

825Ω*

63.4Ω*

+

–

A4LT1222

+

–A5

LT1077

LTC1563-2

+V

G

LTC1968OUT

10k

10k

* = 1% METAL FILM RESISTOR = EPSON C-100R

10µF, 1µF = WIMA MKS-2 E

I2

I1

RSA LPB

42.2k*

84.5k*

20k*

21k*

LP V+

INVA INVBLPA

GND

–5V

5V

5V

5V

0.01µF

0.1µF

V–

SB

EN

10µF 1µF

10µF

5.62k* 24.9k*

43k

RMS DCCONVERTER


AN113-11

an113f

closed core current probe to permit the measurement. An RMS-to-DC converter supplies the RMS value. The quartz crystal test circuit shown in dashed lines exemplifi es a typical measurement situation. The Tektronix CT-1 current probe monitors crystal current while introducing minimal parasitic loading. The probe’s 50Ω terminated output feeds A1. A1 and A2 take a closed loop gain of 1120; excess gain over a nominal gain of 1000 corrects for the CT-1’s 12% low frequency gain error at 32.768kHz.5 A3 and A4 contribute a gain of 200, resulting in total amplifi er gain of 224,000. This fi gure results in a 1V/µA scale factor at A4 referred to the gain corrected CT-1’s output. A4’s LTC1563-2 bandpass fi ltered output feeds an LTC1968-A5 based RMS→DC converter which provides the circuits output. The signal processing path constitutes an extremely narrow band amplifi er tuned to the crystal’s frequency. Figure 24 shows typical circuit waveforms. Crystal drive, taken at C1’s output (trace A), causes a 530nA RMS crystal current which is represented at A4’s output (trace B) and the RMS→DC converter input (trace C). Peaking visible in trace B’s unfi ltered presentation derives from parasitic paths shunting the crystal.

Typical circuit accuracy is 5%. Uncertainty terms include the transformer’s tolerances, its ≈1.5pF loading and re-sistor/RMS→DC converter error. Calibrating the circuit

reduces error to less than 1%. Calibration involves driving the transformer with 1µA at 32.7kHz. This is facilitated by biasing a 100k, 0.1% resistor with an oscillator set at 0.100V output. The output voltage should be verifi ed with an RMS voltmeter having appropriate accuracy (see Reference 8’s Appendix B). Figure 23 is calibrated by padding A2’s gain with a small resistive correction, typically 39Ω.

Direct Reading Quartz Crystal-Based Remote Thermometer

Although quartz crystals have been used as temperature sensors (see References 7 and 10) there has been almost no adaptation of this technology. The primary impediment has been lack of standard product quartz crystal tempera-ture sensors. The advantages of quartz-based temperature sensing include nearly purely digital signal conditioning, good stability and a direct, noise immune digital output ideally suited to remote sensing.

Figure 25 utilizes an economical, commercially available (Reference 9) quartz temperature sensor in a direct read-ing thermometer scheme suited to remote data collection. An LTC485 transceiver, set up in transmit mode, forms a quartz-based, Pierce class oscillator. The transceiver’s differential line driving outputs provide frequency coded temperature data to a 1000 foot cable run. A second RS485 transceiver differentially receives the data, presenting a single ended output to the PIC-16F73 processor. The pro-cessor converts the frequency coded temperature data to its °C equivalent, which appears on the display. Figure 26 is a software listing of the processor’s program.6 Accuracy over a sensed –40°C to 85°C range is about 2%.

Figure 24. C1’s 32.768kHz Output (Trace A) and Crystal Current Monitored at A4 Output (Trace B). RMS Converter Input Is Trace C. Peaks in Trace B’s Unfi ltered Waveform Derive From Inherent and Parasitic Paths Shunting Crystal.

Note 5. The validity of this gain error correction at one sinusoidal frequency –32.768kHz—was investigated with a 7-sample group of Tektronix CT-1s. Device outputs were collectively within 0.5% of 12% down for a 1µA 32.768kHz sinusoidal input current. Although this tends to support the measurement scheme, it is worth noting that these results are as measured. Tektronix does not guarantee performance below the specifi ed –3dB 25kHz low frequency roll-off.Note 6. Mark Thoren of LTC designed the processor-based circuitry and authored Figure 26’s software.

C = 1µA/DIV

A = 2V/DIV

B = 1µA/DIV



AN113-12

an113f

–

+1k

3.3MY1

1M10M

LTC485LTC485

PIC-16F73

D1BAV74LT1

10k

5V5V

5V

86

7

1

25

3

OSC1

OSC2

MCLR

SENSOR IS Y1 = EPSONHTS-20640kHz/25°C–29.6ppm/°C

100Ω

RC7RC6RC5RC4RC3RC2RC1RC0

RB7RB6RB5RB4RB3RB2RB1RB0

RA5RA4RA3RA2RA1RA0

1917161514131211

2827262524232221

765432

28

9

818

10

1

VDO

Y110MHz

2 × 16 CHARACTERLCD DISPLAY

(OPTREX DMC-162498OR SIMILAR)

1000 FEETTWISTED PAIR

AN113 F25

VCC

CONTRAST

GND

D7D6D5D4EN

RWRS

100k

6

5V

5V

4

5

7

82

3

10pF 10pF 15pF

100pF0.1µF

R1, 10k

Figure 25. Quartz Crystal-Based Remote Thermometer Has 2% Accuracy over –40°C to 85°C Sensed Range, Drives 1000ft Cable. RS-485 Transceiver Oscillates at Y1 Quartz Sensor Determined Frequency and Drives Cable. Second Transceiver Receives Data and Feeds Processor. Display Reads Directly in °C.

/* Thermometer based on Epson HT206 temperature sensing crystal. Output is to a standard Epson HD447980 based alphanumeric LCD display. LCD driver functions are part of compiler library

Written for CSS compiler version 3.182

*/

#include <16F73.h>#device adc=8#fuses NOWDT, HS, PUT, NOPROTECT, NOBROWNOUT#use delay (clock=10000000) // Tell compiler how fast we’re going#use rs232(baud=9600, parity=N, xmit=PIN_C6, rcv=PIN_C7, bits=8)#include “lcd.c” // LCD driver functions

void main( ){ int16 temp; unsigned int16 f; setup_adc_ports(NO_ANALOGS); setup_adc(ADC_OFF); setup_spi (FALSE); setup_counters (RTCC_INTERNAL, RTCC_DIV_1); setup_timer_1 (T1_EXTERNAL|T1_DIV_BV_1); setup_timer_2 (T2_DISABLED, 0, 1); lcd_init( ); // Initialize LCD

while(1) ( set_timer1(0); // Reset counter setup_timer_1(T1_EXTERNAL|T1_DIV_BY_1); // Turn on counter delay_ms(845); // 0.845412 is the magic time to count delay_us(412); // -it gives 1 less plus per degree C setup_timer_1(T1_DISABLED); // turn off counter f = get_timer1(); // Read result temp = 33770 – f + 25; // Convert to temperature

//** At this point ‘f’ is the temperature in degrees C **// //** For this experiment, dump to standard HD44780 type LCD display **//

lcd_putc(‘\f’); // Clear screen lcd_gotoxy(1, 1); // Goto home position printf(lcd_putc, “%ld”, temp); // And display result }}

Figure 26. Software Listing for PIC Processor Program. Code Converts Frequency to °C Equivalent, Drives Display.


AN113-13

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Figure 27. 1Hz to 100MHz V→F Converter Has 160dB Dynamic Range, Runs From 5V Supply. Input Biased Servo Amplifi er Controls Core Oscillator, Stabilizing Circuit’s Operating Point. Wide Range Operation Derives From Core Oscillator Characteristics, Divider/Charge Pump-Based Feedback and A1’s Low DC Input Errors.

AN113 F27

FEEDBACKDIVIDER

74HC4060 ÷ 16

74AHC74 ÷ 4

+

–

A1LTC1150

Q1 PI CLR1

CLK1 CLK2

D1

5V

5V

10µF10µF

CLK

20Ω

1µF

33Ω

5V510k

1Hz2k

2kLINEARITY(60MHz)

CHARGE PUMP

SERVO AMP.

6.19k*

10k

∑

510k

0.1µF

C120pF

1µF

7.5kD1

12k

120Ω

120Ω

I1

–V BIAS GENERATOR

≈–3VDC HERE

5V

NCQ12N3906

Q22N3904

COREOSCILLATOR

I2

Q2

Q4

CLR

LT14602.5V

LTC6943

FOUT1Hz TO 100MHz

P2 CLR2D2

14

5V

D1 = JPAD-500; LINEAR SYSTEMS = 74ACH14, GROUND UNUSED INPUTS

= BAT-85 * = IRC-MAR-6, 1% RESISTOR ** = WIMA FKP-2 1µF, 0.22µF = WIMA MKS-2CIRCLED AREA = AIR WIRED, MINIMUM AREA, MINIMIZE STRAY

CAPACITANCE, RELIEVE GROUND PLANE 20pF = AG MICA DASHED AREA = LEAKAGE GUARD TRACE

10k

100MHz

1k

1.5k*

0.22µF

16

12

511

4

13

1

2

9

6

7

10

100Ω*100pF**

100pF**

1µF

+ +

VIN – 0V TO 5V

01


AN113-14

an113f

1V/DIVAC COUPLED

2V/DIV

HORIZ. = 5ns/DIV AN113 F28

2V/DIV(ON 0.05VDC)

1V/DIV


1Hz-100MHz V→F Converter

Figure 27’s circuit achieves a wider dynamic range and higher output frequency than any commercially available voltage to frequency (V→F) converter. Its 100MHz full-scale output (10% overrange to 110MHz is provided) is at least ten times faster than available units. The circuit’s 160dB dynamic range (8 decades) allows continuous operation down to 1Hz. Additional specifi cations include 0.1% linearity, 250ppm/°C gain temperature coeffi cient, 1Hz/°C zero shift, 0.1% frequency shift for VSUPPLY = 5V ± 10% and a 0V to 5V input range. A single 5V supply powers the circuit.7

A1, a chopper stabilized amplifi er, servo biases a crude but wide range core oscillator in Figure 27. The core oscillator drives a charge pump via digital dividers. The averaged difference between the charge pump’s output and the circuit’s input appears at a summing node (∑) and biases A1, closing a control loop around the wide range core oscillator. The circuit’s extraordinary dynamic range and high speed derive from core oscillator characteristics, divider/charge pump-based feedback and A1’s low DC input errors. A1 and the LTC6943-based charge pump stabilize circuit operating point, contributing high linearity and low drift. A1’s low offset drift allows the circuit’s 50nV/Hz gain slope, permitting operation down to 1Hz at 25°C.

The positive input voltage causes A1 to swing nega-tively, biasing Q1. Q1’s resultant collector current ramps C1 (trace A, Figure 28) until Schmitt trigger inverter I1’s output (trace B) goes low, discharging C1 via Q2. C1’s discharge resets I1’s output to its high state, Q2 goes off

and the ramp-and-reset action continues. D1’s leakage dominates all parasitic currents in the core oscillator, ensuring operation down to 1Hz. The ÷64 divider chain’s output clocks the LTC6943-based charge pump. The charge pump’s two sections operate out-of-phase, resulting in charge transfer at each clock transition. Charge pump stabil-ity is primarily determined by the LT1460 2.5V reference, the switches low charge injection and the 100pF capaci-tors. The 0.22µF capacitor averages the pumping action to DC. The averaged difference between the input derived current and the charge pump feedback signal is amplifi ed by A1, which biases Q1 to control circuit operating point. Core oscillator nonlinearity and drift are compensated by A1’s servo action, resulting in the high linearity and low drift previously noted. A1’s 1µF capacitor provides stable loop compensation. Figure 29 shows loop response (trace B) to an input step (trace A) is well controlled.

Some special techniques enable this circuit to achieve its specifi cations. D1’s leakage current dominates all parasitic currents at I1’s input; hence Q1 must always source current to sustain oscillation, assuring operation down to 1Hz. The 100MHz full-scale frequency sets stringent restrictions on core oscillator cycle time. Only 10ns is available for a

Figure 28. V→F Operation at 40MHz. Core Oscillator Wave-forms Viewed in 670MHz Real Time Bandwidth Include Q1 Collector (Trace A) and Q2 Emitter (Trace B). Ramp-and-Reset Operating Characteristic Is Apparent; Reset Duration of 6ns Permits 100MHz Repetition Rate.

Figure 29. Response (Trace B) to an Input Step (Trace A) Shows 30ms Settling Time at Summing Junction (Σ). A1’s 1µF Capacitor Shapes Response, Stabilizing Feedback Loop. Clamped Response on Negative Going Input Step is Due to Summing Junction Limiting.

Note 7. Reference 12 (1986) contains a circuit with comparable specifi cations although considerably more complex than the one presented here. The advent of high speed CMOS logic permitted replacing the earlier designs ECL elements, facilitating a dramatic decrease in complexity. Comparing the designs permits viewing the impact a technology shift can have in realizing a circuit function. In this case, the effect is pervasive, directly or indirectly infl uencing nearly every aspect of circuit operation. While circuit architecture is consistent, this incarnation is substantially and favorably altered.


AN113-15

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Note 8. Avalanche mode pulse generation is a subtle, arcane technique requiring extensive discussion. The text’s cavalier treatment is deliberately brief in order to maintain focus on this circuit’s low timing jitter characteristics. More studious coverage can be found in References 13-22.

complete ramp-and-reset sequence. The ultimate speed limitation is the reset interval. Figure 28, trace B, shows a 6ns interval, comfortably within the 10ns limit.

A scaled resistive path from the input to the charge pump corrects small nonlinearities due to residual charge injec-tion. This input derived correction is effective because the charge injections effect varies directly with input determined frequency.

Prototype and small lot construction may proceed using the schematic and its notes, but component selection should be considered for volume production. Figure 30 lists applicable components and their selection targets.

To calibrate this circuit apply 5.000V and trim the 100MHz adjustment for a 100.0MHz output. Next, ground the input and adjust the 1Hz trim for 1Hz output. Allow for long set-tling time, as charge pump update rate at this frequency is once every 32 seconds. Note that this trim accommodates either offset polarity because of the –V bias derived from A1’s clock output. Finally, set the 60MHz adjustment for 60.0MHz with 3.000VIN. Repeat these adjustments until all three points are fi xed.

Delayed Pulse Generator with Variable Time Phase, Low Jitter Trigger Output

Fast circuitry often requires a pulse generator that also supplies a variable time phase trigger output. It is desirable that the main output pulse occurrence be continuously settable from before to after the trigger output with low time jitter. Figure 31’s circuit produces a 360ps risetime output pulse with trigger output time phase variable from –30ns to 100ns. Jitter is 40ps.

COMPONENTSELECTION PARAMETER

(25°C)TYPICAL YIELD

(%)

Q1 ICER < 20pA at 3V 90

Q2 IEBO < 20pA at 3V 90

D1 IREV < 500pA, > 75pA at 3V 80

I1 IIN < 25pA 80

A1 IB < 5pA at VSUPPLY = 5V 90

74ACH74 Operate with 3.6nS Wide(50% Point) Input Pulse

80

Q1 and Q2 form a current source that charges the 1000pF capacitor. When the LTC1799 clock is high (trace A, Fig-ure 32) both Q3 and Q4 are on. The current source is off and A2’s output (trace B) is at ground. C1’s latch input prevents it from responding and its output remains high. When the clock goes low, C1’s latch input is disabled and its output drops low. The Q3 and Q4 collectors lift and Q2 comes on, delivering constant current to the 1000pF capacitor. The resulting linear ramp at A2 (trace B) is ap-plied to bounded current summing amplifi ers A3 and A4. Both amplifi ers compare ramp induced current with fi xed, opposite polarity currents derived from A1 – Q6. A1-Q6, in turn, is referred to the +5 supply rail which also sets Q1-Q2 current and hence, ramp slope. This ratiometric connection promotes supply rejection. When A4 and A3 (traces C and F, respectively) come out of diode bound and cross zero, comparators C2 and C1 (traces D and G, respectively) are heavily overdriven and switch rapidly. C2’s output path includes components which form trace E’s trigger output pulse. C1 triggers output pulse generator Q5, operating in avalanche mode (trace H).8

The “delay adjust” control sets the ramp amplitude that A3-C1 switches the main output at, providing the desired variable time phase with respect to the A4-C2 controlled trigger output. Time jitter between C1 and C2 outputs is minimized because A3 and A4 effectively multiply ramp transition rate as their outputs enter the active region, provide gain and cross zero.

Figure 30. Selection Criteria for Components Ensure V→F Performance. First Five Entries Enhance Operation Below 100Hz. Last Entry Assures Reliable Feedback Divider Operation.


AN113-16

an113f

Figu

re 3

1. P

ulse

Gen

erat

or O

utpu

t Tim

e Ph

ase

Varie

s –3

0ns

to 1

00ns

with

Res

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to Tr

igge

r Out

put;

Jitte

r Is

40ps

. Clo

cked

Ram

p at

A2

Prod

uces

Var

iabl

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3-C1

) and

Fix

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4-C2

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ays

Driv

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Puls

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, Res

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rs a

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Poi

nt, M

inim

izin

g Ti

me

Jitte

r Bet

wee

n Ou

tput

s.

10k

AVAL

ANCH

EBI

ASAD

JUST

162Ω

*

4.7k

4.7k

274Ω

*

100Ω

*(1

00ns

CALI

B.)

47pF

–5V

49.9

k*

1.2k

*

221Ω0.00

1µF

Q1

–5V

5V

–5V

330Ω

1k

10k

330Ω

6 FE

RRIT

EBE

ADS

(SEE

NOT

ES)

330Ω

4.02

k*

CLOC

K

10k

– +

10k*

Q2

470Ω

1N57

11

74AH

C14

Q3 Q4

2k*

(–30

nsCA

LIB.

)

499Ω

*20

0Ω*

C1

– +C2

L

L

L2

40",

50Ω

COI

LED

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LIN

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BAT-

85

100Ω

RING

ING

10pF

3pF

0.5p

F TO

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TRIG

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10nS

0.25

V

PULS

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ECTO

R

200Ω

**

200Ω

*

200Ω

**

200Ω

**

200Ω

**

2N25

01/

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69Q5 (S

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)

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Ω

RESI

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GROU

ND 2

00Ω

RES

ISTO

RS

DIRE

CTLY

AT

OUTP

UTCO

NNEC

TOR. 50

Ω

30pF

5pF

AN11

3 F3

1

– +A44.

02k*

– +

– +

–

A3

S

GND

DIV

OUT

+V5V

5V

5V

LTC1

799

200Ω

*

22µF

250Ω 25Ω

+

10µF

+

Q610

0Ω

+A1

A2

300Ω

+

6.19

k*

MP

P

1µF

10µF

39µF

100V

4.7µ

F10

0V10

0VP6

KE10

0A

F B

GND

V C

V IN

SW

5V

L1 220µ

H

13k

+10

0Ω

LT10

82

BAV-

21

M

1µF

100V M

≈60V

DELA

Y AD

JUST

–30n

s TO

100

ns

=

1N41

48

PNP

= 2N

5087

NP

N =

2N23

69

* =

1% F

ILM

RES

ISTO

R

**

=

1% F

ILM

, 120

6 SI

ZE

A1

= LT

1006

A2

-A4

= LT

1809

C1

, C2

= LT

1394

L1

= CO

ILCR

AFT

D033

16P-

224

L2

=

1TU

RN#2

2 W

IRE

0.05

”

DI

AMET

ER A

IR C

ORE

=

FER

RITE

BEA

D, F

ERRO

NICS

#21-

110J

=

POL

YPRO

PELE

NE

= M

YLAR


AN113-17

an113f

The A3-A4 amplifi er gain is the key to low jitter between C1 and C2’s switching times. The amplifi ers augment the comparator’s relatively low gain, promoting decisive switching despite the ramp input. Figure 33 shows A4 (trace A)-C2 (trace B) response to the ramp crossing the trip point. As the ramp nears the trip point A4 comes out of bound, providing an amplifi ed version of the ramp’s transition rate to C2. C2 responds by switching decisively 6ns after A4 crosses zero volts at center screen. A3-C1 waveforms are identical. Figure 34, Q5’s pulse output, taken with the oscilloscope synchronized to the trigger output, shows 40ps jitter in a 3.9GHz sampled bandpass.

Circuit calibration is accomplished by fi rst adjusting the “-30ns cal” so the main pulse output occurs 30ns before the trigger output with the “Delay Adjust” set to minimum. Next, with the “Delay Adjust” set to maximum, trim the “100ns cal” so the main pulse output occurs 100ns after the trigger output. Slight interaction between the 30ns and 100ns trims may require repeating their adjustments until both points are calibrated. As mentioned, the avalanche output stage is illustrative only and not detailed in this discussion. Its optimization and calibration are covered in Reference 13.

Figure 32. Low Jitter Delayed Pulser Waveforms Include Clock (Trace A), A2 Ramp (B), A4 (C), C2 (D), Trigger Output (E), A3 (F), C1 (G) and Delayed Output Pulse (H). Trigger-to-Output Pulse Delay Is Continuously Variable From –30ns to 100ns.

Figure 33. A4 (Trace A) - C2 (Trace B) Response to A2’s Ramp Crossing Trip Point. C2 Goes High 6ns after A4 Crosses Zero (Center Screen). A3-C1 Waveforms Are Identical.

Figure 34. Main Pulse Output Synchronized to Trigger Output Shows 40ps Jitter in 3.9GHz. Sampled Bandpass.

C = 2V/DIV

A = 5V/DIV

B = 5V/DIV

E = 5V/DIVF = 2V/DIV

G = 5V/DIV

H = 20V/DIV

D = 5V/DIV


A = 0.5V/DIV

B = 1V/DIV


VERT. =2V/DIV

HORIZ. = 100ps/DIV AN113 F34


AN113-18

an113f

REFERENCES

1. Williams, Jim, “Bias Voltage and Current Sense Circuits for Avalanche Photodiodes,” Linear Tech-nology Corporation, Application Note 92, November 2002, p. 8.

2. Williams, Jim, “Switching Regulators for Poets,” Ap-pendix D, Linear Technology Corporation, Application Note 25, September 1987.

3. Hickman, R. W. and Hunt, F. V., “On Electronic Voltage Stabilizers,” “Cascode,” Review of Scientifi c Instru-ments, January 1939, p. 6-21, 16.

4. Williams, Jim, “Signal Sources, Conditioners and Power Circuitry,” Linear Technology Corporation, Application Note 98, November 2004, p. 20-21.

5. Williams, Jim, and Thoren, Mark, “Developments in Battery Stack Voltage Measurement,” Application Note 112, Linear Technology Corporation, March 2007.

6. Williams, Jim, “Measurement and Control Circuit Collection,” Linear Technology Corporation, Applica-tion Note 45, June 1991. p. 1-3.

7. Williams, Jim, “Practical Circuitry for Measurement and Control Problems,” Linear Technology Corpora-tion, Application Note 61, August 1994. p. 13-15.

8. Williams, Jim, “Instrumentation Circuitry Using RMS-to-DC Converters,” Linear Technology Corporation, Application Note 106, February 2007. p. 8-9.

9. Seiko Epson Corp. Crystal Catalog. Models HTS-206 and C-100R. See also, p. 10-11, “Drive Level.”

10. Benjaminson, Albert, “The Linear Quartz Thermom-eter—A New Tool for Measuring Absolute and Dif-ference Temperatures,” Hewlett-Packard Journal, March 1965.

11. Williams, Jim, “Applications Considerations and Circuits for a New Chopper Stabilized Op Amp,” 1Hz-30MHz V→F, Linear Technology Corporation, Application Note 9, p. 14-15.

12. Williams, Jim, “Designs for High Performance Volt-age-to-Frequency Converters,” “1Hz-100MHz V→ F Converter,” p. 1-3, Linear Technology Corporation, Application Note 14, March 1986.

13. Williams, Jim, “Slew Rate Verifi cation for Wideband Amplifi ers,” Linear Technology Corporation, Applica-tion Note 94, May 2003.

14. Braatz, Dennis, “Avalanche Pulse Generators,” Private Communication, Tektronix, Inc. 2003.

15. Tektronix, Inc., Type 111 Pretrigger Pulse Generator Operating and Service Manual, Tektronix, Inc. 1960.

16. Hass, Isy, “Millimicrosecond Avalanche Switching Circuit Utilizing Double-Diffused Silicon Transis-tors,” Fairchild Semiconductor, Application Note 8/2, December 1961.

17. Beeson, R. H., Haas, I., Grinich, V. H., “Thermal Re-sponse of Transistors in Avalanche Mode,” Fairchild Semiconductor, Technical Paper 6, October 1959.

18. G. B. B. Chaplin, “A Method of Designing Transistor Avalanche Circuits with Applications to a Sensitive Transistor Oscilloscope,” paper presented at the 1958 IRE-AIEE Solid State Circuits Conference, Philadelphia, PA., February 1958.

19. Motorola, Inc., “Avalanche Mode Switching,” Chapter 9, p. 285-304. Motorola Transistor Handbook, 1963.

20. Williams, Jim, “A Seven-Nanosecond Compara-tor for Single Supply Operation,” “Programmable Subnanosecond Delayed Pulse Generator,” p. 32-34, Linear Technology Corporation, Application Note 72, May 1998.

21. D. J. Hamilton, F. H. Shaver, P. G. Griffi th, “Avalanche Transistor Circuits for Generating Rectangular Pulses,” Electronic Engineering, December 1962.

22. R. B. Seeds, “Triggering of Avalanche Transistor Pulse Circuits,” Technical Report No. 1653-1, August 5, 1960, Solid-State Electronics Laboratory, Stanford Electronics Laboratories, Stanford University, Stan-ford, California.


AN113-19

an113f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

23. Markell, R. Editor, “Linear Technology Magazine Circuit Collection, Volume I,” Linear Technology Corporation, Application Note 52, January 1993.

24. Markell, R. Editor, “Linear Technology Magazine Circuit Collection, Volume II,” Linear Technology Corporation, Application Note 66, August 1996.

25. Markell, R. Editor, “Linear Technology Magazine Circuit Collection, Volume III,” Linear Technology Corporation, Application Note 67, September 1996.

26. Williams, Jim, “Circuitry for Signal Conditioning and Power Conversion,” Linear Technology Corporation, Application Note 75, March 1999.

27. Williams, Jim, “Instrumentation Applications for a Monolithic Oscillator,” Linear Technology Corpora-tion, Application Note 93, February 2003. “Chopped Amplifi ers,” p. 9-10.


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