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An all-digital --frequency discriminator of arbitrary order

Atalla, E; Hegazi, E; Sjöland, Henrik; Ibrahim, M

Published in:IEEE International Symposium on Circuits and Systems, ISCAS 2006. Proceedings.

DOI:10.1109/ISCAS.2006.1693752

2006

Link to publication

Citation for published version (APA):Atalla, E., Hegazi, E., Sjöland, H., & Ibrahim, M. (2006). An all-digital ΣΔ--frequency discriminator of arbitraryorder. In IEEE International Symposium on Circuits and Systems, ISCAS 2006. Proceedings.https://doi.org/10.1109/ISCAS.2006.1693752

Total number of authors:4

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An All-Digital IA-Frequency Discriminator ofArbitrary Order

Essam Atalla', Emad Hegazi', Henrik Sj6land2, and Mohamed Marzouk Ibrahim''ECE Department, Ain Shams University,Cairo,Egypt,

2Department of Electroscience, Lund University, Sweden.emad.hegazigiclasu. edu.eg

Abstract-In this paper, we propose an all-digital frequency output of the synthesizer. High reference frequency (REF) issynthesizer architecture, based on an all-digital XA-frequency used to push the spurs far from the carrier. The need for highdiscriminator. The new all-digital synthesizer is compared to sampling frequency, in addition to the resolution beingpreviously published work. The architecture of the XA- dependent on the number of stages, both make the TDCfrequency discriminator is verified using behavioral power hungry. In this work, we show that using XA-noisesimulation. shaping techniques, we can avoid the use of a TDC and

implement an all-digital noise-shaped frequencyIndex terms- XAFD, D/A, TDC, digitally controlled oscillator discriminator of arbitrary order. In the proposed architecture,(DCO), frequency synthesizers, digital frequency synthesizer, improvement in fractional resolution is due to XA-noisefractional, all-Digital, sigma delta, phase domain, frequency shapin rather than fractional error correction using a TDC.discriminator, retiming, divider, quantizer.

FCW Loop~~~I+ ~~~~~Filter

I. INTRODUCTION DCOREF

Rapid scaling of transistor feature size mandates the CLKsearch for a new design style for analog and RF circuits. TDC ZExploiting the physical operation of the MOS device, i.e. a rF <*good switch, allows better utilization of MOS transistors in Lhigh frequency analog circuits. Such paradigm shouldfacilitate the integration of analog and digital circuits on the Figure 1. An All-Digital Phase-Domain Frequency Synthesizersame chip. Recently, an all-digital TX phase-domain phase The paper is organized as follows: Section II introduces thelocked loop frequency synthesizer was proposed [1][2]. The new frequency synthesizer architecture. Section III detailscore of the synthesizer is a digitally controlled oscillator, the architecture for our proposed XA frequency discriminatorDCO [3]. A simplified block diagram of this synthesizer is (XAFD), and compares it to that published in [5]. In sectionshown in Fig. 1. Here, the concept of phase detection is IV, a divider-less version of our .AFD is proposed. Inbased on accumulating the reference and DCO phase '. . . l linformation and obtaining the phase difference throughfixed-point subtraction [2]. In order to guarantee that phasedetection is correct although the DCO and reference (REF) II. A XA DISCRIMINATOR-BASED ALL-DIGITAL PLLsignals origin from different clock domains, reference ARCHITECTUREretiming is adopted by sampling the reference edge using the The proposed synthesizer architecture is shown in Fig.2. TheDCO edge [2]. As a result of retiming, there is a fractionalphase error that may degrade the overall resolution of the coreotensynthesizerithe IF whichoraesuas aAsynthesizer. That is why a time-to-digital converter (TDC), frequency-to-digtal converter. It extracts the frequency of

1 1 1- r * 1 * * ^ ~~~the DCO signal, compares it to a reference frequencywas employed to correct this fractional error. In conjunctionwith the TDC circuit an averaging real-time technique is (XREF), and produces a noise shaped digital bit streamused to calculte DC clock peroean aechic foir whose average is proportional to the frequency error betweencalculating the inverse of a number [4]. These are used to the DCO and the XREF signals. The output bit stream isnralcutiz thefr se correction facTor at hedDCo compared to the input frequency control word of thenormalize the fractional phase correction factor at the DCO snhszr(FW)i re opoue nefrsga,ooutput to one DCO clock period. This approach suffers from synthesizer (RFCW) mi order to produce an errorsignal, onmutil diavntgs th copext an power........... which the whole synthesizer operates, that is digitally filtered

consumption of the TDC in addition to the need of the and then applied to the DCO to control the output frequencyionvseucircuitryofparTiCul tadditih oethe at te CO of the synthesizer. A similar architecture based on a secondinverse circuitry particularly that they operate at the DCOodrYF a rvosypbihd[] n[] naaorate. Nonlinearities in the TDC circuit introduce spurs at the order XAFD was previously published [6]. In [6], an analog

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voltage signal controls the oscillator. Therefore, a high providing second order noise shaping. This architectureresolution D/A is needed after the digital loop filter, which suffers many drawbacks: First, its intensive use of analogadds more complexity to the synthesizer. Extending that in blocks which are difficult to design and prone to process[6] to a higher order noise shaper is possible at the price of mismatches. Second, it uses a multi-modulus divider asadding analog components. A second order discriminator result of the single loop implementation [5]. Third, is hasutilizing intensive analog blocks: charge pump, analog buffer nonlinearities due to PFD dead zone and charge pumpand opamp comparator was reported in [5]. The main leakage. Fourth, the charge pump, the comparator and thecontribution of our work is an all-digital architecture PFD all contribute to the overall output noise of theimplementing a XAFD that is extendable to higher orders discriminator, especially the charge pump, which eventuallywith purely digital components. In this work, a DCO replaces degrades the resolution. Finally, extending this architecturethe voltage controlled oscillator to implement an all-digital to higher orders is not possible because it is difficult toXAFD-based synthesizer where the XAFD is of arbitrary control the stability of the loop using analog gains.order to enhance the frequency resolution.

B. The new all-digital architectureRF_W,/- RF The block diagram ofthe proposed architecture is shown

in Fig. 5 for a first order XAFD. The divider acts as a phaseaccumulator. The phase detection circuit employs

GD0 -Frequency accumulation of the edges of the DIV and REF signals anddiscriminator _ simple arithmetic subtraction to produce the phase error.

Thus, the phase error is available as a binary number. Thequantization is achieved by simple truncation of the LSBs.

XREF Only the sign bit is used for modulus control. Retiming isemployed to guarantee correct phase detection [2]. This is

Figure 2. An All-Digital YAFD-based Frequency Synthesizer done by oversampling the external reference signal (XREF)

In the following section, we explain the operation of the by the input (RF) signal, to produce the retimed reference' . . ~~~~~signal (REF) whose phase iS the reference of theX,AFD in more detail. The proposed architecture is compared scinatrItE i whorthametio thatrif[2]theresutho

to previou workto sow its advntages. dscriminator. It iS worth mentioning that in [2] the result ofto prviu wrtho tsavatge,the phase detection is the error signal that defines the

resolution of the whole synthesizer and that is why the TDCIII. XA-FREQUENCY DISCRIMINATOR was needed to correct for fractional errors due to retiming.

But in our architecture, the phase error is already quantized,A. Principle ofoperation andprevious work and the errors due to retiming are not significant, because the

The first published XAFD is shown in Fig. 3 [7]. The resolution is achieved through sigma-delta noise shaping andquantity that is XA-modulated here is the period of the input not phase detection accuracy as in [2].signal. The input frequency is accumulated into phase. This EFphase signal is compared to a reference signal phase Comparatorproducing a phase error signal that is quantized to a single bit RF- divider ± OTby the DFF. The shown loop acts as a first order noise shaperwith a single bit quantizer. In [7], the phase error signal isnot available, yet the DFF performs both the phase detectionand quantization where its output is a binary digital voltagesignal that indicates whether the signal phase leads or lags Figure 4. Single loop second order YA Frequency Discriminator [5]the reference phase. RF I -Phas

D-FF N/N+1 I7 OUT-RE DIV OUT ~M_C Is

1 D Qgn

McI REFt XREF

Figure 3. First order YA Frequency Discriminator [7]

Since the phase error signal is not available, direct extension Figure 5. The new first order YA Frequency Discriminatorof the architecture to higher orders to provide better noise Another advantage of this circuit is that the phase error isshaping and higher frequency resolution is not straight available asanumber. This allows extending the architectureforward. A single-loop 2n order discriminator shown in Fig. to higher orders without need for analog blocks. A second4 was implemented in [5], using a PFD for phase error order XAFD using this technique is shown in Fig. 6. Thedetection and converting the phase error into an analog phsdecto.phasedet cilncrcuit iS similar to that shown in Fig. 5.signal which iS integrated using a charge pump, thus Only an extra digital accumulator is added to accumulate the

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phase error and provide second order noise shaping. It is in Fig. 5. Now the feedback that governs the XA-operation isstraightforward to extend the XAFD to higher orders using achieved by simple addition. This architecture has two mainconventional XA-modulators design techniques where advantages. First, multi-bit quantization does not add anyscaling coefficients are designed to provide arbitrary signal complexity compared to the architecture in Fig. 5, whichtransfer functions and noise transfer functions. In addition, a requires a multi-modulus. Second, the overall noisemulti-bit discriminator can be easily implemented to provide performance of the discriminator is improved because thehigher resolution and larger dynamic range and improve divider is removed. Of course, this is at cost of the higherstability by reducing quantizer overloading [8]. This is done power consumption in the accumulator clocked by RF input.by controlling a multi-modulus divider at the input with Phasemultiple bits of the phase error (for first order) or theaccumulated phase error (for higher orders) instead of using ign

the sign bit only. All the signals in the new XAFD, except XREFthat for the divider, are represented as fixed-point numbers FCWthat cannot be corrupted by noise [9] whereas in [5], thecharge pump is the main noise contributor in thediscriminator. In [1] and [2], the TDC, is the only noise Figure 8. The Divider-less first order YA Frequency Discriminatorcontributor in the phase detection technique.

REF V. SIMULATION RESULTS

RF Phase V All simulations used behavioral Matlab models thatDVPae error OUTNIN1 rdetection ± capture finite word-length effects. In all simulations, theMC XREF Sign lower modulus of the divider is set to four, the reference

AccumulatorAcuultREF frequency is 1.0 GHz, and the spectrum is calculated usingREFs 2A16 FFT points with Blackman-Harris windowing. Fig. 9

shows the output PSD of the Ist and 2nd order XAFDs shownin Fig. 5 and Fig.6 respectively. It is obvious that noise floor

Figure 6. The new second order YA Frequency Discriminator drops by about 5dB in the divider-less architecture case. Thiscorresponds to 0.54 bits of resolution improvement. Fig. 10

The proposed architecture can be easily modified into an all shows the output PSD of the M\ASH 1-1 2nd order XAFD indigital multistage noise shaper (MiASH) XAFD that avoids Fig.7. Fig. 11 shows a comparison for different values of theany delay mismatches compared to those reported in [10]. number of accumulator bits, Nacc. They are all compared toSince the phase error is available as a number, it can be fed the case of ideal accumulator which is the top graph into a second stage and then use an error combining circuit to Fig.11. In this figure all bit-streams are for input frequencyproduce the higher order noise-shaped bit-stream. A M\ASH equal to 4.036 Fref. It can be shown that Nacc = 7 is most1-1 XAFD is shown in Fig. 7. The second stage is simply a similar to the ideal case. All graphs are similar in the steadyIst order XA-modulator. Similarly, we can produce any state. But during the start-up, Nacc= 7 is the only curve thatMASH architecture where the first stage is always a XAFD gives ideal response. The conclusion we have is that systemand the next stages are XA-modulators. dynamics are dependent on the number of accumulator bits,

but Nacc= 7 is sufficient to give the required response. Fig. 12RF DIV Ph ase shows the response of the 2nd order XAFD to an input

NN d Cmbining frequency step equal to 0.8Fref. The XAFD starts from ajiMCXREF Sign A i locked state at Fin = 4.1 GHz and jumps to Fi = 4.9GHz.

Settling time is in the order of 60 ns, using Nacc= 7.First order

. ) Sigma-DeltaModulator -60 ii[ii ii ii iiii ii[ii iiiii

I8 1111 II H

11 11

1-1 H H 111111 I1 1 1

Figure 7. The newMASH 1-I YAFrequency Discriminator -80 __IIII L I I I iLI - I

IV. DIVIDER-LESS XA-FREQUENCY DISCRIMINATOR - order(Divider-based) I H+ +IH II41111 1/ 111Ir er11Divie1b s d I-141111 1 1-1111

By the same token of phase detection, the XAFD can / " K^ ~~~~~~~~~~~-140--I-I t Itm- h It -I-l t t lM 1Itl It - I-I1-I ti It-

detect the phase difference between two signals at different ,^II 1111 IIIII

frequencies using a small modification. The control word at -160 TiT-,FIlII-dir(-Ie -sI-1i-1l1 order(Divider-Less) II ' lIl li Hlllthe input of the accumulator clocked by the lower frequency --I ll_I II II 1111 111111 I III

. . i r . zs 180 _ _~~~~~~~~~~~~~~~~~~~~~~~ _IHil _11 II I iiS set to N, th1e ratio of th1e higher frequency to the lower IIIllllllX i ilIIIlllllIIIllllfrequency, instead of 1. This guarantees correct phase -200 ___- I II_ l l_||_ _

Fig. 8. The frequency control word (FCW) is equal to N, 1201 10 106 107 108 10which corresponds to the lower division factor ofthe divider

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Figure 9. Output PSD ofthe first and second order -A Frequency VI. CONCLUSIONSDiscriminators shown in Fig. 5, Fig. 6 and Fig. 8

A new, all-digital XAFD architecture was introduced for use-60 in frequency synthesis. The proposed architecture has the

111111;1ly11111111lll :yD^11 advantage of being extendable to higher orders, where the-80 -_ _ I I HIII _I_I Il I Il l iil _II I iilI_-I1 II 1_l,111111 1 1t1 1 W Kdesign methodology is similar to that of conventional XA-

-100__1;4-14 I-I-X- 4-11- 44 I4Ill- - 41W 141 1 modulators. Thus, the STF and the NTF are arbitrary and can111111111 li I" ' 11 IIIII III 1 1 11III be optimized to achieve a desired performance. In addition-120 - - I 1T -I- l-l r, B decmI ir -i m-r4bTIe

the new architecture can be configured into MASH-140 _ _1111111_ _ _ _11111 _ _ _ _iTiFii ____m _______structures. VWhen has multiple advantages in the context ofI1 111111 1 1 1111111 11 1 111 1 1 1111111 1 1 111111sytei r.tow a .VJL.In

-160 -I-14-II-IIU-I-I-I1"II 1-4-II_111-I-14141w- 1414. frequency synthesizers. Compared to what was reported inI H1i1 II11HM [2], the removal of the TDC simplifies the circuit and

-180 ICtltIIIItIt ttMIltIItIlmtttlt180|111111 1 1 1 I 1111 1 1 111 1 1 1 111ll reduces the sampling frequency because there are no spurs-200 I- l-11IH1111:1111111II ITIII due to TDC nonlinearities that need to be pushed to high

I.... :...t:I I.1...~ I 11111.111frequencies. This is in addition to the reduction in power2204 le lo' o10' 10 10o' consumption, and the expected improvement in the overallphase noise performance. In addition, a divider-less XAFD

Figure 1O. Output PSD of the MASH 1-I second order YA Frequency was proposed. It provides better noise performance andDiscriminator shown in Fig. 7 makes multi-bit quantization easier because there is no need

Fin = 4.036 Fref for a multi-modulus divider.

Ideal acc r REFERENCES

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Discriminator shown in Fig. 6 showing response to an input frequency step IEEE Symposium on Circuits and Systems (ISCAS), vol. 1, pp. 408-equal to 0.8Fref where Nacc = 7 41 1, June 1998.

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