An Abstract Model of De-synchronous Circuit Design and

Its Area Optimization

Jin Gang

University of Manchester

Overview

• Motivation

• Design flow

• Abstract model － Control Graph

• Timed Petri-net model for Control Path

• Performance Evaluation

• Area Optimization

• Conclusion

Motivation

• Asynchronous Circuit– Benefit

• Low power• Better EMC• Modularity

– Drawback• Difficult to design

Motivation

• De-synchronous Circuit– Benefit

• Benefit from Asynchronous• Design within synchronous design tools

– Drawback• Not the original asynchronous design method• May introduce some area overhead into circuit

Design Flow

• Datapath design is the same as synchronous counterpart

• More concern need to give to the control path

RTL Level RTL Simulation

Logic SynthesisDesignWare Cell Library

Gate Level Netlist of Control Path

Gate Level Netlist(Latch)

Combine Gate Level Netlist

Gate Level Simulation

Back End Design

Gate Level Netlist(Register)

Design Flow

1. Split each flip-flop into a master-slave latch pair.

2. Generate the matched delay unit for each combinational logic path.

3. Implement the local controller corresponding to each latch.

Control Graph

• An abstract model for control path

• Use a directed graph to represent the control path

• Purpose of this model– Evaluate the performance of the circuit– Optimize the circuit

Control Graph

1

01

0

0 1

L1 L2

L3L4

L5L6

L6

L5

L4

L3

L1

L2

Control Graph

L1Ri

Ai

Ro

Ao

L4Ri

Ai

Ro

Ao

L2Ri

Ai

Ro

Ao

L3Ri

Ai

Ro

Ao

C

L3Ri

Ai

Ro

Ao

L1Ri

Ai

Ro

Ao

L2Ri

Ai

Ro

Ao

L4Ri

Ai

Ro

Ao C

Timed Petri-net model for control path A Timed Petri-net

model for control path can be derived from control graph

L6

L5

L4

L3

L1

L2

Performance Evaluation

• Use the average cycle time to evaluate the performance of the de-synchronous circuit

• The performance evaluation is a linear programming problem

})(

{max0My

DxCyTi

TTi

i

Area Optimization

• Multi local controllers can be combined to a single local controller

• Condition– Only the local controllers with same polarity

can be combined– This combination can preserve the equality of

the circuit

Area Optimization

Area Optimization

• This optimization problem is NP-hard

• The optimizing procedure need be directed by the performance evaluation function, which can grantee the performance of the circuit

• This optimization is a trade-off between the area and the benefit of asynchronous circuit

Area Optimization

• Θ is the a threshold defined to control the maximal number of the latches can driven by a single local controller

• After the optimization, the fan-in and fan-out of the control path will be changed, so the area also will be changed according it

Results Θ=2 Original Optimized

Circuit Vertex Edge C-element Vertex Edge C-element

s27 6 10 4 4 6 2

s298 28 83 55 16 38 22

s344 30 93 63 16 40 24

s349 30 93 63 16 40 24

s386 12 42 30 6 12 6

s420 32 152 120 14 44 28

s510 12 42 30 6 12 6

s526 42 165 123 22 77 55

s1448 12 42 30 6 12 6

Results Θ=3Original Optimized

Circuit Vertex Edge C-element Vertex Edge C-element

s27 6 10 4 4 6 2

s298 28 83 55 12 25 13

s344 30 93 63 12 25 13

s349 30 93 63 12 25 13

s386 12 42 30 4 6 2

s420 32 152 120 12 30 18

s510 12 42 30 4 6 2

s526 42 165 123 14 48 34

s1448 12 42 30 6 12 6

The change of average fan-in and fan-out

Original Optimized

Circuit Average fan-in/out Average fan-in/out(Θ=2) Average fan-in/out(Θ=3)

s27 2.67 3.00 3.00

s298 3.96 4.15 4.42

s344 4.10 4.38 5.42

s349 4.10 4.38 5.42

s386 4.50 4.00 4.50

s420 5.75 4.75 5.17

s510 4.50 4.00 4.50

s526 4.93 5.41 6.43

s1448 4.50 4.00 4.00

Conclusion

• Compatible with synchronous design method

• Can reduce the area overhead of the control path

• Can preserve the performance of the circuit

• Will lose some benefit of asynchronous circuit

Finish

Thanks for your attention