Amit's Seminar Report(Final)40

8/11/2019 Amit's Seminar Report(Final)40

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High-k gate dielectric

Seminar ID: 564

A Technical Seminar Report

submitted in partial fulfillment of

the requirement for the B.Tech.

under Biju Patnaik University of Technology, Rourkela.

Submitted By

AMIT RANJAN Roll No. ECE201110040

AUG - 2014

Under the guidance of

Mr. Chandan Kumar Pandey

APEX INSTITUTE OF TECHNOLOGY & MANAGEMENT

Pahala, Bhubaneswar, Odisha

752101, India


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APEX INSTITUTE OF TECHNOLOGY & MANAGEMENT

Pahala, Bhubaneswar, Odisha 752101, India

CERTIFICATE

This is to certify that the seminar work entitled High-K Gate

Dielectricis a bonafide work being done by Mr. Amit Ranjanbearing

Registration No. 1101314076of ECE branch.

This seminar report is submitted in partial fulfillment for the requirement

of the B.Tech. degree under Biju Patnaik University of Technology,

Rourkela, Odisha.

(Mr. CHANDAN KUMAR PANDEY)

Seminar Guide

(Mrs. T.Mita Kumari) (Prof. R.C. Das)

B .Tech Seminar Coordinator PRINCIPAL


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i

ABSTRACT

The term high-dielectric refers to a material with a high dielectric constant (as

compared tosilicon dioxide). High- dielectrics are used in semiconductor

manufacturing processes where they are usually used to replace asilicon dioxide gate

dielectric or another dielectric layer of a device. The implementation of high- gate

dielectrics is one of several strategies developed to allow further miniaturization of

microelectronic components, colloquially referred to as extendingMoore's Law.
http://en.wikipedia.org/wiki/Silicon_dioxidehttp://en.wikipedia.org/wiki/Silicon_dioxidehttp://en.wikipedia.org/wiki/Moore%27s_Lawhttp://en.wikipedia.org/wiki/Moore%27s_Lawhttp://en.wikipedia.org/wiki/Moore%27s_Lawhttp://en.wikipedia.org/wiki/Silicon_dioxidehttp://en.wikipedia.org/wiki/Silicon_dioxide


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ACKNOWLEDGEMENT

I would like to express my immense sense of gratitude to my guide, Mr. Chandan

Kumar Pandey, for his valuable instructions, guidance and support throughout my

seminar.

I again owe my special thanks to Mrs. T.Mita Kumari, Technical Seminar

Coordinator for giving me an opportunity to do this report.

And finally thanks to Prof. R.C. Das, Principal, APEX Institute Of Technology and

Management for his continued drive for better quality in everything that happens at

APEX Institute Of Technology and Management. This report is a dedicated

contribution towards that greater goal.

(Amit Ranjan)

ECE201110040


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TABLE OF CONTENTS

ABSTRACT ................................................................................................................... i

ACKNOWLEDGEMENT ........................................................................................... ii

List of figures ............................................................................................................... iv

List Of tables ................................................................................................................ v

1. Introduction .............................................................................................................. 1

2.Brief History of the High-k gate dielectric ............................................................. 2

3. Relevance of High-k materials in Microelectronics ..................................... 3

4. Needs For High-K gate Dielectric ........................................................................... 5

First principles ....................................................................................................... 5

Gate capacitance impact on drive current............................................................... 6

5. High-k materials....................................................................................................... 7

6. Materials reqirement for high-k gate dielectrics ............................................... 10

6.1 Thermodynamic stability...........................................................................11

6.2 Kinetic stability..........................................................................................11

6.3 High quality interface................................................................................12

6.4 Amorphous to crystalline transition temperature..........................................12

7. Latest Development in Hf-Based High-k Oxides..................................... 14

7.1 Nitrogen doped Hf-based oxides..............................................................14

7.2 Silicon doped Hf-based oxides.................................................................15

8. Application of high k dielectrics in CMOStechnology andemerging new

technology ................................................................................................................... 16

9. Conclusion .............................................................................................................. 18

References ................................................................................................................... 19


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iv

List of figures

Figure 4.1 Conventional silicon dioxide gate dielectric structure compared toa potential high-k dielectric

structure................. ...........................................................05

Figure6.1 xrd spectra for the Hfo2 and HfoxNy

films.......................................................................................................14


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v

List Of tables

Table 5.1 Leading high-k candidates with their properties ...................9


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1. Introduction

Microelectronics has undergone enormous development in recent years with an ever

increasing performance of integrated circuits. This development has been made

possible by modern CMOS technology, notably the down-scaling of transistor

dimensions that leads to an exponential increase in the number of transistors on a

chip. The downscaling and performance improvement of transistors have so far

followed a trend predicted by Gorden. E. Moore, the Intel cofounder, in 1960s.

However this may become difficult in the very near future due to a number of issues

related to excessive power consumption and heat generation in integrated circuits.

Therefore, the semiconductor industry is looking for alternate performance boosters,

in particular by introducing new materials and new device architecture in place of

traditional, standard silicon CMOS technology.

In order to be well-prepared with options to continue scaling during such a scenario,

nearly a decade of research and development has been conducted by various groups.

The different approaches include, introduction of high - k gate dielectric, low-k

interconnects, replacement of bulk silicon with strained silicon-on-insulator (sSOI),

high mobility channel material like germanium, GaAs, graphene etc. and non planar

CMOS device structures like FinFET. As the scaling has clearly reached fundamental

material limits, especially for gate oxide, further scaling can be realized only by

introducing new materials with higher k values. If the thickness of the standard2

SiO

based gate dielectric drops below the tunneling limit, gate leakage current will

increase tremendously. For an oxide thickness of 1.5 nm at 1.5 V the leakage current

density would be 100A/cm2 which is obviously undesirable for low power

applications . To prevent tunneling currents, physically thicker dielectric layers are

required. As the gate dielectric become physically thicker, transistor requires a

material with high dielectric constant to maintain its electrical characteristics. In 2007

a hafnium based high-k dielectric material was introduced for the first time by Intel.


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2.Brief history of the high-k gate dielectric

To overcome gate leakage problems, incorporation of nitrogen into2

SiO has been

adopted. There are several ways to introduce nitrogen into2

SiO , such as post

deposition annealing in nitrogen ambient and forming a nitride/oxide stack structure.

By incorporating nitrogen into2

SiO , it not only increases the dielectric constant but

also acts as a better barrier against boron penetration. In addition, a nitride/oxide stack

structure maintains the benefits of good interface quality between the oxide and

substrate . Despite the immense development with2

SiO , these oxynitrides still have

low k values and so a relatively thick layer is required to prevent direct tunneling

current. Therefore, alternative materials with a higher k than2

SiO are needed to

achieve the required capacitance without tunneling currents. A lot of oxides have been

proposed, unfortunately due to limitations dictated by low power applications,

scalability, or serious reactions with the Si substrate. The choice of alternative gate

dielectrics has been narrowed to2

HfO ,2

ZrO and their silicates due to their excellent

electrical properties and high thermal stability in contact with Si.

However, another problem associated with Hf-based and Zr-based oxides is low

crystallization temperature. They can easily crystallize during standard CMOS

processes. Hf-based oxides are preferred over Zr-based oxides for its relative higher

crystalline temperature. These crystalline structures can increase the gate leakage

which providing pathways for diffusion of dopants and dielectric breakdown. Manyfocused on the improvement of the crystallization temperature of these oxides, such as

N, Si, Al, Ta and La have been incorporated into these Hf-based high-k oxides.


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3. Relevance of high-k materials inmicroelectronics

The dramatic performance improvements in microelectronics over the past few

decades have been accomplished by severe reduction in the size of memory and logic

devices. The capacitance density (C/A) is directly proportional to k value and

inversely propositional to thickness of the dielectric layer as given by the equation:

oxt

k

A

C0

.........................................................(1)

whereoxt and k are the thickness and relative dielectric constant of

the high-k material respectively.

Scaling demanded drastic decrease of the2

SiO thickness to achieve never-higher

capacitance densities. Fundamental limits of2

SiO as a dielectric material, imposed by

electron tunneling, will be reached as the film thickness approaches ~1 nm. This

thickness is already at a level where severe problems start to occurring .At thickness

the dielectric will not be able to effectively withstand voltages and tunneling current.

Another problem related to the2

SiO scaling is reliability; the requirements for

reliability are even more difficult to meet than the leakage current requirements. The

solution for the aforementioned problems related to2

SiO scaling is to select a gate

dielectric with a higher permittivity than that of2

SiO (k =3.9) which can provide a

lower equivalent oxide thickness at higher physical thickness.

The equivalent oxide thickness (EOT ) of a material is defined as the thickness of the

2SiO layer that would be required to achieve the same capacitance density as the

high-k material in consideration. EOT is thus given by

oxt

kEOT *

9.3

.......................................................(2)


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Numerous high-k materials ranging from32

OAl (k ~ 9) to perovskites (k ~ 102104)

are being actively investigated, in order to identify a long term promising material.

However, finding a suitable high-k material is a major challenge because the selected

material must have a higher resistivity, act as a good barrier layer, be thermally stable,

and form an ideal interface with silicon.2

SiO films can be conveniently formed via

oxidation of the silicon substrate. In contrast, high-k materials must be formed by

deposition. Atomic layer deposition (ALD) has emerged as a very promising

technique for depositing high-k thin films for the microelectronics industry.


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4. Needs for high-k gate dielectric

Silicon dioxide has been used as a gate oxide material for decades. As transistors havedecreased in size, the thickness of the silicon dioxide gate dielectric has steadily

decreased to increase the gate capacitance and thereby drive current, raising device

performance. As the thickness scales below 2nm, leakage currents due totunneling

increase drastically, leading to high power consumption and reduced device

reliability. Replacing the silicon dioxide gate dielectric with a high- material allows

increased gate capacitance without the associated leakage effects.

. First principles

The gate oxide in aMOSFET can be modeled as a parallel plate capacitor. Ignoring

quantum mechanical and depletion effects from theSi substrate and gate,

thecapacitance Cof this parallel platecapacitor is given by

t

Ak

C 0

..........................(3)

fig.4.1 Conventional silicon dioxide gate dielectric structure compared to a

potential high-k dielectric structure[4]

Where

Ais the capacitor area

is therelative dielectric constant of the material (3.9 for silicon dioxide)
http://en.wikipedia.org/wiki/Nanometerhttp://en.wikipedia.org/wiki/Quantum_tunnelinghttp://en.wikipedia.org/wiki/MOSFEThttp://en.wikipedia.org/wiki/Siliconhttp://en.wikipedia.org/wiki/Capacitancehttp://en.wikipedia.org/wiki/Capacitorhttp://en.wikipedia.org/wiki/Dielectric_constanthttp://en.wikipedia.org/wiki/Silicon_dioxidehttp://en.wikipedia.org/wiki/Silicon_dioxidehttp://en.wikipedia.org/wiki/Dielectric_constanthttp://en.wikipedia.org/wiki/File:High-k.svghttp://en.wikipedia.org/wiki/File:High-k.svghttp://en.wikipedia.org/wiki/Capacitorhttp://en.wikipedia.org/wiki/Capacitancehttp://en.wikipedia.org/wiki/Siliconhttp://en.wikipedia.org/wiki/MOSFEThttp://en.wikipedia.org/wiki/Quantum_tunnelinghttp://en.wikipedia.org/wiki/Nanometer


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0

is thepermittivity of free space

tis the thickness of the capacitor oxide insulator

Since leakage limitation constrains further reduction of t, an alternative method

to increase gate capacitance is alter by replacing silicon dioxide with a high -

material. In such a scenario, a thicker gate oxide layer might be used which can

reduce theleakage current flowing through the structure as well as improving

the gate dielectricreliability.

Gate capacitance impact on drive current

The drain currentID for aMOSFET can be written (using the gradual channel

approximation) as

2

2

,

thG

invsatD

VV

CL

WI

.........................................(4)

Where

Wis the width of the transistor channel

Lis the channel length

is the channel carrier mobility (assumed constant here)

inv

C is the capacitance density associated with the gate dielectric when the

underlying channel is in the inverted state

G

V is the voltage applied to the transistor gate

D

V is the voltage applied to the transistor drain

th

V is thethreshold voltage

The termG

V th

V is limited in range due to reliability and room temperature

operation constraints, since a too largeG

V would create an undesirable, high electric

field across the oxide. Furthermore, Vth cannot easily be reduced below about 200

mV, because leakage currents due to increased oxide leakage (that is, assuming high-

dielectrics are not available) andsubthreshold conduction raise stand-by power

consumption to unacceptable levels. Thus, according to this simplified list of factors,
http://en.wikipedia.org/wiki/Vacuum_permittivityhttp://en.wikipedia.org/wiki/Subthreshold_leakagehttp://en.wikipedia.org/wiki/Reliability_engineeringhttp://en.wikipedia.org/wiki/MOSFEThttp://en.wikipedia.org/wiki/Threshold_voltagehttp://en.wikipedia.org/wiki/Subthreshold_conductionhttp://en.wikipedia.org/wiki/Subthreshold_conductionhttp://en.wikipedia.org/wiki/Threshold_voltagehttp://en.wikipedia.org/wiki/MOSFEThttp://en.wikipedia.org/wiki/Reliability_engineeringhttp://en.wikipedia.org/wiki/Subthreshold_leakagehttp://en.wikipedia.org/wiki/Vacuum_permittivity


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an increased ID,sat requires a reduction in the channel length or an increase in the gate

dielectric capacitance.

5. High-k materials


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The choice of a material with higher dielectric constant than silicon dioxide can give

the same equivalent oxide thickness with a higher gate oxide but many of them did

not have all the desired properties. High-k materials under investigation include

32OAl,

32OY,

2CeO,

2HfO,

2ZrO,

32OLa. The dielectric constants of these ALD

grown films vary from 3.9 to 300. Searching for the best high-k candidate is not an

easy task since each of these materials does impose some challenges. Table 5.1 lists

the major high-k candidates and their properties.

Material (ev)Eg

k-value evEc

evEV

Stability

with si

Crystal

structure


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2SiO 9 3.9 3.5 4.4 yes Amorphous

43NSi 5 7.5 2.4 1.8 yes Amorphous

32OAl 8.7 8.5-10.5 2.8 4.9 yes Amorphous

52OTa 4-4.5 20-35 0.3 3.1 no Orthorhombic

2Tio 3-3.5 30-100 1.2 1.2 yes Tetragonal

32OLa 4.3 27 2.3 0.9 yes Hexagonal,

cubic

32OY 5.6 12-20 2.3 2.6 yes Cubic

2HfO 5.7 35 2.5 3.4 yes Cubic,

Tetragoal

2ZrO 5.8 25 1.4 3.3 yes Monoclinic

52OGd 5.4 12-23 3.2 3.9 yes Amorphous

Table 5.1: Leading high-k candidates with their properties[1]


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6. Materials reqirement for high-k gate

dielectrics

There is a set of material and electrical requirements for a viable alternate high-k gate

dielectric material . Major requirements include:

Larger energy band gap with higher barrier height to Si substrate and metal

gate to reduce the leakage current.

Large k value.

Good thermodynamic stability on Si to prevent the formation of a low-k2

SiO

interface.

Good kinetic stability.

High amorphous-to-crystalline transition temperature to maintain a stable

morphology after heat treatment.

Low oxygen diffusion coefficients to control the formation of a thick low-k

interface layer.

Low defect densities in high-k bulk films and at the high-k/Si interface with

negligible C-V hysteresis (< 30 mV).

Low fixed charge density (~1010cm-2eV-1).

Low high-k/Si interface state density (~1010cm-2eV-1).

High enough channel carrier mobility (~90% of SiO2/Si system).

Good reliability and a long life time.


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In addition, the new high-k gate dielectric material must be compatible with current

CMOS fabrication process flow and other materials used in the CMOS integrated

circuits. In the following sections the most important high-k requirements are

discussed in detail.

6.1 Thermodynamic stability

A potential gate oxide insulator must be thermodynamically stable on silicon surface.

Current microprocessor device fabrication process usually take place at high

temperatures (>10000 C). During this process the dielectric must remain in a solid

state. If a thin high-k gate dielectric material is thermodynamically unstable on

Silicon, it tends to react with Si at an elevated temperature and an interface layer will

be formed between the high- k layer and Si substrate. This interface layer usually has

a low k value and acts as a series capacitor with the high-k dielectric layer. This low-k

interface will deteriorate the electrical properties of the final high-k gate stack

structure.

6.2 Kinetic stability

The new high-k material should be compatible with existing process conditions.

Assuming we choose an amorphous oxide material , this requires that the oxide

remains amorphous when annealed up to 1000C for 5 seconds. This is strenuous

condition in that2

SiO is an excellent glass former but most other high-k materials are

not. Aluminium Oxide (32

OAl ) is a reasonably good glass former and is the best.

52OTa is moderately good glass former, but was eliminated because it is reactive. All

other oxides crystallize bellow 1000C. This problem can be overcome by alloying

the desired oxide with a glass former like2

SiO or32

OAl giving either a silicate or

aluminate. This is how the industry now retain the stability against crystallization

close to 1000C .


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6.3 High quality interface

2SiO -Si interface offers the best interface quality (interface trap density Dit~1010eV-

1cm-2) for the Si channel area of the MOSFETs. A comparable interface quality will

be expected between the high-k gate dielectric and Si. However, almost all high-k

materials exhibit one or two orders of magnitude high interface state density and

significant flat band voltage shift (WVFB), mainly due to a high fixed charge density.

The origin of the high interface defect density is still under intensive investigation.

Lucovsky et al. reported that bonding constraints of the high-k materials may play a

significant role in determining high-k/Si interface quality. Experimental resultsshowed that if the average number of bonds per atom is over 3 for a metal oxide, an

over-constrained high-k/Si interface will form and the Dit will increase exponentially.

Similarly, a metal oxide with a low coordination number will form an under-

constrained high-k/Si interface, which will also lead to a high interface state density

and poor device performance. In addition, formation of metal silicide at the interface

will also generate unfavorable bonding conditions to the device characteristics.

Ideally, no metal oxide or silicide should be present at or close to the2

SiO /Si

interface. In addition, the gate oxide/Si substrate interface must have minimum oxide

fixed charges and interface trap charges to minimize carrier scattering at the channel

(to maximize mobility). Amorphous layers are generally preferred for gate oxides to

minimize electrical and mass transport along the grain boundaries and therefore to

minimize the gate leakage current.

6.4 Amorphous-to-crystalline transition

temperature

A polycrystalline gate dielectric layer will suffer a high leakage current because their

grain boundaries may serve as a leaky path. Variation in the grain size and crystal

orientation of the polycrystalline films may also cause a non-uniform dielectric

property within the dielectric films, which will become a reliability concern for

practical application. Although single crystal oxides may theoretically solve the


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problems caused by grain boundaries and provide films with good quality, at present

they can only be grown by molecular beam epitaxy (MBE) deposition method . It will

be a great challenge to incorporate MBE deposition into the traditional CMOS

fabrication process flow due to the inherent low throughput. In contrast, high quality

amorphous high-k gate dielectrics can be easily deposited by commercial ALD

equipment. Amorphous high-k gate dielectric layers will also offer reproducible and

isotropic dielectric properties. Almost all metal oxides of interest tend to crystallize

either during deposition or after heat treatment. For traditional CMOS fabrication

process flow, heat treatment above 1000C will be needed for the source/drain and

poly-Si dopant activation after ion implantation. Therefore, an amorphous-to-

crystalline transition temperature above 1000C will be required. For example,2

HfO

and2

ZrO will crystallize at very low temperature (~500C) . Of all the high-k

candidate materials, only32

OAl can stay amorphous at 10008 temperature. However,

32OAl does not have a sufficient high dielectric constant (k) value, adding a third

element into the material may increase the amorphous-to-crystalline transition

temperature. For example adding a small layer of32

OAl with2

HfO layer will

enhance crystallization temperature of 2HfO .


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7. Latest development in Hf-based high-koxides

Crystallization of pure2

HfO occurs at only about 4004500 C causing grain

boundary leakage current and non-uniformity of the film thickness. As a result,

impurities such as O, B, and P can penetrate the grain boundaries during high

temperature post processing. It causes equivalent oxide thickness (EOT) scaling and

reliability concerns when Hf-based high-k ultrathin gate oxides are integrated into

high temperature CMOS processes.

7.1 Nitrogen doped Hf-based high-k oxides

Nitrogen introduction into2

HfO films has significantly improved the electric

properties as well as crystallinity but nitrogen doping leads to decreased band gap.

Despite the disadvantages, the introduced nitrogen can suppress the growth of

microstructure and interfacial layer. When N is added to2

HfO , it is expected to

distort the equilibrium of the lattice and produce disordered states. Researches have

demonstrated that adding nitrogen results in the reduction of the mobility of Hf and O

atoms as well as increase in the nucleation temperature and consequently the

crystalline temperature. All these indicate that nitrogen acts as a crystallization

inhibitor and causes an increase in the crystallization temperature in Hf-based gate

dielectrics.

fig.6.1 XRD spectra for the2

HfO and HfOxNy films.[1]


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7.2 Silicon doped Hf-based high-k oxides

The interfacial layer between the high-k dielectrics and Si substrate is one of the key

factors determining the performance and reliability of a MOS transistor. Hence, it is

extremely crucial to fabricate a2

SiO /Si like interface. A2

SiO interfacial layer is

often grown between Hf-based oxide and Si by thermal oxidation,2

HfO /2

SiO gate

dielectric stack usually introduces an additional EOT increase due to the low k SiOx

interfacial layer, whereas addition of Si into Hf-based oxide to form Hf silicate will

improve interface quality and foster the formation of amorphous structures. A

negative effect is the reduction in the k value, the k value decreases inversely with

increasing Si concentration in Hf-based oxides. By using nitrogen incorporated

HfSiO films, HfSiON is thermally stable compared to2

HfO due to the Si-N bonds

that are created by the nitridation step, and thus HfSiON has the potential for

implementation in a conventional gate-first process with high temperature activation

annealing.


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8. Application of high-k dielectrics in CMOStechnology and

emerging new technology

High K dielectric for DRAM capacitor

DRAM capacitor must have a minimum capacitance of ~ 30 fF per cell in order to

provide enough sensing margin and data retention time. When devices scale, the area

occupied by the capacitor must scale in order to obtain a small cell size even when

the capacitance stays fixed. For trench capacitor, the capacitor surface area must be

increased by etching deeper trenches. For stacked capacitor, it is difficult to increase

the surface area indefinitely and high K dielectric must be used to obtain smaller cell

sizes. To achieve high capacitance, the equivalent oxide thickness must be 1nm or

lower. Unlike gate dielectric, the DRAM capacitor is very sensitive to leakage. The

data retention time suffers greatly if the capacitor leakage exceeds ~ 1 fA/cell. The

most commonly selected high K dielectrics are52

OTa ,32

OAl , or BST (Ba-Sr-

Titanate) in order to ensure low leakage. These high K dielectrics also contain fixed

charges that manifest into displacement current that degrades the access speed. High

K dielectric capacitors may be constructed using either polysilicon electrodes or metal

electrodes. Polysilicon electrode has the advantage of simpler processing, but the

disadvantage of high resistance which adversely impact the access speed of DRAM.

Metal electrode, on the other hand, has low resistance but may interact strongly withboth high K material and Si. Consequently, expensive noble metal such as Ir and Ru

are used. Metal oxides (high K) are extremely sensitive to plasma and hydrogen

damage and thus need to be either protected or isolated from hydrogen and plasma.

Recently,2

IrO and2

RuO electrodes are adopted because of their stabilizing effects

on high K dielectric. The successful application of high K dielectric will be the key to

future high speed DRAM technology.


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High k ferroelectrics for FeRAM capacitor

Most ferroelectrics have very high permittivity in the order of 500 1000. These

dielectrics contain permanent dipoles that can be oriented by applying an electric

field, and thus are suitable for non-volatile data storage. The memory cell is very

similar to DRAM, consisted of a capacitor and an access MOS transistor. The storage

node is usually in the form of a ferroelectric capacitor, with PZT or SBT as the

dielectric. FeRAM not only is non-volatile, but also consumes little power during

switching because it is a voltage device and not a current device. The datum is stored

in the form of dipole polarization and thus requires no current to charge and discharge

the capacitor. It is also very fast (< 100 ns access time) compared to other non-volatile

memories for the same reason. Consequently, it becomes an ideal memory for

embedded and SoC (System-on-Chip) applications the most important being hand-

held devices such as cellular phone, and contactless smart card which requires both

high speed and low power. High K ferroelectrics for FeRAM, however, face

several daunting challenges. Both PZT and SBT require high temperature (650C

700C) to form ferroelectric phase and even when noble metal electrode (Pt, Ru, Ir) is

used it interacts with the ferroelectric. They also are extremely sensitive to plasma and

hydrogen induced damage. In addition, oxygen vacancy at electrode interface causes

severe fatigue degradation. Recent progress in using2

IrO electrodes has greatly

alleviated the above problems and large array up to 32 Mb is demonstrated . In

addition, epitaxial growth of PZT on3

LaNiO electrode at < 400C further allows the

embedding of FeRAM in SoC using capacitor over interconnect (COI) modular

concept .


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9. Conclusion

Extensive R & D Efforts for High-k Gate Dielectrics Are Needed to Realize

EOT


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References

[1]. M. Houssa, High-k Gate Dielectrics, Institute of Physics Publishing, Bristol, UK

(2004).

[2]. S. M. Sze, Physics of Semiconductor Devices, 2nd ed., John Wiley & Sons, New

York (1981).

[3].J. P. Chang, in High-k Gate Dielectric Deposition Techniques, High Dielectric

Constant Materials, H. R. Huff and D. C. Gilmer, Editors, p. 379, Springer-Verlag,

New York (2005).

[4]. G.D Wilk, R.M Wallace, and J.M Anthony, J. Appl. Phys. 89, 5243 (2001).

[5]. Robertson, J. (2005). Interfaces and defects of high-K oxides on silicon, vol. 49,

pp. 283-293, Solid-State Electronics.

[6]. Huang, A.P; Yang, Z.C; Chu, P.K, Hafnium-based High-k Gate Dielectrics.

[7].T. Hori, Gate Dielectrics and MOS ULSIs: Principles, Technologies,

and Applications, Springer, Berlin, Germany (1997).

[8]. N. A. Chowdhury, P. Srinivasan, D. Misra, R. Choi, and B. H. Lee, Paper

presented at the SEMATECH International Workshop on Electrical Characterization

and Reliability for High-k Devices, Austin, TX, p. 143 (2004).

Amit's Seminar Report(Final)40

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