eBook ISBN:0-306-47509-XPrint ISBN: 0-7923-8393-12002 Kluwer Academic PublishersNew York, Boston, Dordrecht, London, MoscowPrint 1999 Kluwer Academic PublishersAll rights reservedNo part of this eBook may be reproduced or transmitted in any form or by any means, electronic,mechanical, recording, or otherwise, without written consent from the PublisherCreated in the United States of AmericaVisit Kluwer Online at: http://kluweronline.comand Kluwer's eBookstore at: http://ebooks.kluweronline.comDordrechtALGORITHMSFORVLSIPHYSICALDESIGNAUTOMATIONTHIRD EDITIONNaveed A. SherwaniIntelCorporation.KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOWThis Page Intentionally Left BlankALGORITHMSFORVLSIPHYSICALDESIGNAUTOMATIONTHIRDEDITIONTo my parentsAkhterandAkramSherwaniContentsForeword xviiPreface xixAcknowledgements xxvii1 VLSIPhysicalDesignAutomation13791.11.21.31.41.5VLSI Design CycleNew Trends in VLSI Design CyclePhysical Design CycleNew Trends inPhysical DesignCycleDesign Styles1.5.11.5.21.5.31.5.41.5.51.5.6Full-CustomStandardCellGateArraysFieldProgrammableGateArraysSeaofGatesComparison of Different Design Styles1.6 SystemPackagingStyles1.6.1 DiePackagingandAttachmentStyles1.6.1.11.6.1.2DiePackageStylesPackageandDieAttachmentStyles1.6.21.6.31.6.41.6.5PrintedCircuitBoardsMultichip ModulesWaferScaleIntegrationComparison of DifferentPackaging Styles1.71.81.9HistoricalPerspectivesExistingDesignToolsSummary1315171820222525262626272729313132333539404343452 DesignandFabricationof VLSIDevices2.12.2FabricationMaterialsTransistor Fundamentals2.2.12.2.2BasicSemiconductorJunctionTTLTransistorsviii Contents2.2.3 MOSTransistors2.3 Fabricationof VLSICircuits2.3.12.3.22.3.3nMOSFabricationProcessCMOSFabricationProcessDetailsofFabricationProcesses2.42.5Design RulesLayout of BasicDevices2.5.12.5.22.5.3InvertersNAND and NOR GatesMemory Cells2.5.3.12.5.3.2Static Random Access Memory (SRAM)Dynamic Random Access Memory (DRAM)2.62.7SummaryExercises3 FabricationProcessanditsImpactonPhysicalDesign3.13.2Scaling MethodsStatusofFabricationProcess3.2.1 ComparisonofFabricationProcesses3.3 IssuesrelatedtotheFabricationProcess3.3.13.3.23.3.33.3.43.3.53.3.63.3.7ParasiticEffectsInterconnectDelayNoiseandCrosstalkInterconnectSizeandComplexityOtherIssuesinInterconnectPower DissipationYieldandFabricationCosts3.4 FutureofFabricationProcess3.4.13.4.23.4.3SIARoadmapAdvances in LithographyInnovationsinInterconnect3.4.3.13.4.3.23.4.3.33.4.3.4More Layers of MetalLocalInterconnectCopperInterconnectUnlanded Vias3.4.43.4.53.4.6Innovations/IssuesinDevicesAggressiveProjectionsfortheProcessOtherProcessInnovations3.4.6.13.4.6.2SiliconOnInsulatorSiliconGermaniun3.53.63.73.8Solutions for InterconnectIssuesTools for Process DevelopmentSummaryExercises46485153535862626466676971717576777779798081828282838585868787878788888990909091939494Contents ix4 DataStructuresandBasicAlgorithms 974.14.2BasicTerminology 99ComplexityIssuesandNP-hardness4.2.1 Algorithms for NP-hard Problems4.2.1.14.2.1.24.2.1.34.2.1.4ExponentialAlgorithmsSpecialCase AlgorithmsApproximationAlgorithmsHeuristicAlgorithms4.3 Basic Algorithms4.3.1 Graph Algorithms4.3.1.14.3.1.24.3.1.34.3.1.44.3.1.54.3.1.6Graph Search AlgorithmsSpanning Tree AlgorithmsShortestPathAlgorithmsMatching AlgorithmsMin-Cutand Max-Cut AlgorithmsSteiner Tree Algorithms4.3.2 Computational Geometry Algorithms4.3.2.14.3.2.2Line Sweep MethodExtendedLineSweepMethod4.4 BasicDataStructures4.4.14.4.24.4.34.4.44.4.54.4.64.4.74.4.8AtomicOperations forLayout EditorsLinkedListof BlocksBin-BasedMethodNeighbor PointersCornerStitchingMulti-layerOperationsLimitationsof ExistingDataStructuresLayoutSpecificationLanguages4.5 Graph Algorithms for Physical design4.5.1 Classesof GraphsinPhysicalDesign4.5.1.14.5.1.2GraphsRelatedtoaSetof LinesGraphsRelatedtoSetofRectangles4.5.24.5.34.5.4RelationshipBetweenGraphClassesGraphProblems inPhysicalDesignAlgorithms for Interval Graphs4.5.4.14.5.4.2MaximumIndependentSetMaximum Clique and Minimum Coloring4.5.5 Algorithms forPermutationGraphs4.5.5.14.5.5.2MaximumIndependentSetMaximum-IndependentSet4.5.6 Algorithms for Circle Graphs4.5.6.14.5.6.24.5.6.3MaximumIndependentSetMaximum-IndependentSetMaximum Clique4.64.7SummaryExercises100101102102102103104104104106108110110111115115115117117119120122123130131131135135136138138140142142143144144146148148149151151152kkx Contents5 Partitioning 1575.1 ProblemFormulation5.1.1 DesignStyle SpecificPartitioning Problems5.25.3Classification of Partitioning AlgorithmsGroupMigrationAlgorithms5.3.15.3.2Kernighan-LinAlgorithmExtensionsofKernighan-LinAlgorithm5.3.2.15.3.2.25.3.2.35.3.2.4Fiduccia-Mattheyses AlgorithmGoldberg and Burstein AlgorithmComponent ReplicationRatio Cut5.4 SimulatedAnnealingandEvolution5.4.15.4.2Simulated AnnealingSimulatedEvolution5.5 OtherPartitioningAlgorithms5.5.1 Metric Allocation Method5.65.75.8Performance DrivenPartitioningSummaryExercises1631661681691701711731741741761771771791831831851871876 FloorplanningandPinAssignment 1916.1 Floorplanning6.1.1 ProblemFormulation6.1.1.1 Design Style Specific Floorplanning Problems6.1.26.1.36.1.46.1.56.1.66.1.7ClassificationofFloorplanningAlgorithmsConstraintBasedFloorplanningIntegerProgrammingBasedFloorplanningRectangularDualizationHierarchicalTreeBasedMethodsFloorplanningAlgorithmsforMixedBlockandCellDe-signs6.1.86.1.96.1.106.1.11SimulatedEvolution AlgorithmsTiming Driven FloorplanningTheoreticaladvancementsinFloorplanningRecentTrends6.2 Chip planning6.2.1 ProblemFormulation6.3 Pin Assignment6.3.1 ProblemFormulation6.3.1.1 DesignStyleSpecificPinAssignmentProblems6.3.26.3.36.3.4Classification of Pin AssignmentAlgorithmsGeneral PinAssignmentChannel Pin Assignment6.46.56.6IntegratedApproachSummaryExercises193193194194196198200201203203204205206207207207208208209210211214217217Contents xi7 Placement 2197.1 ProblemFormulation7.1.1 DesignStyleSpecificPlacementProblems7.27.3Classificationof PlacementAlgorithmsSimulationBasedPlacementAlgorithms7.3.17.3.27.3.37.3.4SimulatedAnnealingSimulatedEvolutionForceDirectedPlacementSequence-PairTechnique7.3.5 ComparisonofSimulationBasedAlgorithms7.4 PartitioningBasedPlacementAlgorithms7.4.17.4.2Breuers AlgorithmTerminalPropagationAlgorithm7.5 OtherPlacementAlgorithms7.5.17.5.27.5.37.5.4ClusterGrowthQuadraticAssignmentResistiveNetworkOptimizationBranch-and-BoundTechnique7.67.77.87.9PerformanceDrivenPlacementRecentTrendsSummaryExercises2202232252252262292322332332362362362392402402412412422422432442448 GlobalRouting 2478.1 ProblemFormulation8.1.1 DesignStyleSpecificGlobalRoutingProblems2532578.2 Classification of Global RoutingAlgorithms8.3 MazeRoutingAlgorithms8.3.18.3.28.3.38.3.4Lees AlgorithmSoukups AlgorithmHadlocks AlgorithmComparison of MazeRouting Algorithms8.48.58.6Line-ProbeAlgorithmsShortestPathBasedAlgorithmsSteinerTreebasedAlgorithms8.6.18.6.28.6.38.6.4SeparabilityBasedAlgorithmNon-RectilinearSteinerTreeBasedAlgorithmSteinerMin-MaxTreebasedAlgorithmWeightedSteinerTreebasedAlgorithm8.7 IntegerProgrammingBasedApproach8.7.1 Hierarchical Approach8.88.98.10Performance Driven RoutingSummaryExercises260261261263264267269272273274277279281282282286287288xii Contents9 Detailed Routing9.1 Problem Formulation2912932932952973023023033043063063113123163163183203203213213233253293303343383403453453463463483493523533543553583583623623639.1.19.1.29.1.39.1.49.1.5RoutingConsiderationsRouting ModelsChannelRoutingProblemsSwitchbox RoutingProblemsDesignStyle Specific Detailed Routing Problems9.29.3Classification of Routing AlgorithmsSingle-Layer RoutingAlgorithms9.3.1 General River RoutingProblem9.3.1.1 GeneralRiverRoutingAlgorithm9.3.2 Single Row Routing Problem9.3.2.19.3.2.29.3.2.39.3.2.4Originof SingleRowRoutingAGraphTheoreticApproachAlgorithmforStreetCongestionMinimizationAlgorithm for Minimizing Doglegs9.4 Two-Layer ChannelRouting Algorithms9.4.19.4.2Classification of Two-Layer AlgorithmsLEAbasedAlgorithms9.4.2.19.4.2.29.4.2.3Basic Left-Edge AlgorithmDoglegRouterSymbolicChannelRouter:YACR29.4.3 ConstraintGraphbasedRoutingAlgorithms9.4.3.19.4.3.2NetMergeChannelRouterGlitter:AGridless Channel Router9.4.49.4.59.4.6GreedyChannelRouterHierarchicalChannelRouterComparisonof Two-LayerChannelRouters9.5 Three-Layer Channel RoutingAlgorithms9.5.19.5.29.5.39.5.4ClassificationofThree-LayerAlgorithmsExtendedNetMergeChannelRouterHVH Routing from HV SolutionHybrid HVH-VHV Router9.69.7Multi-LayerChannelRouting AlgorithmsSwitchboxRoutingAlgorithms9.7.19.7.29.7.39.7.49.7.5Classificationof switchbox routing algorithmsGreedyRouterRip-upandRe-routeBasedRouterComputationalGeometryBasedRouterComparisonofSwitchboxRouters9.89.9SummaryExercisesContents xiii10 Over-the-CellRoutingandViaMinimization 36937037137337337738939639839840040140340740840941041041141741841942242342642742742842943043243343643943944044444410.1 Over-the-cellRouting10.1.110.1.2CellModelsTwo-Layer Over-the-Cell Routers10.1.2.110.1.2.210.1.2.3BasicOTCRoutingAlgorithmPlanar Over-the-Cell RoutingOver-the-Cell RoutingUsingVacantTerminals10.1.310.1.410.1.5Three-LayerOver-the-cellRoutingMultilayerOTCRoutingPerformanceDrivenOver-the-cell Routing10.2 ViaMinimization10.2.1 ConstrainedViaMinimizationProblem10.2.1.1 Graph Representation of Two-Layer CVMProb-lem10.2.2 UnconstrainedVia Minimization10.2.2.110.2.2.210.2.2.3OptimalAlgorithmforCrossing-ChannelTVMProblemApproximation Result for Generalk-TVMProb-lemRoutingBasedonTopologicalSolution10.310.4SummaryExercises11 ClockandPowerRouting11.1 ClockRouting11.1.111.1.2Clocking SchemesDesignConsiderationsfortheClockingSystem11.1.2.1 DelayCalculationforClockTrees11.1.3 ProblemFormulation11.1.3.1 DesignStyleSpecificProblems11.1.4 ClockRoutingAlgorithms11.1.4.111.1.4.211.1.4.311.1.4.411.1.4.511.1.4.6H-tree BasedAlgorithmThe MMMAlgorithmGeometricMatchingbasedAlgorithmWeightedCenterAlgorithmExact ZeroSkewAlgorithmDME Algorithm11.1.511.1.6SkewandDelayReductionbyPinAssignmentMultipleClockRouting11.211.311.4PowerandGroundRoutingSummaryExercisesxiv Contents12 Compaction12.1 ProblemFormulation44945045045145245345446046346346346446446746847047347347347447447547647647948048548548949049249349449649750150250550751051251251351412.1.1 DesignStyle SpecificCompactionProblem12.212.3Classificationof CompactionAlgorithmsOne-Dimensional Compaction12.3.1 Constraint-GraphBasedCompaction12.3.1.112.3.1.212.3.1.312.3.1.4ConstraintGraphGenerationCriticalPathAnalysisWire JoggingWireLengthMinimization12.3.2 VirtualGridBasedCompaction12.3.2.112.3.2.212.3.2.3BasicVirtual Grid AlgorithmSplitGridCompactionMostRecentLayerAlgorithm12.412.5CompactionTwo-DimensionalCompaction12.5.1 Simulated AnnealingbasedAlgorithm12.6 HierarchicalCompaction12.6.1 Constraint-GraphBasedHierarchicalCompaction12.7 Recent trendsincompaction12.7.112.7.2Performance-drivencompactionCompactiontechniquesforyieldenhancement12.812.9SummaryExercises13 PhysicalDesignAutomationof FPGAs13.113.213.313.4FPGATechnologiesPhysicalDesignCycle forFPGAsPartitioningRouting13.4.113.4.2RoutingAlgorithm for theNon-SegmentedModelRouting AlgorithmsfortheSegmentedModel13.4.2.113.4.2.2Basic AlgorithmRoutingAlgorithmforStaggered Model13.513.6SummaryExercises14 PhysicalDesignAutomationof MCMs14.114.214.314.4MCMTechnologiesMCM Physical DesignCyclePartitioningPlacement14.4.114.4.2ChipArrayBasedApproachFull CustomApproach14.5 Routing14.5.1 Classification of MCMRouting Algorithms1~ - DimensionalContents xv14.5.214.5.3Maze Routing 514515515517517517519519521521MultipleStageRouting14.5.3.114.5.3.214.5.3.3PinRedistributionProblemLayer AssignmentDetailedRouting14.5.414.5.514.5.6TopologicalRoutingIntegratedPinDistributionandRoutingRouting in Programmable MultichipModules14.614.7SummaryExercisesBibliography 525AuthorIndex 563SubjectIndex 567This Page Intentionally Left BlankForewordSincetheinventionofintegratedcircuitsthirtyyearsago,manufacturingofelectronicsystemshastakenrapidstridesinimprovementinspeed,size,andcost.Fortodaysintegratedcircuitchips,switchingtimeisontheorderofnanoseconds,minimumfeaturesizeisontheorderof sub-microns,transistorcountisontheorderofmillions,andcostisontheorderofafewdollars.Infact,itwasestimatedthattheperformance/costratioof integratedcircuitchipshasbeenincreasingattherateofonethousand-foldeverytenyears,yielding a total offor the last three decades.A combination of high productperformanceandlowper-unitcostleadstotheverypervasiveintroductionofintegratedcircuitchipstomanyaspectsof modernengineeringandscientificendeavorsincludingcomputations,telecommunications,aeronautics,genetics,bioengineering,manufacturing,factoryautomation,andsoon.Itisclearthattheintegratedcircuitchipwillplaytheroleofakeybuildingblockintheinformationsociety of the twenty-first century.Themanufactureofintegratedcircuitchipsissimilartothemanufactureofotherhighlysophisticatedengineeringproductsinmanyways.Thethreemajor steps aredesigning the product, fabricating the product,andtesting thefabricatedproduct.Inthedesignstep,alargenumberof componentsaretobedesignedorselected,specificationsonhowthesecomponentsshouldbeas-sembledaretobemade,andverificationstepsaretobecarriedouttoassurethecorrectnessof thedesign.Inthemanufacturingstep,agreatdealof man-power,anda large collection of expensive equipment,together withpainstakingcareareneededtoassembletheproduct accordingtothedesignspecification.Finally,thefabricatedproductmustbetestedtocheckitsphysicalfunction-ality.Asinallengineering problems,thereareconflictingrequirementsinallthesesteps.Inthedesignstep,wewanttoobtainanoptimalproductdesign,andyetwealsowantthedesigncycletobeshort.Inthefabricationstep,wewanttheproductyield tobehigh,andyetwealso needtobeabletoproducealargevolumeof theproductandgetthemtomarketintime.Inthetestingstep,wewanttheproducttobetestedthoroughlyandyetwealsowanttobeable todosoquickly.The titleof thisbook reveals how theissue of enormousdesigncomplexityistobehandledsothathighquality designscanbeobtainedinareason-ableamountof designtime:Weusemuscles (automation)andweusebrainxviii(algorithms).ProfessorSherwanihaswrittenanexcellentbooktointroducestudentsincomputerscienceandelectricalengineeringaswellasCADengi-neerstothesubjectofphysicaldesignofVLSIcircuits.Physicaldesignisakeystepinthedesignprocess.Researchanddevelopmenteffortsinthelasttwentyyearshaveledustosomeverygoodunderstandingonmanyoftheimportantproblemsinphysicaldesign.ProfessorSherwanisbookprovidesatimely,up-to-dateintegration of theresultsinthe field andwillbemostusefulbothasagraduateleveltextbookandasareferenceforprofessionalsinthefield.Allaspectsofthephysicaldesignprocessarecoveredinameticulousandcomprehensivemanner.Thetreatmentisenlighteningandenticing.Fur-thermore,topicsrelatedtosomeof thelatesttechnology developmentssuchasFieldProgrammableGateArrays(FPGA)andMulti-ChipModules(MCM)arealsoincluded.Astrongemphasisisplacedonthealgorithmicaspectofthedesignprocess.Algorithmsarepresentedinanintuitivemannerwithouttheobscurityof unnecessary formalism.Boththeoreticalandpracticalaspectsofalgorithmicdesignarestressed.Neithertheeleganceof optimalalgorithmsnor theusefulnessof heuristicalgorithmsare overlooked.Froma pedagogicalpointof view,the chapters on electronic devicesand on data structures and ba-sicalgorithmsprovideusefulbackground material forstudentsfromcomputerscience, computerengineering,andelectricalengineering.Themanyexercisesincludedinthebookarealsomosthelpfulteachingaids.Thisisabookonphysicaldesignalgorithms.Yet,thisisabookthatgoesbeyondphysicaldesignalgorithms.Thereareotherimportantdesignstepsof whichourunderstandingisstillquitelimited.Furthermore,develop-ment of new materials, devices, and technologies will unquestionably create newproblemsandnewavenuesof researchanddevelopmentinthedesignprocess.Analgorithmicoutlookondesignproblemandthealgorithmictechniquesforsolvingcomplexdesignproblems,whichareaderlearnsthroughtheexamplesdrawn from physical design inthis book,will transcend theconfine of physicaldesignandwillundoubtedlypreparethereaderformanyoftheactivitiesinthe field of computer-aided design of VLSI circuits.I expect to hear from manystudentsandCADprofessionalsintheyearstocomethattheyhavelearnedagreatdealaboutphysical design,computer-aided design,andscientificresearchfromProfessor Sherwanis book.Ialsoexpecttohearfrommanyof themthatProfessor Sherwanis book isasourceof informationaswellasa source of in-spiration.Urbana-Champaign,September1992C.L.LiuPrefaceFromitshumblebeginningintheearly1950stothemanufactureofcircuitswithmillions of components today,VLSI design hasbrought the power of themainframecomputer tothelaptop.Of course,thistremendousgrowthinthearea of VLSI design is made possible by the development of sophisticated designtools and software.To deal with the complexity of millions of components andtoachievea turnaroundtimeof acoupleof months,VLSIdesigntoolsmustnotonlybecomputationallyfastbutalsoperformclosetooptimal.The futuregrowth of VLSI systemsdependscriticallyontheresearchanddevelopment of Physical Design (PD) Automation tools. In the last two decades,theresearchinphysicaldesignautomationhasbeenvery intense,andliterallythousands of research articles covering all phases of physical design automationhave been published.The development of VLSI physical design automation alsodependsonavailabilityof trainedmanpower.Wehavetwotypesof studentsstudyingVLSIphysicaldesign:studentspreparingforaresearchcareerandstudentspreparingforacareerinindustry.Bothtypesofstudentsneedtobuilda solidbackground.However,currently welack coursesandtextbookswhich givestudentsacomprehensivebackground.Itiscommontofindstu-dentsdoingresearchinplacement,butareunawareof thelatestdevelopmentsincompaction.ThosestudentsseekingcareersinindustrywillfindthattheVLSI physical design industry is very fast paced.They are expected to be con-versantwithexistingtoolsandalgorithmsforallthestagesof thedesigncycleof a VLSI chip.In industry, it is usual to find CAD engineers who work on oneaspectof physicaldesignandlackknowledgeof otheraspects.Forexample,aCADengineerworkinginthedevelopmentofdetailedroutersmaynotbeknowledgeableaboutpartitioningalgorithms.Thisisagainduetothelackof comprehensive textbookswhichcover background material inallaspectsofVLSI physical design.ProvidingacomprehensivebackgroundinonetextbookinVLSIphysicaldesign isindeeddifficult.This is due to the fact that physical design automa-tionrequiresamixofbackgrounds.Someelectricalengineeringandasolidundergraduatecomputersciencebackgroundisnecessarytograspthefunda-mentals.Inaddition,somebackgroundingraphtheoryandcombinatoricsisalsoneeded,sincemanyofthealgorithmsaregraphtheoreticoruseothercombinatorial optimization techniques.Thismix of backgroundshas perhapsxxrestrictedthedevelopmentof coursesand textbooks inthisveryarea.Thisbookisanattempttoprovideacomprehensivebackgroundintheprinciples and algorithms of VLSIphysical design.The goal of this book is toserveasabasisforthedevelopmentof introductorylevelgraduatecoursesinVLSI physical design automation.Itis hoped thatthe book provides self con-tainedmaterialforteachingandlearningalgorithmsofphysicaldesign.Allalgorithms which are considered basic have been included.The algorithms arepresentedinanintuitivemanner,sothatthereadercanconcentrateonthebasicideaof thealgorithms.Yet,atthesametime,enoughdetailisprovidedsothatreaderscanactuallyimplementthealgorithmsgiveninthetextanduse them.Thisbookgrewoutof agraduatelevelclassinVLSIphysicaldesignau-tomationatWesternMichiganUniversity.Initiallywrittenasasetofclassnotes,thebooktook formasitwasrefinedovera periodof threeyears.Overview of the BookThisbookcoversallaspectsofphysicaldesign.Thefirstthreechaptersprovidethebackgroundmaterial,whilethefocusofeachchapteroftherestof thebookisoneachphaseof thephysicaldesigncycle.Inaddition,newertopicslikephysicaldesignautomationofFPGAsandMCMshavealsobeenincluded.InChapter1,we give an overview of the VLSI physical design automationfield.Topics include the VLSI design cycle,physical designcycle,design stylesandpackagingstyles.Thechapterconcludeswithabrief historicalreviewofthe field.Chapter 2 discusses the fabrication process for VLSI devices.It is importanttounderstandthefabricationtechnologyinordertocorrectlyformulatetheproblems.Inaddition,itisimportantforonetounderstand,whatisdoableand what is not!Chapter 2 presents fundamentals of MOS and TTL transistors.It then describes simple NANDand NOR gates in nMOS and CMOS.Chapter3presentsthestatusoffabricationprocess,aswellas,processinnovations on the horizons and studies its impact on physical design.We alsodiscussseveralotherfactorssuchasdesignrules,yield,delay,andfabricationcosts involved in the VLSI process.BasicmaterialondatastructuresandalgorithmsinvolvedinthephysicaldesignispresentedinChapter4.Severaldifferentdatastructuresforlayouthave been discussed.Graphs which are used to model several different problemsin VLSI designare defined and basic algorithms for these graphs are presented.Chapter5dealswithpartitioningalgorithms.AnattempthasbeenmadetoexplainallthepossiblefactorsthatmustbeconsideredinpartitioningtheVLSIcircuits.Groupmigration,simulated annealing and simulated evolutionalgorithmshavebeenpresentedindetail.Theissueofperformancedrivenpartitioningisalsodiscussed.InChapter6,we discuss basic algorithms for floorplanning and pinassign-ment.Several different techniques for placement such as, simulated annealing,xxisimulated evolution,and force-directed are discussed inChapter7.Chapter8dealswithglobalrouting.Itcoverssimple routingalgorithms,such as maze routing, and more advanced integer programming based methods.Italso discussesSteinertree algorithms forrouting of multiterminalnets.Chapter9isthelongestchapterinthebookandrepresentsthedepthofknowledgethathasbeengainedinthedetailedroutingareainthelastdecade.Algorithms are classified according to the number of layers allowed forrouting.In single layer routing,we discuss general river routing and the singlerowrouting problem.Allmajortwo-layer channelandswitchboxroutersarealsopresented.Thechapteralsodiscussesthree-layerandmultilayerroutingalgorithms.Chapter10 discusses two ways of improving layouts after detailedrouting,namely,viaminimizationandover-the-cellrouting.Basicalgorithmsforviaminimization are presented.Over-the-cell routing is a relatively new techniquefor reducing routing areas.We presentthe two latestalgorithms for over-the-cell routing.Theproblemsofroutingclockandpower/groundnetsarediscussedinChapter11.Thesetopicsplayakeyroleindeterminingthelayoutofhighperformance systems.Circuit compaction is discussed inChapter12.One di-mensional compaction,as wellas two dimensional compaction algorithmsarepresented.FieldProgrammableGateArrays(FPGAs)arerapidlygaining groundinmanyapplications,suchassystemprototyping.InChapter13,wediscussphysical design automation problems and algorithms for FPGAs.In particular,wediscussthepartitioningandroutingproblemsinFPGAs.BothoftheseproblemsaresignificantlydifferentfromproblemsinVLSI.Manyaspectsofphysicaldesignof FPGAsremainatopicof currentresearch.Multi-ChipModules(MCMs)arereplacingconventionalprintedcircuitboardsinmanyapplications.MCMspromisehighperformancesystemsata lower cost.In Chapter14, we explore the physical design issues in MCMs.Inparticular,therouting problemof MCMsisa truethreedimensionalproblem.MCMsarecurrentlya topicof intenseresearch.Attheendof eachchapter,alistof exercisesisprovided,whichrangeincomplexity fromsimple toresearch level.Unmarked problemsandalgorithmsarethesimplest.Theexercisesmarked with () are harderandalgorithmsintheseexercisesmay takea significanteffortto implement.The exercisesandalgorithmsmarkedwith()arethehardest.Infact,someof theseproblemsareresearchproblems.Bibliographic notes can be found at the end of each chapter.In these notes,we give pointers to the readers for advanced topics.An extensive bibliographyispresentedattheendof thetext.Thisbibliographyiscomplete,tothebestof our knowledge,up to theSeptember of 1998.Anattempthasbeen made toincludeallpaperswhichareappropriateforthetargetedreadersof thistext.Thereadersmayalso find theauthorandthesubjectindexattheback of thetext.xxiiOverview of the Second EditionIn1992,whenthisbook was originally published,the largestmicroprocessorhadonemilliontransistors andfabricationprocesshadthreemetallayers.Wehavenowmovedintoasixmetallayerprocessand15milliontransistormicro-processorsarealreadyinadvancedstagesofdesign.Thedesignsaremovingtowardsa500to700Mhzfrequencygoal.Thischallenging frequencygoal,aswellas,theadditionalmetallayershavesignificantlyalteredtheVLSIfield.Manyissuessuchasthreedimensionalrouting,Over-the-Cellrouting,earlyfloorplanninghavenowtakenacentralplaceinthemicroprocessorphysicaldesignflow.ThischangesintheVLSIdesignpromptedustoreflecttheseinthebook.Thatgavebirthtotheideaof thesecondedition.ThebasicpurposeofthesecondeditionistointroduceamorerealisticpicturetothereaderexposingtheconcernsfacingtheVLSIindustrywhilemaintainingthetheoretical flavor of thebook.Newmaterialhasbeenaddedtoallthechapters.Severalnew sectionshavebeenaddedtomanychapters.Few chapters have been completelyrewritten.New figures have been added tosupplementthenewmaterialandclarifytheexistingmaterial.Insummary,Ihavemadeanattempttocapturethephysicaldesignflowusedintheindustryandpresentitinthesecondaddition.Ihopethatreaderswill find thatinformation bothusefulandinteresting.Overview of the Third EditionIn1995,whenwepreparedthe2ndeditionofthisbook,asixmetallayerprocessand15milliontransistormicroprocessorswereinadvancedstagesofdesign.In1998,sixmetalprocessand20milliontransistordesignsareinpro-duction.Several manufacturers have moved to 0.18 micron processand copperinterconnect.Onecompanyhasannouncedplansfor0.10micronprocessandplans to integrate 200 to 400 million transistors on a chip.Operating frequencyhasmoved from266Mhz(in1995)to650MhzandseveralGhzexperimentalchipshavebeendemonstrated.Interconnectdelayhasfarexceededdevicede-layandhasbecomeadominantthemeinphysicaldesign.Processinnovationssuch ascopper,lowkdielectrics,multiple threshold devices,local interconnectareonceagainpoisedtochangephysicaldesignonceagain.Thebasicpurposeofthethirdeditionistoinvestigatethenewchallengespresented by interconnect andprocess innovations.In particular,we wanted toidentifykeyproblemsandresearch areasthatphysicaldesigncommunityneedstoinvestinordertomeetthechallenges.Wetookataskof presentingthoseideas while maintaining the flavor of the book.Asa result,we have added twonewchapters and new material has beenadded to mostof the chapters.Anewchapter on process innovation and its impact on physical design has been added.Anotherfocusof thebookhasbeentopromoteuseof Internetasaresource,so wherever possible URLshas been provided for further investigation.Chapters1and2havebeenupdated.Chapter3isanewchapteronthefabricationprocessanditsimpact.Chapter4(algorithms)andChapter5xxiii(partitioning)havebeeneditedforclarity.ChapteronFloorplanning,Place-mentandPinAssignmenthasbeensplitintoChapter6(Floorplanning)andChapter7(Placement)to bringsharper focusto floorplanning. NewsequencepairalgorithmshavebeenaddedtoChapter7(Placement)Chapter8and9havebeeneditedforclarityandreferenceshavebeenupdatedasappropriate.Newsectionshave beenaddedtoChapter10,Chapter11andChapter12.InChapter10,wehaveaddedmaterialrelatedtoperformancedrivenrouting.InChapter11,DMEalgorithmhasbeenadded.InChapter12,wehaveaddednew compaction algorithms. Chapters 13 (FPGAs) and 14 (MCMs) have beenupdated.Wehavemadeanattempttoupdatethebibliographyquiteexten-sively and many new items have beenadded.Insummary, I have made anattemptto capture the impactof interconnectandprocessinnovationsonphysicaldesignflow.Ihaveattemptedtobalancematerialonnewinnovationswiththeclassicalcontentofthe2ndedition.Ihope thatreaders will find thatinformationbothusefulandinteresting.To the TeacherThisbookhasbeenwrittenforintroductorylevelgraduatestudents.Itpresents concepts and algorithms in an intuitive manner.Each chapter contains3to 4 algorithms thathave beendiscussed indetail.Thishasbeendone soasto assist students in implementing the algorithms.Other algorithms have beenpresentedinasomewhatshorterformat.Referencestoadvanced algorithmshave been presented at the end of each chapter.Efforthas beenmade to makethebookselfcontained.Thisbookhasbeendeveloped fora one-semester ora two-semestercourseinVLSIphysicaldesignautomation.Inaone-semestercourse,itisrecom-mendedthatchapters8,9,11,and12beomitted.Ahalf-semester algorithmdevelopmentprojectishighlyrecommended.Implementationof algorithmsisanimportanttoolinmakingstudentsunderstandalgorithms.Inphysicalde-sign,the majority of thealgorithms are heuristic in nature and testing of thesealgorithms on benchmarks should be stressed.In addition, the development ofpracticalalgorithmsmustbestressed,thatis,studentsmustbeveryawareofthe complexity of the algorithms.An optimalalgorithm may be imprac-tical for an input of size10 million.Several () marked problems at the end ofeachchaptermayserveasmini-projects.In a two-semester class, it is recommended that all the chapters be included.Readingstate-of-artpapers mustbeanintegralpartof thisclass.Inparticular,studentsmaybeassignedpapersfromproceedingsofDACandICCADorfromIEEETransactionsonCAD.Papers fromTransactionstypicallyrequirea littlemoremathematicalmaturitythanthepapersinDACandICCAD.Animportantpartofthisclassshouldbeatwo-semesterproject,whichmaybethedevelopmentof anewalgorithmforsomeprobleminphysicaldesign.Atypicalfirstpartof theprojectmayinvolvemodifyinganexistingalgorithmforaspecialapplication.Some()problemsmayserveasprojects.Inboththecourses,agoodbackgroundinhandlayoutiscritical.ItisIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIxxivexpectedthatstudentswillhaveaccesstoa layouteditor,suchasMAGICorLEDIT.Itisveryimportantthatstudentsactually layouta fewsmallcircuits.Forexamplesseeexercisesattheendof Chapter2.For faculty members, a teaching aid package, consisting of a set of 400 over-heads(foils)isavailablefromtheauthor.Thesearequitehelpfulinteachingtheclass,asall theimportantpointshave beensummarizedonsectionbysec-tionbasis.Inordertoobtainthesefoils,pleasesendanemail(oramail)totheauthor,attheaddressbelow.To the StudentFirstandforemost,Ihopethatyouwillenjoyreadingthisbook.Everyefforthasbeenmadetomakethisbookeasytoread.Thealgorithms havebeenexplainedinanintuitivemanner.Theidea istogetyoutodevelopnewalgorithmsattheendofthesemester.Thebookhasbeenbalancedtogiveapracticalaswellasatheoreticalbackground.Inthatsense,youwillfindituseful,if youarethinkingabouta careerinindustryorif youarethinkingaboutphysical designasapossiblegraduateresearch topic.Whatdoyouneedtostartreadingthisbook?Somematurityingeneralalgorithmtechniquesanddatastructuresisassumed.Someelectricalengi-neering background and mathematics background will be helpful,although notnecessary.Thebookisself-containedtoagreatextentanddoesnotneedanysupportingtextorreferencetext.If youareconsideringacareerinthisfield,Ihaveoneimportantpieceofadvise for you.Research inthis field moves very fast.Asa result,no textbookcanreplacestate-of-the-artpapers.Itisrecommendedthatyoureadpaperstokeepyouabreastof latestdevelopments.AlistofconferenceproceedingsandjournalsappearsinthebibliographicnotesofChapter1.Ialsorecom-mend attending DAC and ICCAD conferences every year and a membership inACM/SIGDA,IEEE/DATCandIEEE/TC-VLSI.To the CAD ProfessionalThisbookprovidesadetaileddescriptionofallaspectsofphysicaldesignandIhopeyouhavepicked upthisbook toreview your basicsof physicalde-sign.While itconcentrates on basic algorithms,pointers are given to advancedalgorithmsaswell.Thetexthasbeenwrittenwithabalanceoftheoryandpractice in mind.You will also find the extensive bibliography useful for findingadvancedmaterialonatopic.ErrorsandOmissionsNobookisfreeoferrorsandomissions.Despiteourbestattempt,thistextmaycontainsomeerrors.If youfindanyerrorsorhaveanyconstructivesuggestions,Iwouldappreciatereceivingyourcommentsandsuggestions.Inparticular,newexerciseswouldcertainlybevery helpful.Youcanmailyourxxvcommentsto:NaveedSherwaniIntelCorporation,MailStop:JFT-1042111N.E.25thAvenueHillsboro,OR 97124-5961oremailthemto sherwaan@ichips.intel.com.Aconcentratedefforthasbeenmadetoincludeallpertinentreferencestopapers and books thatwe could find. If you find omissions in thebook,pleasefeelfreetoremindme.ThisbookwastypesetinLatex.Figuresweremadeusing xfig andin-serteddirectlyintothetextas.ps files usingtransfig.ThebibliographywasgeneratedusingBibtexandtheindexwasgeneratedwithaprogramwrittenbySiddharthBhingarde.Portland,March,1998NaveedA.SherwaniThis Page Intentionally Left BlankAcknowledgmentsNobookisaproductofoneperson.Thesameistrueforthisbook.FirstImustthankallmembersofthenitegroupwhoworkedtirelesslyfordaysandnights(mostlynights)forthefinalsixmonths.FirstIwould liketothankSiddharthBhingarde,SurendraBurman,MoazzemHossain,ChandarKamalanathan, WasimKhan,Arun Shanbhag, Timothy Strunk andQiong Yu.Thanksarealsotoduetonitegroupmemberswhohavegraduated.Inpar-ticularRoshanGidwani,JahangirHashmi,NancyHolmes,andBoWu,whohelpedinallstagesofthisproject.Specialthanksareduetotheyoungestmemberofnitegroup,TimothyStrunk,whomade(almost)allthefiguresinthetextandbroughtenthusiasmtotheteam.ThanksarealsoduetoAnandPanyam,KonduruNageshandAizazManzar forhelping inthe final stagesofthisproject.ManystudentsinmyclassCS520(IntroductiontoVLSIdesignautomation)sufferedthroughearlierversionof thisbook,andIwouldliketothankthemfortheirconstructivesuggestions.Several colleagues and friends contributed significantly by reviewing severalchaptersandusingpartsof thebookintheircourses.Inthisregard,IwouldliketothankJeffBanker,AjayGupta,MarkKerstetter,SartajSahni,andJasonCong.IwouldalsoliketoespeciallythankDineshMehtaandSi-QingZheng.IwishtoexpressmysincerethankstoMalgorzataMarek-Sadowska,whomadeverycriticalremarksandcontributionstotheimprovementinthequalityof thetext.Thanks are due to two special people, who have contributed very generouslyin my career and helped in many ways.I would like to thank Vishwani AgrawalandC.L.Liufor theirconstantencouragementandsoundwordsof advise.Iwouldliketothankseveraldifferentorganizationswhohavecontributeddirectlytothisproject.First,IwouldliketothankKenWan,andtherestof theCTSgroup atAdvancedMicro Devices for helping with many technicaldetails.IwouldalsoliketothankACMSIGDAforsupportingourresearchduring the last four years.Thanks are also due to Western Michigan University,andinparticularDonaldNelsonandDouglasFerraro,who,despiteallcosts,madethenecessaryfacilitiesavailabletocomplete thisbook.TheNationalScienceFoundationdeservesthanksforsupportingtheVLSIlaboratoryandourresearchatWesternMichiganUniversity.IwouldalsoliketothankRezaRashidiandthestaff of FRClaboratory fortheirhelpinprintingthetextandxxviiicoverdesign.I would also like to thank our system manager Patty Labelle, who cheerfullyaccepted our occasional abuse of thesystem and keptall the machines upwhenweneededthem.Imustalsothankourdepartmentsecretaries Phyllis WolfandSueMoorian for being very helpfulduring allstages of this project.ImustthankmycopyeditorFrankStrunk,whoverycarefullyreadthemanuscriptintheshorttimewegavehim.ThanksarealsoduetoCarlHar-ris,editoratKluwerAcademicPublishersforbeingunderstandingandgoingbeyondhiscall of duty to helpoutwithmy requests.Finally,IwishtothankmyparentsandmyfamilyforsupportingmethroughoutmylifeandforbeingtherewhenIneededthem.TheysufferedasIneglectedmanysocial responsibilitiestocomplete thisbook.Kalamazoo, September,1992NaveedA.SherwanixxixAcknowledgments for the Second EditionThesecondeditionprojectwouldnothavebeenpossiblewithoutthehelpofSiddharthBhingarde,AmanSureka,RameshwarDonakantiandAnandPa-nyam.Inparticular,Siddharthworkedwithme formany manynightsonthisproject.Iamverygratefultotheseindividualsfortheirhelp.SeveralofmycolleaguesatIntel helpedasreviewersofthechapters.Inthis regard,I would like to thank Marc Rose,John Hansen,Dave Ackley,MikeFarabee,andNirajBindal.Several friendsandfamilymembershelpedbybeingcopyeditors.SabahatNaveed,ShaziaAsifandAkramSherwanihelpedbyeditingmanyrevisions.Internetplayedakeyrole,asmanyoftheserevisionsweredoneinPakistanandthenemailedtome.I would like to thank IntelCorporation for helping mewith this project.Inparticular,IwouldliketothankAtiqBajwaformakingthetimeavailableformetocompletetheproject.Portland,March,1995NaveedA.SherwanixxxAcknowledgments for the Third EditionThethirdeditionwouldnothavebeenpossible withoutthehelpofFaranRafiq,SrinivasaDanda,SiddharthBhingarde,NirajBindal,PrashantSaxena,PeichenPanandAnandPanyam.Iamverygratefultotheseindividualsfortheirhelp.Inparticular,IamindebtedtoFaranRafiq,whoworkedtirelesswithmeandthisprojectwouldnothave beenpossiblewithouthisdedicationandhardwork.I would like to thank IntelCorporation for helping me with the third edition.Inparticular,IwouldliketothankManpreetKhairafortheResearchandDevelopmentenvironment,whichhashelpedmature many ideas.ImustthankmycopyeditorTawniSchlieski,whoverycarefullyreadthenewchapters and turned themaround ina very short time.I am very thankfultoCarlHarris,editoratKluwerAcademicPublishersforencouragingmetowritethethirdedition.Finally,I amvery thankful to my wife Sabahat and mydaughter Aysel fortheirencouragementandsupport.Portland,September,1998NaveedA.SherwaniChapter1VLSIPhysicalDesignAutomationTheinformationrevolutionhastransformedourlives.Ithaschangedourperspective of work,lifeathome and provided new tools for entertainment.Theinternethasemergedasamediumtodistributeinformation,communication,eventplanning,andconductingE-commerce.Therevolutionisbasedoncom-putingtechnologyandcommunicationtechnology,bothof whicharedrivenbyarevolutioninIntegratedCircuit(IC)technology.ICsareusedincomputersformicroprocessor,memory,andinterfacechips.ICsarealsousedincomputernetworking,switchingsystems,communicationsystems,cars,airplanes,evenmicrowaveovens.ICsarenowevenusedintoys,hearingaidsandimplantsforhumanbody.MEMstechnologypromisestodevelopmechanicaldevicesonICstherebyenablingintegrationofmechanicalandelectronicdevicesonaminiaturescale.Manysensors,suchasaccelerationsensorsforautoairbags,alongwithconversioncircuitryarebuiltonachip.Thisrevolutionarydevel-opmentandwidespreaduseofICshasbeenoneofthegreatestachievementsof humankind.IC technologyhas evolved in the1960s from the integration of a few transis-tors(referredtoasSmallScaleIntegration(SSI))otheintegrationofmillionsoftransistorsinVeryLargeScaleIntegration(VLSI)chipscurrentlyinuse.EarlyICsweresimpleandonlyhadacoupleof gatesoraflip-flop.SomeICsweresimplyasingletransistor,alongwitharesistornetwork,performingalogicfunction.InaperiodoffourdecadestherehavebeenfourgenerationsofICswiththenumberof transistorsonasinglechipgrowingfromafewtoover20million.Itisclearthatinthenextdecade,wewillbeabletobuildchipswithbillionsof transistorsrunningatseveralGhz.WewillalsobeabletobuildMEMchipswithmillionsof electricalandmechanicaldevices.Suchchips will enable a new era of devices which will make such exotic applications,suchastele-presence,augumentedrealityandimplantableandwearablecom-puters,possible.Costeffectiveworldwidepoint-to-pointcommunicationwillbecommonandavailabletoall.2 Chapter1.VLSIPhysicalDesignAutomationThisrapidgrowthinintegrationtechnologyhasbeen(andcontinuestobe)madepossiblebytheautomationofvariousstepsinvolvedinthedesignandfabrication of VLSIchips.Integrated circuitsconsistof a number of electroniccomponents,builtbylayering severaldifferentmaterialsinawell-definedfash-ionona siliconbasecalledawafer.Thedesignerof anICtransformsacircuitdescriptionintoageometricdescription,calledthelayout.Alayoutconsistsofasetofplanargeometricshapesinseverallayers.Thelayoutischeckedtoensurethatitmeetsallthedesignrequirements.Theresultisasetofde-signfilesthatdescribesthelayout.Anopticalpatterngeneratorisusedtoconvertthedesignfiles intopatterngeneratorfiles.Thesefilesareusedtoproducepatternscalledmasks.Duringfabrication,thesemasksareusedtopatternasiliconwaferusingasequenceof photo-lithographicsteps.Thecom-ponentformationrequiresveryexactingdetailsaboutgeometricpatternsandtheseparationbetweenthem.Theprocessofconvertingthespecificationofanelectricalcircuitintoalayoutiscalledthephysicaldesignprocess.Duetothetighttolerancerequirementsandtheextremelysmallsizeof theindividualcomponents,physicaldesignisanextremelytediousanderrorproneprocess.Currently,thesmallestgeometricfeatureofacomponentcanbeassmallas0.25 micron(one micron, written asis equalto).Forthesakeofcomparison,ahumanhairisindiameter.Itisexpectedthatthefeaturesizecanbereduced below0.1micronwithin five years.Thissmallfea-ture size allows fabrication of as many as 200 million transistors on a 25 mm25mmchip.Duetothelargenumberof components,andtheexactingdetailsrequiredbythefabricationprocess,physicaldesignisnotpracticalwithoutthehelpof computers.Asa result,almostallphasesof physicaldesign extensivelyuseComputerAidedDesign(CAD)tools,andmanyphaseshavealreadybeenpartiallyorfullyautomated.VLSIPhysicalDesignAutomationisessentiallytheresearch,developmentandproductizationofalgorithmsanddatastructuresrelatedtothephysicaldesignprocess.Theobjectiveistoinvestigateoptimalarrangementsofdevicesonaplane(orinthreedimensions)andefficientinterconnectionschemesbe-tween thesedevices to obtainthedesired functionality andperformance.Sincespaceonawaferisveryexpensiverealestate,algorithmsmustusethespacevery efficientlytolower costsandimprove yield.Inaddition,thearrangementofdevicesplaysakeyroleindeterminingtheperformanceofachip.Algo-rithmsforphysicaldesignmustalsoensurethatthelayoutgeneratedabidesbyalltherulesrequiredbythefabricationprocess.Fabricationrulesestablishthetolerance limitsof the fabrication process.Finally,algorithms mustbeeffi-cientandshouldbeabletohandleverylargedesigns.Efficient algorithmsnotonlyleadtofastturn-aroundtime,butalsopermitdesignerstomakeiterativeimprovementstothelayouts.TheVLSIphysicaldesignprocessmanipulatesverysimplegeometricobjects,suchaspolygonsandlines.Asaresult,physi-caldesignalgorithmstendtobeveryintuitiveinnature,andhavesignificantoverlapwithgraphalgorithmsandcombinatorialoptimizationalgorithms.Inviewof thisobservation,manyconsiderphysical designautomationthestudyof graphtheoreticandcombinatorialalgorithmsformanipulationof geometricI'm75I'm1.1. VLSI Design Cycle 3objectsintwoandthreedimensions.However,apuregeometricpointof viewignorestheelectrical(bothdigitalandanalog)aspectofthephysicaldesignproblem.InaVLSIcircuit,polygonsandlineshaveinter-related electricalproperties,whichexhibitaverycomplexbehavioranddependonahostofvariables.Therefore,itisnecessarytokeeptheelectricalaspectsofthege-ometricobjectsinperspectivewhiledevelopingalgorithmsforVLSIphysicaldesignautomation.Withtheintroductionof VeryDeepSub-Micron(VDSM),whichprovidesverysmallfeaturesandallows dramaticincreasesintheclockfrequency, the effect of electrical parameters on physical design will play a moredominantroleinthedesignanddevelopmentof newalgorithms.Inthischapter,wepresentanoverviewofthefundamentalconceptsofVLSIphysicaldesignautomation.Section1.1discussesthedesigncycleofaVLSI circuit.New trends in the VLSI design cycle are discussed inSection1.2.InSection1.3,differentstepsofthephysicaldesigncyclearediscussed.Newtrends in the physical design cycle are discussed in Section1.4.Different designstylesarediscussedinSection1.5andSection1.6presentsdifferentpackagingstyles.Section1.7presentsabriefhistoryofphysicaldesignautomationandSection1.8listssomeexistingdesigntools.1.1VLSIDesignCycleTheVLSIdesigncyclestartswithaformalspecificationofaVLSIchip,followsaseriesofsteps,andeventuallyproducesapackagedchip.AtypicaldesigncyclemayberepresentedbytheflowchartshowninFigure1.1.Ouremphasisisonthephysicaldesignstepof theVLSIdesigncycle.However,togainaglobalperspective,webrieflyoutlineallthestepsoftheVLSIdesigncycle.1.2.System Specification:The first step of any design process is to lay downthespecificationsof thesystem.Systemspecificationisahighlevelrep-resentationofthesystem.Thefactorstobeconsideredinthisprocessinclude:performance,functionality,andphysicaldimensions(size of thedie(chip)).Thefabricationtechnologyanddesigntechniquesarealsoconsidered.Thespecificationof asystemisacompromisebetweenmar-ketrequirements,technologyandeconomicalviability.Theendresultsare specifications for the size,speed,power,and functionality of the VLSIsystem.ArchitecturalDesign:Thebasicarchitectureofthesystemisdesignedinthisstep.Thisincludes,suchdecisionsasRISC(ReducedInstructionSetComputer)versusCISC(ComplexInstructionSetComputer),num-berofALUs,FloatingPointunits,numberandstructureofpipelines,andsizeofcachesamongothers.TheoutcomeofarchitecturaldesignisaMicro-ArchitecturalSpecification(MAS).WhileMASisatextual(Englishlike) description,architectscanaccuratelypredicttheperfor-mance,poweranddiesizeofthedesignbasedonsuchadescription.4 Chapter1.VLSIPhysicalDesignAutomationSuchestimatesarebasedonthescalingof existingdesignorcomponentsof existingdesigns.Sincemanydesigns(especiallymicroprocessors)arebasedonmodificationsorextensionstoexisting designs,suchamethodcanprovidefairlyaccurateearlyestimates.Theseearlyestimatesarecriticaltodeterminetheviabilityof a productforamarketsegment.Forexample,formobilecomputing(suchaslaptopcomputer),lowpowerconsumptionisacriticalfactor,duetolimitedbatterylife.Earlyesti-matesbasedonarchitecturecanbeusedtodetermineifthedesignislikelytomeetitspowerspec.3.4.5.BehavioralorFunctionalDesign:Inthisstep,mainfunctionalunitsofthesystemareidentified.Thisalsoidentifiestheinterconnectre-quirementsbetweentheunits.Thearea,power,andotherparametersofeachunitareestimated.Thebehavioralaspectsofthesystemareconsideredwithoutimplementationspecificinformation.Forexample,itmayspecifythata multiplicationisrequired,butexactlyinwhichmodesuchmultiplicationmaybeexecutedisnotspecified.Wemayuseava-rietyofmultiplicationhardwaredependingonthespeedandwordsizerequirements.Thekeyideaistospecifybehavior,intermsofinput,outputandtimingof eachunit,withoutspecifyingitsinternalstructure.Theoutcomeoffunctionaldesignisusuallyatimingdiagramorotherrelationshipsbetweenunits.Thisinformationleadstoimprovementoftheoveralldesignprocessandreductionof thecomplexityof subsequentphases.Functionalorbehavioraldesignprovidesquickemulationof thesystemandallows fastdebugging of thefullsystem.Behavioral designislargelyamanualstepwithlittleornoautomationhelpavailable.LogicDesign:Inthisstepthecontrolflow,wordwidths,registerallo-cation,arithmeticoperations,andlogicoperationsofthedesign thatrepresentthefunctionaldesignarederivedandtested.ThisdescriptioniscalledRegisterTransferLevel(RTL)description.RTLisexpressedinaHardwareDescriptionLanguage(HDL),suchasVHDLorVerilog.Thisdescriptioncanbeusedinsimulationandverification.Thisde-scriptionconsistsofBooleanexpressionsandtiminginformation.TheBooleanexpressionsareminimizedtoachievethesmallestlogicdesignwhichconformstothefunctionaldesign.Thislogicdesignof thesystemissimulatedandtestedtoverifyitscorrectness.Insomespecialcases,logic design can be automated using highlevel synthesis tools.These toolsproduceaRTLdescriptionfromabehavioraldescriptionof thedesign.CircuitDesign:Thepurposeofcircuitdesignistodevelopacircuitrep-resentationbasedonthelogicdesign.TheBooleanexpressionsarecon-verted intoa circuitrepresentation by taking intoconsideration thespeedand power requirements of the original design.CircuitSimulation isusedto verify the correctness and timing of each component.The circuit designisusuallyexpressedinadetailedcircuitdiagram.Thisdiagramshowsthecircuitelements(cells,macros,gates,transistors)andinterconnec-1.1.VLSIDesignCycle 5System SpecificationArchitecturalDesignx (ABOCD)+{A+D)+(A(B+C)Y-(A(B+C)+AC+D+A(8C+DI ~ IPackagingand TestingFabricationPhysical DesignFunctional DesignFigure1.1: A simple VLSI designcycle.6 Chapter1.VLSIPhysicalDesignAutomationtionbetweentheseelements.Thisrepresentationisalsocalledanetlist.Toolsusedtomanuallyentersuchdescriptionarecalledschematiccap-turetools.Inmanycases,anetlistcanbecreatedautomaticallyfromlogic(RTL)descriptionbyusinglogicsynthesis tools.6.7.PhysicalDesign:Inthisstepthecircuitrepresentation(ornetlist)isconvertedintoageometricrepresentation.Asstatedearlier,thisgeo-metricrepresentationof acircuitiscalledalayout.Layoutiscreatedbyconvertingeachlogiccomponent(cells,macros,gates,transistors)intoageometricrepresentation(specificshapesinmultiplelayers),whichper-formtheintendedlogicfunctionof thecorrespondingcomponent.Con-nectionsbetweendifferentcomponentsarealsoexpressedasgeometricpatternstypicallylinesinmultiplelayers.Theexactdetailsof thelayoutalso depend ondesign rules,which are guidelinesbased on the limitationsof thefabricationprocessandtheelectricalpropertiesofthefabricationmaterials.Physicaldesignisaverycomplexprocessandthereforeitisusuallybroken downinto varioussub-steps.Variousverificationandval-idationchecksareperformedonthelayoutduringphysicaldesign.Inmanycases,physicaldesigncanbecompletelyorpartiallyautomatedandlayoutcanbegenerateddirectlyfromnetlistbyLayoutSynthesistools.Mostof thelayoutof ahighperformancedesign (suchasamicro-processor)maybedone using manual design,while many low to mediumperformancedesignordesignswhichneedfastertime-to-marketmaybedoneautomatically.Layoutsynthesistools,whilefast,dohaveanareaandperformancepenalty,whichlimittheirusetosomedesigns.Man-uallayout,whileslowandmanuallyintensive,doeshavebetterareaandperformanceascomparedtosynthesizedlayout.Howeverthisadvan-tagemaydissipateaslargerandlargerdesignsmayunderminehumancapabilitytocomprehendandobtaingloballyoptimizedsolutions.Fabrication:Afterlayoutandverification,thedesignisreadyforfabri-cation.Sincelayoutdataistypicallysenttofabricationonatape,theeventofreleaseof dataiscalledTapeOut.Layoutdataisconverted(orfractured)into photo-lithographic masks, one for each layer.Masks iden-tifyspacesonthewafer,wherecertainmaterialsneedtobedeposited,diffusedorevenremoved.Silicon crystalsaregrownandslicedtopro-duce wafers.Extremely small dimensions of VLSI devices require that thewafersbepolished to near perfection.The fabricationprocessconsistsofseveralstepsinvolvingdeposition,anddiffusionofvariousmaterialsonthewafer.Duringeachsteponemaskisused.Severaldozenmasksmaybeusedtocompletethefabricationprocess.Alargewaferis20cm(8inch)indiameterandcanbeusedtoproduce hundredsof chips,depend-ing of thesize of thechip.Beforethechipismassproduced,a prototypeismadeandtested.Industryisrapidlymovingtowards a30cm(12inch)waferallowing evenmorechipsperwaferleadingtolowercostperchip.1.2.NewTrendsinVLSI DesignCycle 78. Packaging,TestingandDebugging:Finally,thewaferisfabricatedand dicedintoindividual chips ina fabrication facility.Eachchipisthenpackagedandtestedtoensurethatitmeetsallthedesignspecificationsandthatitfunctionsproperly.ChipsusedinPrintedCircuitBoards(PCBs)arepackagedinDualIn-linePackage(DIP),PinGridArray(PGA),BallGridArray(BGA),andQuadFlatPackage(QFP).ChipsusedinMulti-ChipModules(MCM)arenotpackaged,sinceMCMsusebareornakedchips.ItisimportanttonotethatdesignofacomplexVLSIchipisacomplexhumanpowermanagementprojectaswell.Severalhundredengineersmaywork on a large design project for two to three years.This includesarchitecturedesigners,circuitdesigners,physicaldesignspecialists,anddesignautomationengineers.Asaresult,designisusuallypartitionedalongfunctionality,anddifferentunitsaredesignedbydifferentteams.Atanygiventime,eachunitmaynotbeatthesamelevelof design.Whileoneunitmaybeinlogicdesignphase,anotherunitmaybecompleting itsphysicaldesignphase.Thisimposesaseriousproblemforchipleveldesigntools,sincethesetoolsmustworkwithpartialdataatthechiplevel.TheVLSIdesigncycleinvolvesiterations,bothwithinastepandbetweendifferentsteps.Theentiredesigncyclemaybeviewedastransformationsofrepresentationsinvarioussteps.Ineachstep,anewrepresentationofthesystemiscreatedandanalyzed.Therepresentationisiterativelyimprovedtomeetsystemspecifications.Forexample,alayoutisiterativelyimprovedsothatitmeetsthetimingspecificationsof thesystem.Anotherexamplemaybedetectionof designruleviolationsduring designverification.If suchviolationsaredetected,thephysicaldesignstepneedstoberepeatedtocorrecttheerror.Theobjectivesof VLSICADtoolsaretominimizethetimeforeachiterationandthetotalnumberofiterations,thusreducingtime-to-market.1.2NewTrendsinVLSIDesignCycleThedesign flow describedintheprevioussectionisconceptuallysimpleandillustratesthebasicideasof theVLSIdesigncycle.However,therearemanynewtrendsintheindustry,whichseektosignificantlyalterthisflow.Themajorcontributingfactorsare:1. Increasinginterconnectdelay:Asthefabricationprocessimproves,the interconnectis notscaling at thesame rate as the devices.Devicesarebecomingsmallerandfaster,andinterconnecthasnotkeptupwiththatpace.As a result,almost 60%of a pathdelay may be due to interconnect.Onesolutiontointerconnectdelayandsignalintegrityissueisinsertionof repeatersinlongwires.Infact,repeatersarenownecessaryformostchiplevel nets.Thistechniquesrequiresadvancedplanning since area forrepeatersmustbeallocated upfront.8 Chapter1.VLSIPhysicalDesignAutomation2.3.4.5.Increasinginterconnectarea:Ithas been estimated thata micropro-cessordiehasonly60%-70%of itsarea covered withactivedevices.Therestoftheareaisneededtoaccommodatetheinterconnect.Thisareaalsoleadstoperformancedegradation.InearlyICs,a fewhundredtran-sistorswereinterconnectedusingonelayerof metal.Asthenumberoftransistorsgrew,theinterconnectareaincreased.However,withthein-troductionof asecondmetallayer,theinterconnectarea decreased.Thishasbeenthetrendbetweendesigncomplexityandthenumberofmetallayers.Incurrentdesigns,withapproximately tenmilliontransistorsandfourtosixlayersofmetal,onefindsabout40%ofthechipsrealestatededicatedtoitsinterconnect.Whilemoremetallayershelpinreducingthediesize,itshouldbenotedthatmoremetallayers(afteracertainnumberof layers)donotnecessarilymeanlessinterconnectarea.Thisisduetothespacetakenupbytheviasonthelowerlayers.Increasingnumberofmetallayers:Tomeettheincreasingneedsofinterconnect,thenumberofmetallayersavailableforinterconnectisincreasing.Currently,athreelayerprocessiscommonlyusedformostdesigns,whilefourlayerandfivelayerprocessesareusedmainlyformicroprocessors.As a result,a three dimensional view of the interconnectisnecessary.Increasingplanningrequirements:Themostimportantimplicationof increasing interconnectdelay,area of thediededicated to interconnect,and a large number of metal layers is that the relative location of devices isveryimportant.Physicaldesignconsiderationshavetoenterintodesignatamuchearlierphase.Infact,functionaldesignshouldincludechipplanning.Thisincludestwonewkeysteps;blockplanningandsignalplanning.Block planning assigns shapesand locations to main functionalblocks.Signal planningreferstoassignmentofthethreedimensionalregionsthroughwhichmajorbussesandsignalswillberouted.Timingshouldbeestimatedtoverifythevalidityofthechipplan.Thisplanshouldbeusedtocreatetimingconstraintsforlaterstagesof design.Synthesis:Thetimerequiredtodesignanyblockcanbereducediflayoutcanbedirectlygeneratedorsynthesized fromahigherlevelde-scription.Thisnotonlyreducesdesigntime,italsoeliminateshumanerrors.Thebiggestdisadvantageistheareausedbysynthesizedblocks.Suchblockstakelargerareasthanhandcraftedblocks.Dependinguponthe level of design on which synthesis is introduced, we have two types ofsynthesis.LogicSynthesis:ThisprocessconvertsanHDLdescriptionofablockintoschematics(circuitdescription)andthenproducesitslayout.Logicsynthesisisanestablishedtechnologyforblocksinachipdesign,and for complete Application Specific Integrated Circuits(ASICs).Logicsynthesis is not applicable for large regular blocks, such as RAMs,ROMs,PLAsandDatapaths,andcomplete microprocessor chips for two reasons;1.3.Physical DesignCycle 9speedand area.Logic synthesis tools are too slow and tooarea inefficienttodealwithsuchblocks.HighLevelSynthesis:Thisprocessconvertsa functionalormicro-architecturaldescriptionintoalayoutorRTLdescription.Inhighlevelsynthesis,inputisadescriptionwhichcapturesonlythebehavioralas-pectsofthesystem.Thesynthesistoolsformaspectrum.Thesyn-thesissystemdescribedabovecanbecalled generalsynthesis.Amorerestrictedtypesynthesizessomeconstrainedarchitectures.Forexam-ple,DigitalSignal Processing(DSP)architectures have beensuccessfullysynthesized.ThesesynthesissystemsaresometimescalledSiliconCom-pilers.Anevenmorerestrictedtypeof synthesistoolsarecalledModuleGenerators,whichworkonsmallersizeproblems.Thebasicideaistosimplifythesynthesistask,eitherbyrestrictingthearchitectureorre-strictingthesizeoftheproblem.Siliconcompilerssometimesusetheoutputofmodulegenerators.Highlevelsynthesisisanareaofcurrentresearch andisnotusedinactualchipdevelopment[GDWL92].Insum-mary, high level synthesis systems provide very good implementations forspecializedclassesofsystems,andtheywillcontinuetogainacceptanceastheybecomemoregeneralized.In order toaccommodate the factorsdiscussed above,the VLSIdesign cycleis changing.In Figure 1.2, we show a VLSI design flow which is closer to reality.Duetoincreasinginterconnectdelay,thephysicaldesignstartsveryearlyinthedesigncycletogetimprovedestimatesof theperformanceof thechip,Theearlyfloorphysicaldesignactivitiesleadtoincreasinglyimprovedchiplayoutaseachblockisrefined.Thisalsoallowsbetterutilizationofthechipareatodistributetheinterconnectinthreedimensions.Thisdistributionhelpsinreducing thediesize,improving yieldand reducing cost.Essentially,theVLSIdesign cycle produces increasingly better defineddescriptions of the given chip.Eachdescriptionisverifiedand,if itfailstomeetthespecification,thestepisrepeated.1.3 Physical Design CycleTheinputtothephysical designcycleisacircuitdiagramandtheoutputisthelayoutofthecircuit.Thisisaccomplishedinseveralstagessuchaspartitioning,floorplanning,placement,routing,andcompaction.Thedifferentstagesof physicaldesigncycleareshowninFigure1.3.Each of thesestageswillbe discussed in detail in various chapters;however,to give a global perspective,wepresentabrief descriptionof allthestageshere.1. Partitioning:Achipmaycontainseveralmilliontransistors.Duetothelimitationsofmemoryspaceandcomputationpoweravailableitmaynotbepossibletolayouttheentirechip(orgenericallyspeakinganylargecircuit)inthesamestep.Therefore,thechip(circuit)isnormallypartitionedintosub-chips(sub-circuits).Thesesub-partitionsarecalled10 Chapter1.VLSIPhysicalDesignAutomationEarly Physical DesignLayoutVerificationFigure 1.2: VLSIdesigncycle.1.3.Physical DesignCycle 11blocks.Theactualpartitioningprocessconsidersmanyfactorssuchasthesizeof theblocks,numberof blocks,andnumberof interconnectionsbetweentheblocks.Theoutputofpartitioningisasetofblocksandtheinterconnectionsrequiredbetweenblocks.Figure1.3(a)showsthattheinputcircuithasbeenpartitionedinto threeblocks.Inlargecircuits,thepartitioningprocessishierarchicalandatthetopmostlevelachipmayhave5to25blocks.Eachblockisthenpartitionedrecursivelyintosmaller blocks.2. FloorplanningandPlacement:Thisstepisconcernedwithselectinggoodlayoutalternativesforeachblock,aswellastheentirechip.Theareaofeachblockcanbeestimatedafterpartitioningandisbasedap-proximately on the number and the type of componentsin thatblock.Inaddition,interconnect area required within theblock mustbeconsidered.Theactualrectangularshapeoftheblock,whichisdeterminedbytheaspectratio may,however,bevaried withina pre-specifiedrange.Manyblocksmayhave moregeneral rectilinearshapes. Floorplanningisa crit-icalstep,asitsetsupthegroundwork fora goodlayout.However,itiscomputationallyquitehard.Veryoftenthetaskof floorplanning isdoneby a design engineer,rather than a CADtool.Thisis due to the fact thatahumanisbetterat visualizing theentirefloorplanandtakingintoac-counttheinformationflow.Manualfloorplanningissometimesnecessaryasthemajorcomponentsof anICneedtobeplacedinaccordancewiththesignalflowofthechip.Inaddition,certaincomponentsareoftenrequiredtobelocatedatspecificpositionsonthechip.Duringplacement,theblocksareexactlypositionedonthechip.Thegoalof placementistofindaminimumareaarrangementfortheblocksthatallowscompletionofinterconnectionsbetweentheblocks,whilemeetingtheperformanceconstraints.Thatis,wewanttoavoida place-mentwhichisroutablebutdoesnotallowcertainnetstomeettheirtiminggoals.Placementistypicallydoneintwophases.Inthefirstphaseaninitialplacementiscreated.Inthesecondphase,theinitialplacementisevaluatedanditerativeimprovementsaremadeuntilthelayouthasminimumareaorbestperformanceandconformstodesignspecifications.Figure1.3(b)showsthatthreeblockshavebeenplaced.Itshouldbenotedthatsomespacebetweentheblocksisintentionallyleftemptytoallow interconnectionsbetweenblocks.Thequalityof theplacementwillnotbeevidentuntiltheroutingphasehasbeencompleted.Placementmayleadtoanunroutabledesign,i.e.,routingmaynotbepossibleinthespaceprovided.Inthatcase,anotheriterationofplacementisnecessary.Tolimitthenumberofiterationsof theplacementalgorithm,anestimateof therequiredroutingspaceisusedduringtheplacementphase.Goodroutingandcircuitperformancedependheavilyonagoodplacementalgorithm.Thisisduetothefactthatoncethepositionofeachblockisfixed,verylittlecanbedoneto12 Chapter1.VLSIPhysicalDesignAutomationimprove theroutingandtheoverallcircuitperformance.Lateplacementchangesleadtoincreaseddiesizeandlowerqualitydesigns.3.4.5.Routing:Theobjectiveoftheroutingphaseistocompletetheintercon-nections between blocks according to the specified netlist.First, the spacenotoccupiedbytheblocks(calledtheroutingspace)ispartitionedintorectangularregionscalledchannelsandswitchboxes.Thisincludesthespacebetweentheblocksaswellthe as thespaceontopoftheblocks.The goal of a router is tocomplete all circuitconnections using the short-estpossiblewirelengthandusingonlythechannelandswitchboxes.Thisis usuallydone intwo phases,referred to astheGlobal Routing andDetailedRoutingphases.Inglobalrouting,connectionsarecompletedbetweentheproperblocksof thecircuitdisregarding theexactgeometricdetails of each wire and pin.For each wire, the global router finds a list ofchannelsandswitchboxeswhicharetobeusedasapassagewayforthatwire.Inotherwords,global routing specifiesthedifferentregions intherouting spacethroughwhichawireshouldberouted.Globalroutingisfollowedbydetailedroutingwhichcompletespoint-to-pointconnectionsbetween pins on the blocks.Global routing is converted into exact routingbyspecifyinggeometricinformationsuchasthelocationandspacingofwiresandtheirlayerassignments.Detailed routing includeschannelrout-ingandswitchboxrouting,andisdoneforeachchannelandswitchbox.Routing is a very well studied problem,and several hundred articles havebeenpublishedaboutall itsaspects.Sincealmostall problemsinroutingarecomputationallyhard,theresearchers have focusedonheuristicalgo-rithms.Asaresult,experimentalevaluationhasbecomeanintegralpartofallalgorithmsandseveralbenchmarkshavebeenstandardized.Duetotheverynatureof theroutingalgorithms,completeroutingof alltheconnectionscannot beguaranteed in many cases.Asa result,a techniquecalledrip-upandre-routeisused,whichbasicallyremovestroublesomeconnectionsandreroutes themina differentorder.Therouting phaseofFigure1.3(c)showsthatalltheinterconnectionsbetweenthethreeblockshavebeenrouted.Compaction:Compactionissimplythetaskofcompressingthelayoutinalldirectionssuchthatthetotalareaisreduced.Bymakingthechipsmaller,wirelengthsarereduced,whichinturnreducesthesignaldelaybetweencomponentsofthecircuit.Atthesametime,asmallerareamayimplymorechipscanbeproducedonawafer,whichinturnreducesthecostof manufacturing.However,theexpenseofcomputingtimemandatesthatextensivecompactionisusedonlyforlargevolumeapplications,suchasmicroprocessors.Compactionmustensurethatnorulesregarding thedesignandfabrication processare violatedduring theprocess.Figure1.3(d)showsthecompactedlayout.ExtractionandVerification:DesignRuleChecking(DRC)isaprocesswhichverifiesthatallgeometricpatternsmeetthedesignrulesimposed1.4.NewTrendsinPhysical DesignCycle 13bythefabricationprocess.Forexample,onetypicaldesignruleisthewireseparationrule.Thatis,thefabricationprocessrequiresaspecificseparation(inmicrons)betweentwoadjacentwires.DRCmustchecksuchseparationformillionsof wiresonthechip.Theremaybeseveraldozendesignrules,someofthemarequitecomplicatedtocheck.Aftercheckingthelayoutfordesignruleviolationsandremovingthedesignruleviolations,thefunctionalityof thelayoutisverifiedbyCircuitEx-traction.Thisisareverseengineering process,andgeneratesthecircuitrepresentationfromthelayout.Theextracteddescriptioniscomparedwith the circuit description to verify its correctness.This process is calledLayoutVersusSchematics(LVS)verification.GeometricinformationisextractedtocomputeResistanceandCapacitance.Thisallowsaccuratecalculation of the timing of each component,including interconnect.ThisprocessiscalledPerformanceVerification.Theextractedinformationisalsousedtocheckthereliabilityaspectsofthelayout.ThisprocessiscalledReliabilityVerificationanditensuresthatlayoutwillnotfailduetoelectro-migration,self-heatandothereffects[Bak90].Physical design, like VLSI design, is iterative in nature and many steps, suchasglobalroutingandchannelrouting,arerepeatedseveraltimestoobtainabetterlayout.Inaddition,thequalityofresultsobtainedinastepdependsonthequalityofthesolutionobtainedinearliersteps.Forexample,apoorquality placementcannot be cured by high quality routing.As a result,earlierstepshavemoreinfluenceontheoverallqualityof thesolution.Inthissense,partitioning,floorplanning,andplacementproblemsplayamoreimportantroleindeterminingtheareaandchipperformance,ascomparedtoroutingandcompaction.Sinceplacementmayproduceanunroutablelayout,thechipmightneedtobere-placedorre-partitionedbeforeanotherroutingisattempted.Ingeneral,thewholedesigncyclemay berepeatedseveral timestoaccomplish the design objectives.The complexity of each step varies,dependingonthedesignconstraintsaswellasthedesignstyleused.Eachstepofthedesigncyclewillbediscussedingreaterdetailinalaterchapter.1.4NewTrendsinPhysicalDesignCycleAsfabricationtechnologyimprovesandprocessentersthedeepsub-micronrange,itisclearthatinterconnectdelayisnotscalingatthesamerateasthegatedelay.Therefore,interconnectdelayisamoresignificantpartofoveralldelay.Asaresult,inhighperformancechips,interconnectdelaymustbeconsidered fromvery early design stages.In order to reduce interconnectdelayseveralmethodscanbeemployed.1. Chiplevelsignalplanning:Atthechiplevel,routingof majorsignalsandbusesmustbeplannedfromearlydesignstages,so thatinterconnectdistancescanbeminimized.Inaddition,theseglobalsignalsmustberoutedinthetopmetallayers,whichhavelowdelayperunitlength.14 Chapter1.VLSIPhysicalDesignAutomation(a)(b)F100rplanning&Placement(c)(d)(e)Figure1.3: Physicaldesigncycle.1.5.DesignStyles 152. OTCrouting:Over-the-Cell(OTC)routingisatermusedtodescriberoutingoverblocksandactiveareas.Thisisadeparturefromconven-tionalchannelandswitchboxroutingapproach.Actually,chiplevelsig-nalplanningisOTCroutingontheentirechip.TheOTCapproachcanalsobeusedwithina blocktoreducearea andimprove performance.TheOTCrouting approach essentiallymakesrouting a three dimensionalproblem.AnothereffectoftheOTCroutingapproachisthatthepinsarenotbroughttotheblockboundariesforconnectionstootherblocks.Instead,pinsarebroughttothetopoftheblockasasea-of-pins.Thisconcept,technicallycalled theArbitraryTerminalModel(ATM),willbediscussedina later chapter.Theconventionaldecompositionof physicaldesignintopartitioning,place-mentandroutingphasesisconceptuallysimple.However,itisincreasinglyclearthateachphaseisinterdependentonotherphases,andanintegratedapproachtopartitioning,placement,androutingisrequired.Figure1.4showsthephysical designcyclewithemphasisontiming.Thefigureshowsthattimingisestimatedafterfloorplaningandplacement,andthesestepsareiteratedifsomeconnectionsfailtomeetthetimingrequire-ments.Afterthelayoutiscomplete,resistanceandcapacitanceeffectsof onecomponentonanothercanbeextractedandaccuratetimingforeachcompo-nentcanbecalculated.Ifsomeconnectionsorcomponentsfailtomeettheirtimingrequirements,orfailduetotheeffectofonecomponentonanother,thensomeorallphasesofphysicaldesignneedtoberepeated.Typically,these repeat-or-not-to-repeat decisions are made by experts rather than tools.Thisisduetothecomplexnatureof thesedecisions,astheydependonahostofparameters.1.5DesignStylesPhysicaldesignisanextremelycomplexprocess.Evenafterbreakingtheentireprocessintoseveralconceptuallyeasiersteps,ithasbeenshownthateach step is computationally very hard.However, market requirements demandquicktime-to-marketandhighyield.Asaresult,restrictedmodelsanddesignstylesareusedinordertoreducethecomplexityofphysicaldesign.Thispracticebegan inthelate1960sand led to thedevelopment of several restricteddesignstyles[Feu83].Thedesignstylescanbebroadlyclassifiedaseitherfull-custom or semi-custom.In a full-custom layout, different blocks of a circuit canbeplacedatanylocationonasiliconwaferaslongasalltheblocksarenon-overlapping.Ontheother hand,insemi-customlayout,someparts of a circuitare predesigned and placed on some specific place on the silicon wafer.Selectionof alayoutstyledependsonmanyfactorsincludingthetypeof chip,cost,andtime-to-market.Full-custom layout is a preferred style for mass produced chips,sincethetimerequiredtoproduceahighlyoptimizedlayoutcanbejustified.On the other hand, to design an Application Specific Integrated Circuit(ASIC),16 Chapter 1. VLSI Physical Design AutomationPhysical DesignNoCircuit DesignTiming, size constraintsPartitioningYesTimingSize constraintsFloorplanningandPlacementFabricationFigure1.4: Newphysical designcycle.1.5. Design Styles 17a semi-custom layout style is usually preferred.On a large chip, each block mayuseadifferentlayoutdesignstyle.1.5.1Full-CustomInitsmostgeneralformofdesignstyle,thecircuitispartitionedintoacollection of sub-circuits according to some criteria such as functionality of eachsub-circuit.Theprocessisdonehierarchicallyandthusfull-customdesignshaveseverallevelsofhierarchy.Thechipisorganizedinclusters,clustersconsistofunits,andunitsarecomposed of functionalblocks(inshort,blocks).For sake of simplicity, we use the term blocks for units, blocks, and clusters.Thefull-customdesignstyleallowsfunctionalblockstobeof anysize.Figure1.5showsanexampleofaverysimplecircuitwithfewblocks.Otherlevelsofhierarchy are notshown for this simple example.Internal routing in each blockisnotshownforthesakeofclarity.Inthefull-customdesignstyle,blockscanbeplacedatanylocationonthechipsurfacewithoutanyrestrictions.Inotherwords,thisstyleischaracterizedbytheabsenceofanyconstraintsonthephysicaldesignprocess.Thisdesignstyleallows forverycompactdesigns.Figure 1.5: Full-custom structure.18 Chapter 1. VLSI Physical Design AutomationHowever, the process of automating a full-custom design style has a much highercomplexitythanotherrestrictedmodels.Forthisreasonitisusedonlywhenthefinaldesignmusthaveminimumareaanddesigntimeislessofafactor.Theautomationprocessforafull-customlayoutisstillatopicofintensiveresearch.Somephasesofphysicaldesignofafull-customchipmaybedonemanually to optimize the layout.Layout compaction isa very importantaspectinfull-customdesign.Therectangularsolidboxesaroundtheboundaryof thecircuitarecalledI/O pads.Padsareused tocompleteinterconnectionsbetweendifferentchipsorinterconnectionsbetweenthechipandtheboard.Thespacesnotoccupiedbyblocksareusedforroutingof interconnectingwires.Initiallyalltheblocksareplacedwithinthechiparea withtheobjectiveof minimizingthetotalarea.However, theremustbeenoughspaceleftbetweentheblockssothatroutingcanbecompletedusingthisspaceandthespaceontopof theblocks.Usuallyseveralmetallayersareusedforroutingofinterconnections.Currently,threemetallayersarecommonforrouting.Afourmetallayerprocessisbeingusedformicroprocessors,andasixlayerprocessisgainingacceptance,asfabricationcostsbecomemorefeasible.InFigure1.5,notethatwidth of the M1 wire is smaller than the width of the M2 wire. Also notethatthesizeoftheviabetweenM1andM2issmallerthanthesizeoftheviabetweenhigherlayers.Typically,metalwidthsandviasizesarelargerforhigherlayers.Thefigurealsoshowsthatsomeroutinghasbeencompletedontopof theblocks.Theroutingarea neededbetweentheblocksisbecomingsmallerandsmallerasmoreroutinglayersareused.Thisisduetothefactthatmoreroutingisdoneontopofthetransistorsintheadditionalmetallayers.Ifalltheroutingcanbedoneontopofthetransistors,thetotalchipareaisdeterminedbytheareaofthetransistors.However,ascircuitsbecomemorecomplexandinterconnectrequirementsincrease,thediesizeisdeterminedbytheinterconnectareaandthetotaltransistorareaservesasalowerboundonthediesizeof thechip.Inahierarchicaldesignof acircuit,eachblockina full-customdesignmaybeverycomplexandmayconsistof severalsub-blocks,whichinturnmaybedesignedusingthefull-customdesignstyleorotherdesignstyles.Itiseasytoseethatsinceanyblockisallowedtobeplacedanywhereonthechip,theproblemof optimizingareaandtheinterconnectionof wiresbecomesdifficult.Full custom design is very time consuming; thus the method is inappropriate forvery large circuits, unless performance or chip size is of utmost importance.Fullcustomisusuallyusedfor the layoutof microprocessors and otherperformanceandcostsensitivedesigns.1.5.2StandardCellThedesignprocessinthestandardcelldesign styleissomewhatsimplerthanfull-customdesignstyle. Standardcellarchitectureconsidersthelayouttoconsistof rectangularcellsof thesameheight.Initially,acircuitispartitionedintoseveralsmallerblocks,eachofwhichisequivalenttosomepredefinedsubcircuit(cell).Thefunctionalityandtheelectricalcharacteristicsofeach1.5. Design Styles 19predefinedcellare tested,analyzed,andspecified.Acollection of thesecellsiscalledacelllibrary.Usuallyacelllibraryconsistsof 500-1200 cells.Terminalsoncellsmaybelocatedeitherontheboundaryordistributedthroughoutthecellarea.Cellsareplacedinrowsandthespacebetweentworowsiscalledachannel.Thesechannelsandthespaceaboveandbetweencellsisusedtoperforminterconnectionsbetweencells.If twocellstobeinterconnectedlieinthe same row or inadjacent rows, then the channel between the rows is used forinterconnection.However,iftwocellstobeconnectedlieintwonon-adjacentrows,thentheirinterconnectionwirepassesthroughemptyspacebetweenanytwocellsorpassesontopof thecells.Thisemptyspacebetweencellsinarowiscalleda feedthrough.Theinterconnectionsaredoneintwosteps.Inthefirststep,thefeedthroughsareassignedfortheinterconnectionsofnon-adjacentcells.Feedthroughassignmentisfollowedbyrouting.Thecellstypicallyuseonly onemetal layer for connections inside thecells.Asa result,ina two metalprocess,thesecondmetallayer canbeusedforrouting inover-the-cell regions.Inathreemetallayerprocess,almostallthechannelscanberemovedandallroutingcanbecompletedoverthecells.However,thisisafunctionof thedensityofcellsanddistributionof pinsonthecells.Itisdifficulttoobtainachannellesslayoutforchipswhichusehighlypackeddense cellswithpoorpindistribution.Figure1.6showsanexampleofastandardcelllayout.Acelllibraryisshown,along withthecompletecircuitwithalltheinterconnections,feedthroughs,andpowerandgroundrouting.Inthe figure, thelibraryconsistsoffourlogiccellsandonefeedthroughcell.Thelayoutshownconsistsofseveralinstancesofcellsinthelibrary.Notethatrepresentationofalayoutinthestandardcelldesignstyleisgreatlysimplifiedasitisnotnecessarytoduplicatethecellinformation.Thestandardcelllayoutisinherentlynon-hierarchical.Thehierarchicalcircuits,therefore,havetoundergosometransformationbeforethisdesignstylecan be used.Thisdesign styleiswell-suited for moderatesize circuitsandmediumproductionvolumes.Physical design usingstandardcellsissomewhatsimplerascomparedtofull-custom,andisefficientusingmoderndesigntools.Thestandardcelldesignstyleisalsowidelyusedtoimplementtherandomorcontrol logic partof thefull-customdesignasshowninFigure1.5.LogicSynthesisusuallyusesthestandardcelldesignstyle.Thesynthesizedcircuitismappedtocellcircuits.Thencellsareplacedandrouted.Whilestandardcelldesignsarequickertodevelop,asubstantialinitialinvestment is needed in the development of the cell library, which may consist ofseveral hundredcells.Each cellin thecelllibrary is hand crafted and requireshighlyskilledphysicaldesignspecialists.Eachtypeofcellmustbecreatedwithseveraltransistorsizes.Eachcellmustthenbetestedbysimulationandits performance must be characterized.Cell library development is a significantprojectwithenormousmanpowerandfinancialresourcerequirements.Astandardcelldesign usually takesmore area thana full-custom ora hand-crafteddesign.However,asmoreandmoremetallayersbecomeavailableforroutinganddesigntoolsimprove,thedifferenceinarea betweenthetwodesignstyleswillgraduallyreduce.20 Chapter 1. VLSI Physical Design Automation1.5.3GateArraysThisdesignstyleisasimplificationof standardcelldesign.Unlikestandardcell design, all the cells in gate array are identical.Each chip is an array of iden-ticalgatesorcells.Thesecellsareseparatedbybothverticalandhorizontalspacescalledverticalandhorizontalchannels.Thecircuitdesignismodifiedsuchthatitcanbepartitionedintoanumberofidenticalblocks.Eachblockmustbelogicallyequivalenttoacellonthegatearray.Thenamegatearraysignifiesthefactthateachcellmaysimplybeagate,suchasathreeinputNANDgate.Eachblockindesignismappedorplacedontoaprefabricatedcellonthechipduringthepartitioning/placementphase, whichisreducedtoa block tocellassignmentproblem.The numberof partitionedblocksmustbelessthanorequaltothetotalnumberofcellsonthechip.OncethecircuitCell libraryDFeedthrough cellFigure1.6: Standard cell structure.1.5. Design Styles 21ispartitionedintoidenticalblocks,thetaskistomaketheinterconnectionsbetweentheprefabricatedcellsonthechipusing horizontalandverticalchan-nelstoformtheactualcircuit.Figure1.7showsan uncommitted gatearray,whichissimplya termusedfora prefabricatedchip.Thegatearraywaferistaken intoa fabrication facilityandrouting layersare fabricatedontopof thewafer.Thecompletedwaferisalsocalledacustomizedwafer.Itshouldbenotedthatthenumberof tracksallowedforroutingineachchannelisfixed.As a result,the purpose of the routing phase is simply to complete the connec-tionsratherthanminimizethearea.Twolayersofinterconnectionsaremostcommon;thoughoneandthreelayersarealsoused. Figure1.8illustratesacommittedgate array design.Like standard celldesigns,synthesis canalso usethegatearray style.Ingate array designthe entirewafer,consisting of severaldozenchips,isprefabricated.This simplicity of gate array design isgained at thecostof rigidity imposeduponthecircuitbothbythetechnologyandtheprefabricatedwafers.Theadvantage of gate arrays is that the steps involved for creating any prefabricatedwafer are the same and only the last few steps in the fabrication process actuallydepend on the application for which the design will be used.Hence gate arraysarecheaper andeasiertoproduce thanfull-customorstandardcell.Similar tostandardcelldesign,gatearrayisalsoanon-hierarchicalstructure.Thegatearray architectureisthemostrestrictedformof layout.Thisalsomeansthatitisthesimplestforalgorithmstoworkwith.Forexample,thetaskofroutingingatearrayistodetermineifagivenplacementisroutable.Theroutabilityproblemisconceptuallysimplerascomparedtotherouting ttfrftttrrfftttftfrrffttrrfrfrt} tt}rrftrtrrftrtrfrttt}ff}}rrrfrf rrttt}rft}ttfttttt}}}ttft}r}trtf tt}}rtrft}tttr}rtrftttt}trr}tttr trrtt}trfrtft}ffttrrfrtttffftttf }ttrft}ttrtfftfftrttrft}tttttrtf }trttrrfttfftrttft}}t}fr}fttf}ff rfrffrfftf}}fff}tffffft}ffr}fftf Figure1.7: A conceptual uncommittedgate array.22 Chapter 1. VLSI Physical Design Automationprobleminstandardcellandfull-customdesignstyles.1.5.4FieldProgrammableGateArraysTheFieldProgrammableGateArray(FPGA)isanewapproachtoASICdesignthatcandramaticallyreducemanufacturingturn-aroundtimeandcostforlowvolumemanufacturing[Gam89, Hse88,Won89].InFPGAs,cellsandinterconnectareprefabricated.Theusersimplyprogramstheinterconnect.FPGAdesignsprovidelargescaleintegrationanduserprogrammability.AFPGAconsistsof horizontalrowsof programmablelogicblockswhichcanbeinterconnected by a programmable routing network.FPGA cells are more com-plexthanstandardcells.However,almostallthecellshavethesamelayout.In its simplistic form,a logic block is simply a memory block which can be pro-ABcc Figure1.8: A conceptual gate array.1.5. Design Styles 23ABC-f-i'f-r--/

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;;:;;; B6 ..iiiit:g;;:g;;:;; ;I..' , 'Bsiii.CI.cU:iUi i iii, ..8u999Figure1.9: A committedFPGA.24 Chapter 1. VLSI Physical Design Automationgrammedtorememberthelogic tableof a function.Givenacertaininput,thelogic block looks up the corresponding outputfrom thelogic tableandsetsitsoutputlineaccordingly.Thusbyloadingdifferentlook-uptables,a logicblockcanbeprogrammed toperformdifferentfunctions.Itisclearthatbitsarerequired ina logic block torepresentaK-bitinput,1-bitoutputcombinationallogicfunction.Obviously,logicblocksareonlyfeasibleforsmallvaluesof K.Typically,thevalueofKis5or6.Formultipleoutputsandsequentialcir-cuitsthevalueofKisevenless.Therowsoflogicblocksareseparatedbyhorizontal routing channels.The channelsare notsimply emptyareas inwhichmetallinescanbearrangedforaspecificdesign.Rather,theycontainprede-fined wiring segments of fixed lengths.Each input and output of a logic blockisconnectedtoadedicatedverticalsegment.Otherverticalsegmentsmerelypassthroughtheblocks,servingasfeedthroughsbetweenchannels.Connec-tionbetweenhorizontalsegmentsisprovidedthroughantifuses,whereastheconnectionbetweenahorizontalsegmentandaverticalsegmentisprovidedthroughacross fuse.Figure1.9(c)showsthegeneralarchitectureof aFPGA,which consists of four rows of logic blocks.The cross fuses are shown as circles,while antifuses are shown as rectangles.One disadvantage of fuse based FPGAsisthattheyarenotreprogrammable.ThereareothertypesofFPGAswhichallowre-programming,andusepassgatesratherthanprogrammablefuses.SincetherearenouserspecificfabricationstepsinaFPGA,thefabrica-tionprocesscanbesetupinacosteffectivemannertoproducelargequan-titiesofgeneric(unprogrammed)FPGAs.Thecustomization(programming)ofaFPGAisrathersimple.Givenacircuit,itisdecomposedintosmallersubcircuits,suchthateachsubcircuitcanbemappedtoalogicblock.Theinterconnectionsbetweenanytwosubcircuitsisachievedbyprogramming theFPGAinterconnectsbetweentheircorrespondinglogicblocks.Programming(blowing) one of the fuses (antifuse or cross fuse) provides a low resistance bidi-rectional connection between two segments.When blown, antifuses connect thetwo segments to form a longer one.In order to program a fuse,a high voltage isappliedacrossit.FPGAshavespecialcircuitrytoprogramthefuses.Thecir-cuitryconsistsof thewiringsegmentsandcontrollogicattheperipheryof thechip.Fuseaddressesareshiftedintothefuseprogrammingcircuitryserially.Figure1.9(a)showsacircuitpartitionedintofoursubcircuits,andNotethateachof thesefoursubcircuitshavetwoinputsandoneoutput.Thetruthtableforeachof thesubcircuitsisshowninFigure1.9(b).InFig-ure 1.9(c),andaremappedtologicblocksandrespectivelyandappropriate antifusesandcross fusesare programmed(burnt)toimplementtheentirecircuit.Theprogrammedfusesareshownasfilledcirclesandrectangles.Wehavedescribedtheonce-programtypeof FPGAs.ManyFPGAsallowtheusertore-programtheinterconnect,asmanytimesasneeded.TheseFPGAsusenon-destructivemethodsof programming,suchaspass-transistors.TheprogrammablenatureoftheseFPGAsrequiresnewCADalgorithmstomakeeffectiveuseof logicandroutingresources.TheproblemsinvolvedincustomizationofaFPGAaresomewhatdifferentfromthoseofotherdesign1.5. Design Styles 25styles;however,manystepsarecommon.Forexample,thepartitionproblemof FPGAs is different than partitioning the problem in all design style while theplacementandtheroutingissimilartogatearrayapproach.TheseproblemswillbediscussedindetailinChapter11.1.5.5SeaofGatesTheseaofgatesisanimprovedgatearrayinwhichthemasterisfilledcom-pletelywithtransistors.Themasterofthesea-of-gateshasamuchhigherdensityoflogicimplementedonthechip,andallowsadesignertofabricatecomplexcircuits,suchasRAMs,tobebuilt.Intheabsenceof routingchan-nels,interconnectshave tobecompleted eitherbyrouting through gates,orbyaddingmoremetalorpolysiliconinterconnectionlayers.Thereareproblemsassociatedwitheithersolution.Theformerreducesthegateutilization;thelatterincreasesthemaskcountandincreasesfabricationtimeandcost.1.5.6Comparison of DifferentDesign StylesThechoice of designstyledependsontheintendedfunctionalityof thechip,time-to-marketandtotalnumber of chipstobemanufactured.Itiscommontouse full-custom design style for microprocessors and other complex high volumeapplications, while FPGAs may be used for simple and low volume applications.However,there are several chips which have been manufactured by using a mixofdesignstyles.Forlargecircuits,itiscommontopartitionthecircuitintoseveralsmallcircuitswhicharethendesignedbydifferentteams.Eachteammayuseadifferentdesignstyleoranumberofdesignstyles.Anotherfactorcomplicatingtheissueofdesignstyleisre-usabilityofexistingdesigns.Itisacommonpracticetore-usecompleteorpartiallayoutfromexistingchipsfornewchips toreduce the cost of a newdesign.Itisquite typical touse standardcellandgatearraydesignstylesforsmallerandlesscomplex ApplicationSpe-cificICs(ASICs),whilemicroprocessorsaretypicallyfull-customwithseveralstandardcellblocks.Standardcellblockscanbelaidoutusinglogicsynthesistools.Designstylescanbeseenasacontinuumfromveryflexible(full-custom)toaratherrigiddesignstyle(FPGA)tocatertodifferingneeds.Table1.1summarizesthedifferencesincellsize,celltype,cellplacementandintercon-nectionsinfull-custom,standardcell,gatearrayandFPGAdesignstyles.Anothercomparisonmaybeonthebasisofarea,performance,andthenum-beroffabricationlayersneeded.(SeeTable1.2).Ascanbeseenfromthetable,full-customprovidescompactlayoutsforhighperformancedesignsbutrequiresaconsiderablefabricationeffort.Ontheotherhand,aFPGAiscom-pletelypre-fabricatedanddoesnotrequireanyuserspecificfabricationsteps.However,FPGAscanonlybeusedforsmall,generalpurposedesigns.26 Chapter 1. VLSI Physical Design Automation1.6SystemPackagingStylesTheincreasingcomplexityanddensityof semiconductordevicesarethekeydrivingforcesbehindthedevelopmentofmoreadvancedVLSIpackagingandinterconnectionapproaches.Twokeypackagingtechnologiesbeingusedcur-rentlyarePrintedCircuitBoards(PCB)andMulti-ChipModules(MCMs).Letusfirststartwithdiepackaging techniques.1.6.1DiePackagingandAttachmentStylesDiescanbepackagedinavarietyof stylesdependingoncost,performanceandarearequirements.Otherconsiderationsincludeheatremoval,testingandrepair.1.6.1.1DiePackageStylesICsarepackagedintoceramicorplasticcarrierscalledDualIn-LinePack-ages(DIPs),thenmountedonaPCB.Thesepackageshaveleadson2.54mmcenters on two sides of a rectangular package.PGA(PinGridArray)isa pack-ageinwhichpinsareorganizedinseveralconcentricrectangularrows.DIPsandPGAsrequire large thru-holes to mount them on boards.Asa result,thru-hole assemblies were replaced by Surface MountAssemblies(SMAs).InSMA,stylefull-custom standardcell gate array FPGAcell size variable fixedheight fixed fixedcell type variable variable fixed programmablecell placement variable inrow fixed fixedinterconnections variable variable variable programmabledesigncost high medium medium lowTable1.1: Comparison of differentdesign styles.uneven height cellsare alsoused.stylefull-custom standard cell gate array FPGAArea compact compact moderate largetomoderatePerformance high high moderate lowtomoderateFabricate Alllayers All layers Routing layers only NolayersTable 1.2: Area, Performance and Fabrication layers fordifferent design styles.1.6. System Packaging Styles 27pinsof thedevice do notgo throughtheboard,theyare soldered tothesurfaceoftheboard.Asaresult,devicescanbeplacedonbothsidesoftheboard.TherearetwotypesofSMAs;leadedandleadless.Bothareavailableinquadpackageswithleadson1.27,1.00,or0.635mmcenters.Yetanothervariationof SMAistheBallGridArray(BGA),whichisanarrayof solderballs.TheballsarepressedontothePCB.WhenaBGAdeviceisplacedandpressedtheballsmeltformingaconnectiontothePCB.Allthepackagesdiscussedabovesufferfromperformancedegradationduetodelaysinthepackage.Insomeapplications,anakeddieisuseddirectlytoavoidpackagedelays.1.6.1.2PackageandDieAttachmentStylesThechipsneedtobeattachedtothenextlevelofpackaging,calledsystemlevel packaging.The leads of pin based packages are bentdown and are solderedintoplatedholeswhichgoinsidetheprintedcircuitboard.(seeFigure1.10).SMAssuchasBGAdonotneed thruholesbutstillrequirearelativelylargefootprint.Inthecaseofnakeddies,dietoboardconnectionsaremadebyattachingwiresfromtheI/Opadsontheedgeof thedietotheboard.Thisiscalledthewirebondmethod,andusesaroboticwirebondingmachine.Theactivesideof thediefacesawayfromtheboard.Althoughpackagedelaysareavoidedinwirebondeddies,thedelayinthewiresisstillsignificantascomparedtotheinterconnectdelayonthechip.ControlledCollapsedChipConnection(C4)isanothermethodof attachinganakeddie.Thismethodaimstoeliminatethedelaysassociatedwiththewiresinthewirebondmethod.TheI/Opinsaredistributedoverthedie(ATMstyle)andasolderballisplacedovertheI/Opad.Thedieisthenturnedover,suchthattheactivesideisfacingtheboard,thenpressureisappliedtofusetheballstotheboard.TheexactlayoutofchipsonPCBsandMCMsissomewhatequivalenttothelayoutofvariouscomponentsinaVLSIchip.Asaresult,manylayoutproblemssuchaspartitioning,placement,androutingaresimilarinVLSIandpackaging.In this section,we briefly outline the two commonly used packagingstylesandthelayoutproblemswiththesestyles.1.6.2PrintedCircuitBoardsAPrintedCircuitBoard(PCB)isamulti-layersandwichof routinglayers.CurrentPCBtechnologyoffersasmanyas30ormoreroutinglayers.Viaspecificationsarealsoveryflexibleandvary,suchthatawidevarietyofcom-binationsispossible.Forexample,a setof layerscanbeconnectedbyasinglevia called thestackedvia.The traditional approach of single chippackages on aPCBhave intrinsic limitationsinterms of silicon density,systemsize,andcon-tributiontopropagationdelay.Forexample,thetypicalinnerleadbondpitchonVLSIchipsis0.0152cm.Thefinest pitchfora leadedchipcarrier is0.0635cm.Theratioof theareaof thesiliconinsidethepackagetothepackagearea28 Chapter1.VLSIPhysicalDesignAutomationisabout6%.IfaPCBwerecompletelycoveredwithchipcarriers,theboardwouldonlyhaveatmosta6%efficiencyofholdingsilicon.Inotherwords,94%ormoreoftheboardareawouldbewastedspace,unavailabletoactivesiliconandcontributingtoincreasedpropagationdelays.Thru-holeassembliesgave way to Surface Mount Assemblies(SMAs).SMAs eliminated the need forla