Active-HDL 9.1 Student Edition Release Notes

Active-HDL 9.1 Student Edition Release Notes

file:///C|/Users/LILIA/AppData/Local/Temp/pft61E9.tmp/ReleaseN.htm[14/10/2012 20:37:38]

Introduction Limitations of the Student Edition What's New in Version 9.1?LicensingCompiler and SimulatorDebuggerSimulation DatabaseUnified Coverage DatabaseStatement/Branch CoveragePath CoverageIntegration with Aldec Verification ToolsLibrariesDesign Flow ManagerDesign BrowserConsoleHDL EditorVHDL Code BrowserBlock Diagram EditorState Diagram EditorAccelerated Waveform ViewerScriptsIP ProtectionActive-HDL Interfaces and WizardsInstallationDocumentationOthersProblems Corrected in Version 9.1

What's New in Previous Versions? Software and Hardware Requirements Installing Active-HDLFirst Time InstallationSelection of Optional Components and System LibrariesManual Installation of Vendor LibrariesRe-installationInstalling Service PacksPrevious Version InstalledDirectory StructureNetwork Client Installation

LicensingFull VersionLicense HostidLocal License (Node-locked)Network Floating LicenseLicense Maintenance

Race Conditions Known ProblemsSimulatorCompilerList ViewerDesign Flow ManagerBlock Diagram EditorCode2Graphics(TM) ConverterState Diagram EditorWaveform ViewerSimulink(R) / MATLAB(R) InterfaceSWIFT(TM) SmartModels Library InterfaceInterfaces to Third-Party ToolsLibrary ManagerTestbench GenerationActive-HDL and VSimSA scripting incompatibilityHDL EditorDesign BrowserExport Design to HTML/PDFExport to GraphicsImport of Third-party ProjectsC/HDL DebugAdvanced DataflowMemory ViewerFollow ObjectConsoleMixed HDL DesignsInstallationScriptsFramework

Active-HDL Student Edition is based on version 9.1 (BUILD 2353.4205, 10/24/2011). This edition provides manynew features and enhancements to increase the productivity. The goal of the Student Edition is to provide students bettertools for their course work and projects.

Active-HDL Student Edition has a load-and-go type of license mechanism. This will allow students to use the toolimmediately after the installation. They do not have to register the product in order to get the license. However, Active-HDL Student Edition build has the validity until December 31, 2013. After the build is expired, the latest release ofStudent Edition can be downloaded from the Aldec web site by simply registering yourself.

Active-HDL Student Edition is limited in terms of features in comparison to a commercial version of Active-HDL.Refer to the Limitations of the Student Edition section for details.

What's New in Version 9.1?The following is a brief overview of new features and changes introduced to the commercial version of Active-HDL 9.1:

Licensing

Active-HDL 9.1 requires validation of your existing maintenance contract. The latest version requires a validmaintenance contract as of 9/1/2011. For more information refer to the License Maintenance section of theLicensing chapter.

Changes to the licensing features have been introduced. These changes do not take any functionality away fromthe existing configuration or tool set and they are made in order to improve product launch time and to minimizetime of querying the features. However, an updated license is required in order to fully utilize Active-HDL 9.1.

License Features ChangesASDB to CTF Conversion Merged into Design EntryASDB to CTV Conversion Merged into Design EntryASDB to LST Conversion Merged into Design EntryASDB to Macro Conversion Merged into Design EntryASDB to SES Conversion Merged into Design EntryASDB to TSSI Conversion Merged into Design EntryASDB to VCD Conversion Merged into Design EntryBDE I/O Port Conversion Functions Merged into BDEFollow Object Merged into Design EntryHandel-C Code Debug Merged into Design EntryHandel-C Co-simulation Verilog Merged into Design EntryHandel-C Co-simulation VHDL Merged into Design EntryHDE User Actions Player Merged into Design EntryHDE User Actions Recorder Merged into Design EntryVerilog-HDE Merged into Design EntryVHDL-HDE Merged into Design EntryOVA File Support Merged into Design EntryPSL File Support Merged into Design EntryImport Actel Coreconsole design Merged into new Import 3rd Party ToolsImport Altera Quartus projects Merged into new Import 3rd Party ToolsImport Altera SOPC Simulation Script Merged into new Import 3rd Party ToolsImport Mentor Modelsim Project Merged into new Import 3rd Party ToolsImport Synplify/Synplify Pro Project Merged into new Import 3rd Party ToolsImport Viewlogic Project Merged into new Import 3rd Party ToolsImport Xilinx EDK Simulation Script Merged into new Import 3rd Party ToolsImport Xilinx ISE Project Merged into new Import 3rd Party ToolsState Diagram Multi-Process VHDLGenerator Merged into FSM

New Feature in 9.1 - all Import features are



Preferences ManagerWindows XP/Vista/7Source Revision Control InterfaceServer FarmCode CoverageToggle CoverageProgramming Language Interface (PLI)IP Core GeneratorOn-line DocumentationOthers

Unsupported Verilog Constructs Unsupported ACC Routines Unsupported TF Routines Unsupported VHPI Routines Built-in Standard Packages System LibrariesStandard LibrariesVendor-Specific LibrariesUpdating System Libraries

Source Files for IEEE Packages On-line Documentation How to Reach Technical Support

Import 3rd Party Tools now controlled by one feature (except XilinxFoundation Import)

TCL Scripting Merged into Design EntryVerilog RTL & Gate PerformanceOptimization

Merged into Verilog Simulation (Speeddepends on configuration)

Unified Coverage Database (ACDB)New Feature in 9.1 - ability to us the UnifiedCode Coverage Database (Configurationdependent)

Altera (Simulator Verilog IP with VHDLSimulator only license)

New Feature in 9.1 - ability to simulate AlteraVerilog IP with a VHDL only License(Optional license feature)

Active-HDL requires FlexNet ver. 11.9.1.

The license features selected when starting the VSimSA simulation environment can be specified in the license.inifile stored in the \Dat subfolder. To select the license configuration, modify the following line in the license.ini:

default vsimsa feature=

The value provided in the configuration file can be either ACTIVEHDL_VSIMSA_EE (Expert Edition EE) orACTIVEHDL_VSIMSA (Plus Edition PE), for example:

default vsimsa feature=ACTIVEHDL_VSIMSA.

When not specified, the highest available licence feature is fetched/used. (SPT50899)

The license configuration with which VSimSA has been started, can be determined by using the new checklicensemacro command.

Compiler and Simulator

NOTE: Due to internal changes in the compiler and simulator as well as updates in third-party tool libraries, all user-defined libraries should be re-compiled after the installation of Active-HDL 9.1. The installation program of version 9.1delivers and installs only the updated system and vendor-specific libraries that do not require re-compilation afterActive-HDL is installed.All existing designs will not have any problems associated with re-compiling the libraries. If you update Active-HDL toversion 9.1 and do not re-compile your design libraries, the following error message will be displayed in the Consolewindow:# ELBREAD: Warning: Files created by the old version of the compiler found.# ELBREAD: Error: Library '' has incompatible format. Recompile all library units.

Hierarchical Names Specification

The specification of hierarchical path names reported and accepted by the simulation environment has beenstandardized. With this release, all absolute hierarchical names must begin with the hierarchy separator followedby the name of the top-level unit, e.g. /testbench/UUT/START. (Previously, the name of the top-level unit wasomitted.) An advantage of this solution is the unification in notation of the hierarchical names and the removal ofambiguities that could appear when using multiple top-level units during simulation. For more information, referto the Using Active-HDL | Hierarchical Names topic of the Active-HDL help. The use of the relative hierarchicalnames with a reference to the design region defined by using the env command remains unchanged. Some macrosor HDL code using ambiguous hierarchical names for single top-level module simulations may require an update.

All the debugging tools (e.g. Advanced Dataflow, Watch, Memory Viewer, Waveform Viewer, HDL Editor, etc.)working in the GUI mode present absolute hierarchical paths as the standardized hierarchical paths. Similarly, thehierarchical paths returned by the simulator begin with the hierarchy separator followed by the name of the top-level unit.

The character used for separating the hierarchy levels in hierarchical paths can be changed by using the new$hierarchyseparator predefined variable. The allowed separators are a slash (/) or a dot (.). By default, the slashcharacter is used as the hierarchy separator. This variable is equivalent to the Use hierarchy separator option inthe Preferences dialog box.

VHDL Compilation and Simulation

Simulation of concatenation expressions has been optimized. This optimization resulted in reduced simulation runtimes for designs using Altera IP. (SPT48401)

Simulation performance of VHDL designs containing particular uses of the wait until constructs has beenimproved. (SPT49537)

The names of the force and noforce procedures (available in the aldec_tools package of the pre-installed aldeclibrary) have been changed to force_signal and noforce_signal, respectively. The change has been introduced asforce is the reserved keyword of IEEE Std 1076-2008. (SPT60751)



Support for VHDL 2008 (IEEE Std 1076-2008) has been continuously extended. The following new VHDL2008 features are supported in this version of Active-HDL:

Arrays of unconstrained elements are supported.

type T is array (integer range ) of bit_vector;

Note that the declaration provides constraints neither for array dimensions nor the element type.(Unconstrained array dimensions were allowed by earlier VHDL versions; allowing unconstrained elements isa new feature of IEEE Std 1076-2008.)All objects of type T must be eventually constrained. Constraints can be applied either in an object declarationor in a declaration of a subtype of type T, for example:

-- constraints applied at object declarationsignal s1 : T(0 to 1)(15 downto 0);-- constraints applied to a subtypesubtype ST is T(0 to 1)(15 downto 0);signal s2: ST;

More complex types can be constrained in stages, for example:

-- An unconstrained array type T1 holding unconstrained bit_vectors.type T1 is array (integer range , integer range ) of bit_vector;-- An unconstrained array type holding unconstrained elements of type T1.type T2 is array (integer range ) of T1;-- Start with type T2 and apply constraints to subsequent dimensions-- until a fully constrained subtype ST4 is received.subtype ST2 is T2(1 to 2);subtype ST3 is ST2(open)(1 to 2, 1 to 2);subtype ST4 is ST3(open)(open)(7 downto 0);-- Declare two signals.-- Subtype ST3 is not fully constrained, so the missing-- constraints must be provided at object declaration.signal s1 : ST4;signal s2 : ST3(open)(open)( 7 downto 0 );

Note the use of the open keyword to indicate that the dimension has already been constrained. (SPT47326)

All VHDL pragmas can be labeled. Pragmas are labeled similarly to other statements, i.e. a label followed bya colon is placed in front of the pragma (and behind the comment mark):

--FOO: vhdl_cover_off

report ("VHDL code inside pragmas vhdl_cover_off / vhdl_cover_on.");

--FOO: vhdl_cover_on

A labeled pragma behaves identically to an unlabeled pragma, except that it can be disabled at compile time byusing the -ignore_pragma argument of the acom command. For example, to disable thepragma labeled FOO in the listing above, you could invoke the compiler as follows:

acom -ignore_pragma FOO file.vhd

Any pragma can be ignored, not just vhdl_cover_off. For example, you could label and selectively ignorepragmas vhdl_comp_off and vhdl_comp_on. (Those pragmas disable compilation of an enclosed block.)(SPT48050)

A record type or a subtype of unconstrained elements is supported.

-- An unconstrained array type T1_unconst holding unconstrained bits.type T1_unconst is array (natural range , natural range ) of bit;-- An unconstrained array type T2_unconst holding unconstrained elements of type T1_unconst.type T2_unconst is array (character range ) of T1_unconst;-- A record type of unconstrained elements.type REC isrecordelem1 : T1_unconst;elem2 : T2_unconst;end record;

Since the elements of the record are not constrained, an object of the REC type must be constrained either inan object declaration or in a declaration of a subtype of the REC type. (SPT50387)

The functionality of the -relax argument of the acom command (i.e. the argument that relaxes several LRMrequirements) has been extended to allow declaring entity attributes within an architecture of that entity. Thisfunctionality is required for compiling some models from selected vendor libraries. (SPT49762)

Verilog Compilation and Simulation

The default standard for compilation started from the GUI has been changed. Now, the compiler conforms by



default to IEEE Std 1364-2005.

The Verilog compiler recognizes the following keywords in all working modes (except for Verilog'95, i.e. thecompilation mode set with -v95 argument of the alog command or the equivalent GUI option): config, endconfig,design, instance, cell, use, and liblist. If used in source code, the keywords will trigger an error (except for theVerilog'95 mode) because Active-HDL does not yet support Verilog configurations. The actual error messagedepends on the context where the keyword is used, i.e.:Verilog configurations are not supported yet. or '%s' is a Verilog 2001 keywordIf your Verilog code happens to use the above mentioned keywords, it will cease to compile. Library refreshingwill not be possible either. In this case, you will have to either:- change the identifier names and recompile, or- run compilation in the Verilog'95 mode.The latter option will work only if constructs outside the scope of IEEE Std 1364-1995 are not used.

SystemVerilog Compilation and Simulation (Design Constructs Only)

The automatic variables can be referenced by predefined or user-defined PLI tasks and functions. Previously, onlythe static variables could be passed as arguments for these subroutines. (SPT50706)

Parameterized virtual interfaces and parameterized classes containing those interfaces as their protected memberscan be compiled separately. (SPT60377)

Constant references are now supported. (SPT47858)

Declarations of interfaces can be nested inside modules. (SPT48434)

Virtual interfaces can be declared within the compilation-unit scope.

Struct literals containing keys are supported. For example, the following assignment to the s structure with twointeger fields named x and y is now possible:

s = '{x:2,y:3};

Previously, only a literal without keys (s = '{2,3};) could be used. (SPT47049)

The wildcard index type (*) for associated arrays is fully supported. In the previous versions, the wildcard indexwas emulated by using the reg[511:0] type.

Events can be passed as task arguments. (SPT48955)

Events can be passed by reference.

Event merging is fully supported. In the previous version of Active-HDL, event merging was supported only forevents that were declared as dynamic class members.

Dynamic arrays of events are supported.

Assigning fixed-size arrays to dynamic arrays or queues and vice-versa is supported for one-dimensional arrays.

Part selections are available for queues. One limitation applies - a queue part-selection cannot be passed as anargument to a system task, such as the $display task.

Queues of strings are now supported.

Parameters can now be defined to be of type string. Previously, such parameters were not supported. (Stringconstants had to be used as a workaround.) (SPT46696)

Initialization at declaration for multidimensional packed arrays is supported.

Multidimensional packed arrays being elements of packed structures are supported. (SPT47170)

Using the non-compile-time constants, e.g. genvar, parameter, constant, in hierarchical names is now supported.(SPT17331, SPT18965, SPT19609, SPT46003, SPT48584, SPT48960, SPT49444, SPT49623, SPT50787)

Non-constant expressions are allowed as the multiplier operands in a string replication operation, for example:

int i = 3;

string str = {i{"rep "}}; // str = "rep rep rep "

In previous versions of the compiler, the above operation would trigger a syntax error.

The %p format for the $display and $write families of tasks can be used with an optional 0 field, for example:

$display ("%0p", hndl);

This field indicates that nested properties should not be printed recursively. If the hndl class handle containsproperties that are themselves class instances, they will be output as or null. A sample output for%p could look as follows:

'{i:1, c1:'{foo:0, bar:0, baz:'{0, 0, 0, 0}}, c2:'{foo:0, bar:0, baz:'{0, 0, 0, 0}}, c3:null}



Using 0 in the format specifier (%0p) would limit the output in the following manner:

'{1, , , null}

Function and task prototypes are now accepted in modports. (SPT46383)

Circular `include dependency is not considered a compilation error. In case a circular inclusion is detected, thecompiler reports an appropriate warning and continues the compilation. In case an infinite inclusion occurs, theuser can identify the source of the problem by referring to the warning message. Previously, in such casescompilation was stopped. (SPT49568)

Error reporting in case of encountering duplicate declarations in Verilog/SystemVerilog source files was improved.Along with an error message, the compiler reports a reference to the previous occurrence of the declaration.Double-clicking this message opens the source file in the referenced location. This feature is especially usefulwhen the design resources are stored across multiple directories.

The compilation time warning message "Bind target tb.UUT has not been found. Using blind compilation." whichappeared when an undeclared unit was bound to the project using the bind construct was changed to "Bind target'tb.UUT' cannot be found. Connection rules will be checked during elaboration."

The $recovery system timing check can be used according to the syntax similar to $recrem:

$recovery(reference_event, data_event, removal_limit, recovery_limit, [notifier], [tstamp_cond], [tcheck_cond],[delayed_clk], [delayed_data]);

It is an out-of-standard extension which was implemented to improve user convenience. The syntax described inthe IEEE Std 1800-2009 standard, that is, without removal_limit argument can also be used:

$recovery ( reference_event , data_event , timing_check_limit [ , [ notifier ] ]);

(SPT60773)

The $urandom() and the $urandom_range() system functions are supported. (SPT60502)

SystemVerilog Assertions

The $assertkill, $asserton, and $assertoff assertion control system tasks are now supported. (SPT46060, SPT47127,SPT47861)

Mixed-Language Compilation and Simulation

The bind SystemVerilog construct is supported and can be used to bind SystemVerilog verification code to VHDLunits. Syntax of the statement consists of the bind keyword followed by a VHDL target and a SystemVerilogmodule instantiation. The bind target can be either a VHDL hierarchical name or a VHDL entity. The moduleinstantiation consists of a module identifier, an optional parameter value assignment, an instance name and a listof port connections. The following example shows binding to the top.uut VHDL instance. (SPT51137)

bind top.uut vcheck vcheck_1( clk, d, q );

When binding to an entity, use the entity name (e.g. flp) instead of the instance name, for example:

bind flp vcheck vcheck_1( clk, d, q );

The above statement will bind the vcheck unit to all instances of the flp entity.(SPT48610, SPT48860, SPT49076, SPT49077)

Batch-mode Compiler and Simulator

The Auto-Complete feature has been implemented in the VSimSA command prompt. The new option facilitatesthe use of built-in commands and it can predict:

The names of the macro commands

The names of files and folders being arguments of the built-in commands.

Pressing the Tab key in the VSimSA Console displays the names of matching items based on their initial letterstyped in the command prompt. (SPT46266)

Debugger

The Cover Breakpoints tab has been added to the Breakpoints dialog box. In the new tab, you can manipulate allthe breakpoints set on the cover statements by using the bc macro command, e.g. temporarily disable, enable, orremove a breakpoint, or change conditions that trigger the breakpoint.

Simulation Database



Simulation databases (*.asdb) can be created, manipulated, merged, or acquired from the command line by usingthe new functionality of the asdbman command. Refer to the Scripts section for additional information.(SPT15297)

The data layout in the simulation database has been optimized resulting in appreciably smaller ASDB file sizes.The size reduction depends on the design and the selection of recorded signals. You can expect newly recordedASDB files to be half the size on the average compared to ASDB files recorded in the previous version of Active-HDL. However, in selected usage scenarios, e.g. when only a few signals are recorded, the size of the ASDB filemay be reduced by two orders of magnitude. Active-HDL, version 9.1 can still load ASDB files recorded by theprevious versions of the software (e.g. by Active-HDL version 8.3). However, older versions of Active-HDL (e.g.version 8.3) will not be able to read ASDB files recorded by Active-HDL version 9.1 or newer.

The amount of memory allocated by the module recording signals to the simulation database (ASDB) has beenreduced.

Unified Coverage Database

The new unified storage format of the coverage database has been introduced - Aldec Coverage Database(ACDB). ACDB can currently store the following coverage types (the support for other coverage types ispending):

Statement Coverage

Branch Coverage

The unified format allows exchanging databases with coverage data between Aldec products, merging coverageresults, viewing, and generating reports with coverage statistics.The main new features of the new database are:

Dynamic control of coverage data during simulation with the new acdb clear, acdb disable, acdb enable, acdboff, and acdb save commands. Refer to the Scripts section for additional information.

Possibility to save data of different coverage types to the same database during simulation

Possibility to merge coverage data from multiple simulation runs into a cumulative database (temporal, spatial,and heterogeneous use cases)

Generation of HTML reports for advanced analysis of coverage statistics

The C-based API (compliant with Accellera Unified Coverage Interoperability Standard) allows buildingprocedures for coverage analysis, customizing the report process, transferring coverage data from externaltools into Aldec simulator, etc.

The ACDB database can store coverage data from the entire simulation or it can contain a snapshot made at anymoment of the simulation process. To collect coverage data, the debug mode should be enabled during compilationof VHDL and Verilog source files (pass the -dbg argument of the acom and/or alog commands) and then initializesimulation with the -acdb argument of the asim command. For more information, refer to the Coverage Databasetopic in the on-line documentation. (SPT50527)

Statement/Branch Coverage

Generation of text and HTML reports from Statement Coverage statistics has been enhanced to allow excludingcovered lines and including the context of not covered lines in the report. (SPT46241, SPT46190, SPT46242)

The Subprograms tab has been added to the Code Coverage Viewer. The new tab replaced the Unusedsubprograms tab and now it presents statistics for two categories of subprograms: subprograms that wereexecuted at least once during simulation (Used subprograms) and for those that were not executed at all duringsimulation (Unused subprograms). Additionally, if a subprogram is declared in an external library, its name ispreceded by the name of this library. Otherwise, if the subprogram resides in the current working library, its nameis not presented. (SPT18514)

Tools for navigating through coverage results in the Code Coverage Viewer were improved. The browsing buttonsavailable for different types of results depend on the selection made in the Browse By list box. When browsing theresults by Expressions, two buttons are available for browsing to the next/previous line with expression coveragedata. When browsing by Branch, Block, or Statement coverage types, four buttons are available for the next orprevious, covered or not covered lines.

Path Coverage

In previous versions, the Source column of a Path Coverage report contained only a piece of code showing themost nested and explicit expressions while parental conditions were assumed to be met and omitted in the report.Now, the Source column can also contain information about selected or all implicit conditional expressions that



form individual program paths. Additionally, source code presented in that column is formatted and the lineindentation corresponds to nesting levels of the conditional expressions in original VHDL source code.The additional lines showing parental conditions are reported if the Nested depth option available in theExpression/Path Coverage category of the Design Settings dialog box is enabled or when the -pac_nested_depthargument of the asim command is passed. Refer to the Scripts section for additional information.

Integration with Aldec Verification Tools

Active-HDL offers a new feature that enables projects to be moved from Active-HDL to other Aldec products(ALINT and Riviera-PRO). The interface can launch your designs in those tools based on the options specified inActive-HDL. This allows switching between Aldec products dedicated for different design stages, while stillsharing the same design resources. Note that the product-specific files are stored separately, which protects themfrom being overwritten, or mistakenly removed. The following Aldec products are supported:

ALINT

Riviera-PRO

Active-HDL VSimSA

Riviera-PRO VSimSA

Two modes of operation are available: automatic (based on the options specified in the Design Settings dialogbox), and manual (all actions are controlled by a custom script). For more information refer to the VerifyingDesigns in ALINT and Launching Simulation in Riviera-PRO/VSimSA topics of the Active-HDL Product Help(Help | Product Help). (SPT47012, SPT47150, SPT47266, SPT47508, SPT47726, SPT48023, SPT50601,SPT50602, SPT60476, SPT60727)

Libraries

The following general changes have been implemented to the libraries delivered with Active-HDL 9.1:

All Verilog vendor libraries have been renamed. In the previous versions, the "OVI_" prefix was used in thenames of the libraries. In the current version, the "_VER" suffix is used. The change introduced to the names ofthe libraries may affect proper compilation and simulation of older designs migrated to version 9.1. Designssettings and (re)sources where vendor libraries are specified, for example arguments passed to the alog or asimcommands user-defined macros, the options in the File Properties (Compile tab) or Design Settings (VerilogCompilation/Simulation categories) dialog boxes, libraries specified in the Libraries tab of the SynthesisOptions dialog box, automatically generated scripts, etc. may require additional updates. The change does notapply to the simulation libraries dedicated to the Lattice technology.

The following updates have been introduced to the system and vendor-specific libraries:

New Simulation Libraries

Implementation1. Altera Quartus II 11.1 SP1 (ALTERA_LNSIM, ARRIAIIGZ, ARRIAIIGZ_HSSI, ARRIAIIGZ_PCIE_HIP,MAXV, ALTERA_LNSIM_VER, ARRIAIIGZ_VER, ARRIAIIGZ_HSSI_VER, ARRIAIIGZ_PCIE_HIP_VER,MAXV_VER)2. Lattice Diamond 1.3 (MACHXO2, POWR, OVI_MACHXO2, OVI_POWR)

Updated Libraries

System Libraries1. The ieee_proposed library has been updated to the latest version (released in September 2010).

Verification Libraries1. Accellera's Open Verification Library (OVL) delivered with Active-HDL ($aldec/vlib/ovl) has been upgraded toversion 2.5. Version 2.5 is a bug-fixing release. For detailed information on resolved issues, see the documentationprovided by the OVL team and available in $aldec/vlib/ovl/std_ovl/docs. (SPT48790)

HDL Synthesis1. Mentor Graphics Precision RTL 2011a.612. Synopsys FPGA Synthesis F-2011.09

Implementation1. Actel Designer 9.1 SP32. Lattice Diamond 1.33. Lattice ispLEVER Classic 1.54. QuickLogic QuickWorks 2010.4.15. Xilinx ISE 13.3

New Schematic Libraries



Implementation1. Xilinx ISE 13.3 (ARTIX7, KINTEX7, VIRTEX7)

NOTES: 1. For the complete list of all the pre-compiled vendor libraries delivered with Active-HDL 9.1, refer to the Vendor-Specific Libraries chapter.2. For additional information about availability of discontinued libraries, please contact Aldec Technical Support athttp://support.aldec.com/ContactSupport/. Please note, you will be asked to register if you have not already.

Design Flow Manager

New Flowcharts

HDL Synthesis1. Altera Quartus II 10.1 Synthesis & Implementation2. Altera Quartus II 11.0 Synthesis & Implementation3. Altera Quartus II 11.1 Synthesis & Implementation (supports Quartus II 11.1 SP1) (SPT62175)4. Lattice Diamond LSE 1.15. Lattice Diamond LSE 1.26. Lattice Diamond LSE 1.37. Lattice Synthesis & Implementation in Diamond 1.1 (SPT49380, SPT49634, SPT49713)8. Lattice Synthesis & Implementation in Diamond 1.29. Lattice Synthesis & Implementation in Diamond 1.310. Lattice Synthesis & Implementation ispLEVER 8.1 (supports ispLEVER 8.1 SP1)11. Mentor Graphics LeonardoSpectrum 2010 (supports LeonardoSpectrum 2010a)12. Mentor Graphics Precision RTL 2011 Synthesis (supports Precision RTL 2011a. 61) (SPT61384)13. Synopsys Synplify/Synplify Pro/Synplify Premier/Premier with Design Planner E-2010.09 (supports FPGASynthesis E-2010.09 SP2) (SPT50545)14. Synopsys Synplify/Synplify Pro/Synplify Premier/Premier with Design Planner E-2011.03 (supports FPGASynthesis E-2011.03 SP2)15. Synopsys Synplify/Synplify Pro/Synplify Premier/Premier with Design Planner F-2011.09 (supports FPGASynthesis F-2011.09)16. Synopsys Synplify Pro E-2010.09 for Actel (supports Synplify Pro E-2010.09A-1)17. Synopsys Synplify Pro E-2011.03 for Actel (supports Synplify Pro E-2011.03A)18. Synopsys Synplify Pro D-2009.12 for Lattice (supports Synplify Pro D-2009.12LC-1)19. Synopsys Synplify Pro D-2010.03 for Lattice (supports Synplify Pro D-2010.03L)20. Synopsys Synplify Pro E-2010.09 for Lattice (supports Synplify Pro E-2010.09L-SP2 and Synplify Pro E-2011.03L)21. Xilinx ISE/WebPack 12.3 XST VHDL/Verilog22. Xilinx ISE/WebPack 12.4 XST VHDL/Verilog23. Xilinx ISE/WebPack 13.1 XST VHDL/Verilog24. Xilinx ISE/WebPack 13.2 XST VHDL/Verilog25. Xilinx ISE/WebPack 13.3 XST VHDL/Verilog

Physical Synthesis1. Xilinx PlanAhead 12.32. Xilinx PlanAhead 12.43. Xilinx PlanAhead 13.14. Xilinx PlanAhead 13.25. Xilinx PlanAhead 13.3

Implementation1. Actel Designer 9.1 (supports Designer 9.1 SPA, Designer 9.1 SPB, Designer 9.1 SP1, Designer 9.1 SP1A,Designer 9.1 SP2, and Designer 9.1 SP3)2. Altera Quartus II 10.1 (supports Quartus II 10.1 SP1)3. Altera Quartus II 11.0 (supports Quartus II 11.0 SP1)4. Altera Quartus II 11.1 (supports Quartus II 11.1 SP1) (SPT62175)5. Lattice Diamond 1.16. Lattice Diamond 1.2 (SPT60407)7. Lattice Diamond 1.38. Lattice ispLEVER 8.1 (supports ispLEVER 8.1 SP1)9. Xilinx ISE/WebPack 12.310. Xilinx ISE/WebPack 12.411. Xilinx ISE/WebPack 13.112. Xilinx ISE/WebPack 13.213. Xilinx ISE/WebPack 13.3

Updated Flowcharts

HDL Synthesis1. Mentor Graphics Precision RTL 2010 Synthesis (supports Precision RTL 2010.228, Precision RTL 2010aUpdate2.254OEM for Actel, and Precision RTL 2010a Update2.254OEM for QuickLogic)

Implementation1. Actel Designer 9.0 (supports Actel Designer 9.0 SP3A)



2. Altera Quartus II 10.0 (supports Altera Quartus II 10.0 SP1)3. Lattice ispLEVER Classic (supports Lattice ispLEVER Classic 1.4 and 1.5)4. QuickLogic QuickWorks 2010 (supports QuickWorks 2010.4.1)

Flowchart Changes and Improvements

Lattice flowchart1. The Lattice Synthesis & Implementation in Diamond 1.1 flowchart has been supplemented with the newSynthesis tool list box on the General tab of the Synthesis and Implementation Options dialog box. The newoption allows selecting the default synthesis tool that will be used during synthesis and implementation of a projectin the Lattice Diamond environment. (SPT51087)2. The Libraries tab has been added to the Lattice Diamond LSE and Lattice Synthesis & Implementation inDiamond flowcharts. The new tab allows specifying additional libraries and HDL files used during designsynthesis. (SPT61041)3. The support for the *.lpf constraint files has been added to the Synthesis & Implementation flowcharts. Whenthis type of the flowchart is selected and the file does not exist, the Design Flow Manager automatically generatesthe constraint file. (SPT60584)

Xilinx flowchart1. The flowchart allows running the IBIS model writer. The new tool can be run from the Post-Layout Tools pop-up window accessible from the Design Flow Manager. (SPT60187)2. The glbl.v file (required during timing simulation started from within the Design Flow Manager) stored in the\$aldec\dat subdirectory has been updated to the version compatible with ISE 13.1.3. The Xilinx ISE/WebPack flowcharts allow importing files with best strategy settings generated by SmartXplorer.(SPT61152)

NOTE: For additional information about availability of discontinued flowcharts, please contact Aldec Technical Supportat http://support.aldec.com/ContactSupport/. Please note, you will be asked to register if you have not already.

Design Browser

Simulation can now be initialized directly from the Files tab of the Design Browser window by selecting a singleor multiple design units and selecting the Initialize Simulation command from the context menu. The simulationunit(s) can be selected from the expandable file structure or from a list of library units displayed in the Files tabunder a library icon. Executing the command for the selected design unit(s) automatically sets the top-level.Initialization of simulation run in two separate steps, i.e. first, by selecting the top-level unit(s) and then, byselecting the Initialize Simulation command from the Simulation menu is still available. (SPT50139, SPT50743)

The Windows Explorer submenu was added to the context menu of the Files tab. By clicking on a file or a folderwith the right-mouse button and then selecting the Windows Explorer submenu, you can access the same optionsthat correspond to the selected item and are available in the context menu of Microsoft Windows Explorer.

Active-HDL remembers the user's choice entered in the Make local copy check box available in the Add Files toDesign dialog box. Once the Make local copy option has been set by the user, it will be remembered in thesubsequent Active-HDL sessions. If needed, you can always redefine your choice in the dialog box. This setting isalso included in the export/import of Active-HDL settings performed by the Preferences Manager (prefman.exe).(SPT51124)

Console

The Auto-complete functionality has been implemented. The new feature facilitates entering paths, commands andtheir parameters in the Console window. To take advantages of the new functionality, simply type in the firstletters of a command and press the Tab key. All matching commands will pop up and you will be able to selectthe desired command from the list. The Auto-complete feature also aids in choosing command arguments,defining file names (e.g. while compiling sources with the use of the acom or alog commands), changing pathswith the use of the cd macro, or specifying message identifiers to the msginfo command. (SPT45203, SPT49823,SPT50678)

An absolute file path is printed to the Console window when a file attached to the design tree is dragged and thendropped from the Files tab of the Design Browser window. (SPT61521)

File path information printed to the Console can be controlled with the use of the new Use absolute paths inmessages option available in the Preferences dialog box. When it is enabled, absolute paths are printed to theConsole. Otherwise, the file path information depends on how the files were compiled: if the absolute path wasused during compilation, it is repeated in the same form in a message; otherwise a relative path is printed. Thisoption can also be set by setting the $absolutepaths predefined variable. By default, relative paths are printed to theConsole.

HDL Editor



The view in the HDL Editor window can be zoomed in or out by using the Ctrl key and the mouse-wheel or theZoom In and Zoom Out toolbar buttons. The default zoom can be restored by holding the Ctrl key and clickingthe mouse-wheel or the Zoom to Original Size toolbar button. (SPT47503, SPT60822)

Breakpoints are toggled by double-clicking on the margin of the HDL Editor window. Previously, breakpointswere toggled by a single click, which might be inconvenient in some cases, e.g. when trying to select one orseveral lines of code. (SPT51225)

Highlighting of words and user-defined phrases in now possible. When the Enable phrases highlighting option isenabled in the HDL Editor category of the Preferences dialog box, manual selection of a word or a portion oftext causes other occurrences of this selection to be highlighted. The color of the highlighting can be customized inthe Appearance category. (SPT47504, SPT50018, SPT60823)

Error message tooltips can be enabled or disabled by using the Enable message tooltips option in the HDLEditor category of the Preferences dialog box. (SPT47405, SPT49501)

VHDL Code Browser

Active-HDL introduces a new tool dedicated to analysis of VHDL source code edited in the HDL Editor window.It allows analyzing a source file before it is compiled to a working library. The viewer is integrated with the built-in editor and follows changes introduced to a source file during design development. The structure of source code,declared libraries, packages, design units and objects, data types, interface, attributes, statements, etc. are presentedin the docked Code Browser window in the form of an expandable list. Each item displayed in this windowrepresents a corresponding VHDL construct. Clicking an item allows viewing its declaration in the edited sourcedocument.The Code Browser delivered with Active-HDL 9.1 is available in a preliminary version and any comments,suggestions, or issues encountered while analyzing VHDL code can be sent to Aldec Technical Support.

Block Diagram Editor

The terminals can be aligned. Note that in the previous versions alignment of fubs, symbols, process/alwaysblocks, and special text block was already available. (SPT45853)

Instances of design units and special text blocks (e.g. process/always blocks, signal assignments, etc.) inserted on ablock diagram can be excluded from processing. Previously, each item added to a block diagram was representedby equivalent HDL code in generated source file. In the current version, you can decide whether generated HDLcode will include additional pragmas preventing a portion of HDL code from compilation, synthesis, or collectingcoverage data. It is also possible to omit the selected design objects during generation of HDL code.The options that allow you select the type of pragma or block generation of a portion of source code are availablein the Exclude submenu of the context menu of a block diagram item. (SPT48998)

The rules of preserving the letter case for VHDL identifiers have been improved. Extended identifiers, i.e.identifiers surrounded with backslashes, are created only in those cases where it is necessary to distinguishbetween Verilog objects instantiated in VHDL code whose names differ with letter case only. (SPT48836)

The range attribute of arrays can be used for specifying the generate parameter in VHDL Generate For blocks.For example, the following declaration of the Generate For block is supported:

g0: for i in Bus'range generate.

Note that using the Generate For blocks allows matching the generated instance names with indices of connectedport slices. (SPT44990, SPT49420, SPT49060)

The new Synchronize with Waveform option has been implemented. When the option is enabled, it is possible tosynchronize the view in the Block Diagram Editor window showing highlighted diagram objects (terminals, wires,buses, ports of fubs and symbols, etc.) with the active view of the Accelerated Waveform Viewer and observe thehistory of values for the objects selected on a block diagram. When the synchronization is turned on, theframework is split horizontally and the highlighted diagram objects and corresponding waveform signals arepresented in separate views. An individual block diagram sheet is synchronized with a corresponding waveformdocument. The synchronization between the Block Diagram Editor and the Accelerated Waveform Viewer can beturned on/off from the BDE Edit toolbar. (SPT48827)

An action of the right-mouse button can be customized in the Preferences dialog box. In the previous versions,clicking the right-mouse button started a process of drawing a fub. Since the current version, the setting of theRight-click action option in the Block Diagram Editor category allows selecting between drawing a fub andpanning a block diagram. (SPT45900)

State Diagram Editor

Encoding of a state machine can be saved to or loaded from a file. You can specify a text file (*.csv) with stateencoding data by using the Save/Load FSM Encoding options from the FSM menu, the Save/Load buttons in theGeneral tab of the Machine Properties dialog box, or the States tab of the View/Sort Objects window.



(SPT45846)

Particular bits selected from complex type ports (including vector types in VHDL and Verilog, and record types inVHDL) can be assigned a special purpose, i.e. Clock, Clock Enable, or Reset. This can be realized with theimproved Port Properties dialog box, which allows using the dotted and indexed notation in the Clock, ClockEnable, and Reset text boxes. (In case of the Reset signal, this can also be a range of bits.) Such declared signalscan then be assigned their special function in the Machine Properties dialog box. (SPT46883, SPT50549)

The Custom text box was introduced to the Reset tab of the Machine Properties dialog box. The text box hasreplaced a pop-up window that was available under the Advanced button. Along with this change, the optionsavailable in the tab were rearranged for better visibility and accessibility.

Transcription of state machine ports and parameters into Verilog code can be performed in accordance to the IEEEStd 1364-1995 or IEEE Std 1364-2001 standard. Previously, such ports could be transcribed in accordance to theIEEE Std 1364-1995 standard only. (SPT48043)

Error reporting has been improved in case when an incorrect generation style is selected for a finite state machine.(SPT48255)

Accelerated Waveform Viewer

The following new options that improve handling of waveform objects and allow optimizing performance of theAccelerated Waveform Viewer have been added to the Waveform Preferences dialog box:

Preserve signals when simulation is initialized - when enabled, previously added signals are not removedfrom the Accelerated Waveform Viewer at the initialization of simulation. (SPT47907, SPT48367)

Trace signals when loading AWC document - for AWC files saved with the AWC save format allows usingAWC with any ASDB option enabled, automatically traces relevant signals while opening WaveformConfiguration files (*.awc). (SPT47907, SPT48367)

Reload waveform while zooming and scrolling when simulation is running - if this option is enabled, thewaveform viewer automatically refreshes the view during simulation while zooming or scrolling waveforms. Bydefault, this option is disabled to prevent from frequent waveform reloading and decreasing performance of theviewer. (SPT50028, SPT50029)

The Clicking on the column header sorts signals option has been moved to the Columns tab.

Do not ask to create a copy of simulation database when saving AWC file and Create a copy of simulationdatabase - these two options were introduced along with the removal of the Create copy of SimulationDatabase option from the Save as dialog box.

The AWC documents originated from other simulations can be connected to running simulation. This can beaccomplished by using the new command Connect To Simulator that automatically traces all relevant signals andlinks the AWC file to the current simulation database. (SPT47909)

The Create copy of Simulation Database option has been removed from the Save as window. Instead, a dialogbox pops up when saving an AWC file for the first time, asking if a copy of the simulation database should becreated, or if the AWC file should be linked to an existing one. In the dialog box, you can make your selection adefault action to be executed without a prompt. This setting can be restored to its original state in the WaveformPreferences dialog box.

The stimulators can be saved to a file and then reused in a subsequent simulation session or another design.Stimuli defined manually in the Stimulators dialog box are saved automatically by Active-HDL to thestimulators.set file created in a design directory ($dsn). Stimulators are defined and grouped in sets, i.e. each set ofstimulators can contain unique stimuli definitions applied to user-defined signals (same or different). The sets canbe freely modified, i.e. they can be created from scratch, updated or removed. When a Standard WaveformViewer file (*.awf) containing stimulators is used, stimuli can be imported as a separate set and saved tostimulators.set with other stimulus definitions. (SPT47035)

The Accelerated Waveform Viewer is able to represent vectors as fixed-point numbers. This can be achieved byspecifying the position of the binary point in a vector, in the Binary point spin box of the Signal Propertiesdialog box. The number specified in the Binary point spin box determines the number of least significant bits thatwill be considered a fractional part of the vector. By default, the position of the binary point is set to 0, i.e. thebinary point is located to the right of the least significant bit. (SPT49716)

Two new options were introduced to the pop-up menu of the waveform objects that allow you to quickly changetheir representation radix and notation without the need to access the Signal Properties dialog box. The optionsare available as the Radix and Notation submenus in which you can select the desired representation format. Anadditional advantage is that the new options can be applied to objects that contain signals of heterogeneous types,i.e. virtual objects or complex objects coming from source code, e.g. of a record type, in which case they areapplied recursively through the structure of a selected object, thus changing the representation format of all itscomponents. (SPT49732)

The support for virtual objects has been enhanced. The following object properties can be changed in the SignalProperties dialog box: radix, notation, order of bits, binary point, analog representation, from-to analog range,auto-calculate range. The only restriction for the options to be available is that only scalar signals of the same type



can be members of the virtual objects. (SPT45380, SPT46421, SPT48146, SPT48154, SPT48702, SPT50598)

Signal aliases have been implemented. This functionality, known from the Standard Waveform Viewer and theMemory Viewer, allows displaying real values of signals as easy-to-recognize design mnemonics. You can defineand assign user-defined aliases to waveform objects by using the Use Alias option in the Signal Properties dialogbox or an appropriate command in the Console window. Refer to the Scripts section for additional information.(SPT45262, SPT49439, SPT61050)

The time units displayed in a tooltip of a corresponding active timing cursor can be changed by selecting thedesired unit from the Time Unit submenu available in the context menu of the Cursors View pane, i.e. the lowerpart of the Waveform Viewer window presenting the names of the timing cursors. (SPT22574)

Double-clicking a tooltip displayed in the context menu of the Cursors View pane presenting the position of atiming cursor switches it to the edit mode. In this mode, you can type in precisely a new time value to which thecursor will be moved.

The Value Matching edit box was added to the Compare Selected Signals and Compare Waveforms dialogboxes. The option corresponds to the new -value_matching argument of the asdbcompare macro command and itallows specifying which signal values will be considered identical in the comparison process. In the new edit box,the values should be entered similarly as in the syntax of the asdbcompare command. For additional information,refer to the Scripts section. (SPT50931)

A signal can be added to the Waveform Viewer multiple times. Note, however, that all instances of the signalshare the same properties (radix, notation, color, etc.) but the measurements are always drawn for individuallyselected signals. The behavior of members of virtual objects remains unchanged, i.e. their properties are controlledindividually. (SPT45803, SPT49438)

The default display settings (font size, row height, etc.) of the Signal Grid and Waveform View pane have beenchanged in order to improve legibility of objects names and values. The size of the font in the List View has alsobeen increased. (SPT61101)

Scripts

The following changes have been introduced to the Active-HDL macro commands:

The command output redirected to a file, e.g. do runme.do > report.txt, no longer contains the message prefixdefined by the $messageprefix variable (by default, its value is: #).

The acom command allows specifying the -93, -2002, or -2008 arguments multiple times. Additionally, eachargument can precede one source file or it can be followed by a number of sources. (SPT50344)

The -check_sensitivity_list argument of the acom command used to check sensitivity lists of VHDL processes isno longer supported. It is recommended to use the Aldec ALINT verification tool to verify source code againstpotential coding errors. (SPT60998)

The -f argument of the acom command can now be specified in the command line multiple times. (SPT50349)

The -xevd argument has been added to the syntax of the acom and alog commands. The new argument allowsdisabling extended vacuous evaluations for corresponding implication operators.

The -na argument of the alog command can be assigned a value specifying the types of assertions/covers that willbe excluded from processing during compilation and simulation. The new functionality of the command allowsdisabling all (-na all) or selected assertion/cover types, i.e. OVA or PSL assertions/covers written as comment inVerilog source code (-na emb), OVA assertions/covers (-na ova), PSL assertions/covers (-na psl), orSystemVerilog assertions/covers (-na sva). Previously, the -na argument could be used to disable all definedassertions/covers. The corresponding GUI settings are also available in the Preferences, Design Settings, and FileProperties dialog boxes. (SPT60660)

The alias, aliaspar, aliasswitch commands are supported in the Tcl and Compatibility modes.

Commands for manipulating signal aliases have been implemented. The commands allow creating (aliascreate),removing (aliasremove), saving to a file (aliassave), loading from a file (aliasload), or printing (aliasprint) theinformation about aliases. With the new commands you can automate the control over signal aliases without theneed to use the GUI tools.

A new command for controlling signal aliases in the Waveform Viewer has been implemented. The aliaswavecommand (or wavealias) allows assigning an alias to a particular signal or to a group of signals in a selecteddesign region. The command also allows you to remove previously defined signal aliases. (SPT15692, SPT16370)

The -alias argument has been added to the syntax of the add wave macro command. The new argument allowsassigning an alias to a signal when adding the signal to the waveform viewer. (SPT15692, SPT16370)

The -f argument has been added to the syntax of the asdbcompare command. Instead of passingindividual arguments in the command line, -f allows defining a text file containing a list of all arguments to pass.

The asdbcompare command allows comparing not only complete simulation database files (*.asdb) but alsoselected design objects stored in the databases. The objects of the same name in both databases can be specifiedwith the new -signal argument. It is also possible to compare two objects by using the -signals argument. Both the



arguments can be passed multiple times in the command line. (SPT50403)

The functionality of the asdbman command has been changed. The command allows creating a new database file(*.asdb) from an existing one by filtering out the specified data (asdbman filter), merging several databases into asingle file (asdbman merge), or acquiring information about an existing database and its content (asdbman info).

The asdbcompare and wavecompare macro commands have been supplemented with the -value_matchingargument. With this argument you can specify which signal values will be considered identical in the comparisonprocess. For example, when executed with the argument -value_matching 0=L-:L=0-:-=0L, the commands willnot report differences between the 0, L and - signal values. An equivalent for this argument has also beenimplemented in the GUI. For the additional information, refer to the Waveform Viewer section. (SPT49045,SPT50931)

New arguments were added to the syntax of the asdbman filter command. The arguments allow specifying thekind of ports or signals to be included in the resulting database (-in, -inout, -internal, -out, and -ports), orspecifying the list of signals by means of an external file (-signal_list).

The asim command can assign values to 2-state parameter constants in SystemVerilog units. Previously, forSystemVerilog, only the 4-state parameter constants could be controlled. To assign the values, specify the -g or -Garguments in the syntax of this command.

The close and closedocument commands used with the -all argument close not only the windows docked in theapplication framework, but also the undocked document windows, opened from Active-HDL. (SPT50421)

Three arguments were added to the syntax of the asim command: -acdb, -acdb_cov, and -acdb_file. Thearguments control collecting the coverage data to the ACDB database.

The -pac_nested_depth argument has been added to the syntax of the asim command. When the new argument isused, the Source column in the Path Coverage report will present additional lines of source code showingconditional expressions coming from parent nesting levels that implicitly form a program path. Presentingadditional code fragments may make path analysis easier especially in case of composite paths formed by nestedstatements. The new argument is available in the Advanced mode.

The -sv_liblist and the -sv_root arguments have been implemented in the syntax of the asim command. -sv_liblistspecifies a location of a file that contains a list of DPI libraries to be loaded by the simulator. The -sv_rootargument defines the location where the simulator should start looking for library files set with the -sv_liblist or -sv_lib arguments.

The averilog command is no longer supported.

The awfhierarchy command has been implemented. The new command allows updating hierarchical paths ofobjects stored in the Standard Waveform Viewer files coming from previous versions and used in Active-HDL9.1. For additional information, refer to the Hierarchical Names Specification section.

The bc and bcd commands have been added. The former allows setting breakpoints on OVA, PSL, andSystemVerilog covers while the latter deletes breakpoints previously set by using the bc command.

The bde2code and fsm2code commands have been implemented. The commands are equivalent to the GenerateHDL Code option from the Diagram or FSM menu and they can be used to generate HDL code from a block orstate diagram file (*.bde or *.asf) to the $dsn\Compile subfolder of an active design. (SPT60103)

The cursor command allows controlling the time unit with which the timing cursors are displayed in theAccelerated Waveform Viewer. This has been achieved by introducing the new -unit argument. The samefunctionality can also be controlled in the timing cursor context menu; see the Accelerated Waveform Viewersection for details. (SPT22574)

The enablebc and disablebc commands have been introduced. The new commands allow enabling and disablingcover breakpoints.

Contents of the error message returned by the env command in case of receiving an incorrect hierarchical pathwere refined. The improved message contains path information, which facilitates identifying the source of theproblem. (SPT60521)

The exist command has been enhanced. The command allows checking not only if a file exists in the specifiedlocation (exist -file) but additionally if a variable is defined (exist -var). (SPT50744)

The -strobe_time argument has been added to the syntax of the expwave command. The argument allowsspecifying time intervals between subsequent dumps of signal values stored in the Standard Waveform File(*.awf). (SPT50511)

The measurement command has been enhanced. Now, it allows displaying not only statistics for measurementsinserted to the Accelerated Waveform Viewer window (measurement print) but also inserting and deletingmeasurements (measurement set and measurement delete).

The following new commands that allow importing third-party projects or simulation scripts into Active-HDLhave been implemented: importcoreconsole, importedk, importise, importquartus, importqsys, importsopc, andimportsynplify. All the commands are equivalent to the respective import options available in the File | Importmenu.

The onerror command is now supported in the Tcl and Compatibility modes.



The quietly command is ignored in the Tcl and Compatibility modes. (SPT60312)

The scripterconf command allows resetting the environment of the command interpreter in the selected workingmode, e.g. only in the Tcl mode. Previously, the use of the -reset argument caused that the default environmentand interpreter settings were set simultaneously in all the working modes. The current syntax of the command is asfollows:

scripterconf [-reset] [-do | -tcl | -msim]

(SPT50448)

The transcript command is synchronized with the Command transcript on option in the Console category of thePreferences dialog box. (SPT46257)

The vencrypt command is no longer supported.

The vsimsado macro command was updated so that the scripts converted by the command were compatible withthe most recent versions of Riviera-PRO. (SPT47570)

The wave command can be used to add signal slices to the Accelerated Waveform Viewer. A slice can be selectedfrom arrays of any dimensions. For example, a virtual group for the TR multi-dimensional array can be created byusing the wave command:

type arr is array (1 to 5) of integer;type multiarr is array (1 to 3) of arr;variable TR : multiarr;wave -varray "REM" /testbench/SYS_CLK_G/TR(2:1)(3:4)

Previously, a slice could only be used for vectors. (SPT49739)

The performance of adding multiple objects to the Waveform Viewer by using the wave -rec * syntax has beenimproved. During such operations less memory is allocated and the execution is faster than in the previous release.Note, however, that this change influences the order in which signals are added to the waveform.

The following changes have been introduced to the predefined Active-HDL variables:

The $exitonerror variable is supported. When it is set to 1 in the startup.do macro, it makes Active-HDL exit whena macro specified as a command line argument fails. Setting the variable to 1 is useful in command-lineprocessing when failed macros should not block execution of remaining scripts.

The new $tclerrornotboolean predefined variable has been added. The variable influences the execution of DOmacro commands in the Tcl/Compatibility mode or Tcl scripts containing the acom, alog, asim, buildc, or edfcompcommands. When the variable is set to 0 (or is not specified yet), the command returns the execution status (0when failed and 1 if succeeded) but a macro/script is not terminated. Otherwise, if the variable is set to 1, themacro execution is terminated with an error or the error can be handled with the use of the onerror or catchcommands.

IP Protection

The vencrypt utility has been deprecated and removed from the default installation of Active-HDL. Althoughencrypting Verilog source files with vencrypt is no longer possible, the compiler (alog) will still be able to compilealready encrypted files. Note that Aldec provides another tool for encrypting HDL source files - protectip.

The protectip encryption tool is delivered along with the Active-HDL installation as a stand-alone program(protectip.exe). The program allows encrypting source files prepared according to the requirements outlined inthe latest revisions of the VHDL and Verilog standards (IEEE Std 1076-2008 and IEEE Std 1364-2005). Theexecutable file stored in the $aldec\bin subdirectory has replaced the protectip.pl script that was available onrequest in the previous versions of Active-HDL.

Active-HDL allows compiling source code encrypted by other vendors. To allow the compiler to decrypt suchsource files, prior to the encryption, the ALDEC public key (specified in the Active-HDL documentation) must beinserted into IP source code. For other possible methods of encryption with the ALDEC public key, refer to atechnical documentation provided by a vendor of an encryption tool.

The OpenSSL utility ($aldec\bin\openssl.exe) delivered as part of the IP protection package has been updated toversion 1.0.0c. (SPT49387)

Active-HDL Interfaces and Wizards

The following changes and improvements have been made to the built-in Active-HDL DSP interfaces:

Interface to Simulink/MATLAB1. The version of P-code used for setup.p installation script in the MATLAB environment was upgraded to versionR2007b as the previous format was announced obsolete in R2010b and will not be supported in future MATLABversions. Consequently, MATLAB versions earlier than R2007b are no longer supported by the installation script



delivered with Active-HDL. If you require support for older MATLAB version contact Aldec Support.(SPT49213).

The following changes and improvements have been made to the import of third-party projects (File | Import):

Active-HDL allows importing simulation scripts of Altera Qsys. The import process can be initialized by using thenew Altera Qsys Simulation Script option.

The Altera Quartus II Project option allows importing projects coming from Quartus II ver. 10.1 SP1 and 11.0.

The Xilinx ISE Project option allows importing projects coming from versions 13.1 and 13.2 of Xilinx ISE.

The following changes and improvements have been made to the built-in source revision control interface:

Perforce1. The SCC interface for Perforce has been improved and now it can be also used when Active-HDL is installedon a workstation with 64-bit. version of Windows 7. (SPT51174)2. The new proxy for the SCC interface has been implemented that allows using the recent versions of Perforce.(SPT48713)

Team Foundation Server1. The Team Foundation Server 2010 source revision control system is supported. Relevant information has beenadded to the Source Revision Control topic of the Active-HDL Help | Active-HDL Tools chapter in the on-linedocumentation. (SPT50336, SPT51072)

TortoiseCVS / TortoiseSVN1. Since the TortoiseCVS and TortoiseSVN applications do not provide the SCC API, they cannot be used directlyvia the built-in Source Revision Control interface of Active-HDL. Instead, they can be accessed only from thecontext menu of the MS Windows Explorer. To provide access to these tools directly from Active-HDL, theWindows Explorer option has been added to the pop-up menu of the Design Browser. This option provides thelist of commands that are available in the context menu of the MS Windows Explorer. For additional information,refer to the Design Browser section. (SPT50745)

The following changes and improvements have been made to the built-in Active-HDL simulation interfaces:

VHPI Interface1. The vhpiLanguageP property (an extension to the IEEE Std 1076-2008 standard) has been implemented in theVHPI interface. This property allows identifying the source language of an object whose handle was passed as anargument to the vhpi_get function.

DPI Interface1. The SystemVerilog chandle type is supported in the DPI interface.2. Exported DPI tasks consuming time are now supported. You could, for example, define the following task:

export "DPI-C" task t1;task t1;#100 $display ("Task completed.");endtask

The task can be then called from C/C++ source code. By the time the task completes and control returns to C/C++,the time in the simulator will have advanced by 100 time units. Note that an exported task can use event controlstatements allowing you to synchronize execution of C/C++ code with events in a simulated model.3. DPI open arrays are supported. Open arrays can be used as formal arguments of imported tasks and functions,for example:

import "DPI-C" task put_array(inout int open_arr[]);

The actual argument for such task or function can be an array with arbitrary dimensions. For the put_array task inthe listing above, it could be an array declared as: int a[100];, int a[0:7];, int a[15:8];, etc.

On the C/C++ side, an open array is accessible as a variable of the svOpenArrayHandle type. A number offunctions is available to query the array, for example:

int left = svLeft(hnd, 1);int right = svRight(hnd, 1);int low = svLow(hnd, 1);int high = svHigh(hnd, 1);int inc = svIncrement(hnd, 1);int size = svSize(hnd, 1);int length = svLength(hnd, 1);int dim = svDimensions(hnd);

For a complete list of functions, see the \PLI\Include\svdpi.h header file. The header contains a brief description ofeach function.

The following improvements have been made to the Active-HDL wizards:

Export to PDF Wizard1. Headers and footers of design documentation can be freely customized. You can define your own templates forheaders and footers in which you can use predefined or custom variables that will be translated to appropriateportions of a text at the moment of rendering the PDF document. Then, in the new Headers and Footers



category, you can specify different headers and footers for different sections of the PDF documentation. Havingprepared the template files for headers and footers, you can reuse them in various designs with a few clicks of amouse button. (SPT45849)2. Internal links in PDF files generated for the Active-HDL designs or workspaces can be supplemented withadditional information that refers you to names and page numbers of topics which they point to. By using thisfeature, you will significantly improve legibility of the printed copies of design documentation. (SPT45850)

Export Waveforms WizardThe Export to CTF page of the Wizard has been refined and supplemented with new options. Now, you canspecify the radix and notation for objects exported to a custom text file (*.ctf). In the Strobe group of options, youcan define the values of a specified signal at which the exported data will be sampled. (SPT20008, SPT47293)

New Source File WizardThe New Source File Wizard allows specifying signedness of ports of the generated VHDL or Verilog designentities. This feature also applies to block diagram and state diagram entities targeted to those HDL languages.(SPT46837)

Installation

The installation program of Active-HDL has been upgraded to InstallShield ver.2011. (SPT49745)

The code sign certificate has been implemented. When the setup.exe file is launched, a message window informingthat the file was delivered by a trusted publisher is displayed. This allows verifying whether a copy of Active-HDL has been altered since it was signed by Aldec, Inc. (SPT60086)

Documentation

The ACDB API Reference Guide has been added to the Active-HDL on-line documentation. The new referenceguide is available in Active-HDL Reference Guides section of the References page.

The VSimSA Standalone Simulation Environment Manual (vsimsa.chm) has been removed from the installation ofActive-HDL. The help topics dedicated to the VSimSA environment and the batch mode compilation andsimulation have been moved to respective sections of the Using Active-HDL chapter in the Active-HDL UserGuide (avhdl.chm).

The descriptions of the Active-HDL and VSimSA macro commands have been merged and now they are availablein the Active-HDL Macro Language chapter in the Active-HDL User Guide.

Others

Compilation status information is no longer stored in the compile.cfg file. Instead, this information is saved to aseparate file (*.wsp) which is stored in the local design directory and excluded from the source control operations.This solution prevents propagating compilation status information between different machines working on thesame design resources. (SPT49334)

Verilog and VHDL protected source files (*.vhdp and *.vp) are recognized within the Active-HDL environment asHDL files rather than external files. This change results with highlighting the syntax of such files, automaticallyincluding them in the design compilation, etc. (SPT48631)

The Print Design Files and Print Workspace options allow printing design files on any of the printers installedto the operating system. Previously, only the default system printer was available for these options. (SPT15450,SPT49831)

The Tools and External HDL Editors categories of the Preferences dialog box were reorganized. The categoriesare now called User Tools and File Tools correspondingly and can be found in the Tools section. Additionally,the application area of the user-defined tools has been extended. For more information, refer to the Active-HDLProduct Help (Help | Product Help).

The Tools | Windows category of the Preferences dialog box was updated: the Accelerated Waveform Vieweroption was added and the Waveform Editor option was renamed to Standard Waveform Editor so that thebehavior of both windows could be controlled. (SPT51156)

The Active-HDL Preferences Manager (prefman.exe) supports export/import of settings specified for EDA toolsdefined in the Integrated Tools category of the Preferences dialog box. (SPT49633)

Problems Corrected in Version 9.1

Licensing



A change in a mechanism used to report an insufficient number of licenses for Expression or Path Coverage wasintroduced. Previously, a fatal error was reported in the Console and a message box was displayed, whichterminated simulation. After the change, no message box is displayed in the GUI and an error is reported (insteadof a fatal error) in the Console, which does not terminate execution of a simulation macro. (SPT62054)

A defect in the Diagnose program (diagnose.exe) causing an error while attempting to verify a license stored in alocal license.dat file was resolved. (SPT62161)

Previously, Active-HDL and VSimSA reported an incorrect license error message when a maximum number ofusers was reached. Now, this issue is revised. (SPT49193)

In the previous version, the SecureIP license feature was not released after a simulation session was terminated.Now, the issue is resolved. (SPT49629)

The license-related error messages contain information about the design region where unsupported constructs wereused. (SPT50793)

VHDL Compilation and Simulation

An issue was fixed that generated an improper compilation error in case of assignment of an aggregate with thenested others choice to the record with another record used as field. (SPT61764)

A defect was revised that caused an improper compilation error that appeared in certain circumstances if aconstant in a package was initialized by a function using another constant as a parameter. (SPT61872)

An issue with simulation performance in case when large variables declared inside procedures were used wasresolved. (SPT50252)

An issue that caused an elaboration failure in case of using external names of objects instantiated with for, if, orcase generate statements was fixed. (SPT48911, SPT50635)

Previously, passing arguments to the standalone VHDL compiler (vcom.exe) through a text file was not possible.Now, the issue is corrected. (SPT49958)

Incorrect results were returned by the array 'RANGE attribute. This issue was resolved. (SPT49756)

In the previous versions, the Verilog compiler was used to compile PSL files in VHDL projects. In the currentversion, the VHDL compiler is invoked. (SPT60130)

The following defects resulting in occurrence of compiler or simulator errors were fixed: SPT49294, SPT49571,SPT49765, SPT49762, SPT50255, SPT50894, SPT50956, SPT51019, SPT51065, SPT60431, SPT60472,SPT60573, SPT60608, SPT60875, SPT61029, SPT61423, SPT61505, SPT61594, SPT61814, SPT61947,SPT62300.

Verilog/SystemVerilog Compilation and Simulation

An issue causing that wrong simulation results were produced for designs using unnamed generate blocks wasresolved. (SPT49749)

An issue with continuous assignment inside two mutually exclusive branches of a conditional generate constructwas corrected. (SPT21050)

A defect in a mechanism that incorrectly resolved hierarchical references to parameters inside generate blocks wasfixed. (SPT51171, SPT51172)

Contents of the VCP2905 warning message have been refined. (The warning is printed when one of case blockconditions may render values that duplicate another condition in the same case block.) (SPT60530)

The following defects resulting in occurrence of compiler or simulator errors were fixed: SPT49455, SPT49527,SPT49543, SPT49657, SPT50830, SPT50924, SPT51027, SPT51154, SPT60886, SPT61779, SPT61213.

Mixed-language Simulation

An issue was resolved that caused that the simulator running in the SLP mode produced incorrect results for aVHDL design instantiating a SecureIP Verilog module. (SPT51063)

SystemC Compilation and Simulation

Previously, when a design path contained a space character, building SystemC applications resulted in compilationfailures. Now, the issue is revised. (SPT50628)

C/HDL Debugging

In previous versions, breakpoints did not stop simulation if they were set in encrypted source code. This issue isresolved. (SPT50926, SPT51165)

Design Coverage

Merging Toggle Coverage results did not work in the previous version. This issue was resolved. (SPT62019)

The use of the Coverage Merge option prevented the avhdl.exe process from closing and releasing resources after



Active-HDL was closed. This issue was corrected.

Design Flow Manager

Previously, an issue in the Xilinx ISE 4.x flowchart blocked initialization of timing simulation. This defect wascorrected. (SPT62040)

Several defects in the Xilinx ISE 7.x/11.x/13.2 flowcharts blocking optional flowchart tools (e.g. SmartXplorer,ChipScope) and proper implementation process were resolved.

An issue with running the Synopsys Synplify Pro D-2010.03 for Lattice flowchart when the Lattice ispLEVER 8.1implementation tool is selected has been corrected. (SPT50780)

An issue preventing to employ the Lattice Diamond LSE 1.1 as the implementation tool has been fixed.(SPT51086)

An issue causing an error in the Tcl engine when running a script generated by using the Generate Synth. andImpl. Script option of the Synplify D-2010.03 flowchart was revised.

An issue with assigning pins during implementation executed with the use of a Tcl script generated by using theGenerate implementation script option in the Altera Quartus II flowcharts was revised. (SPT48993)

A defect that caused that preparing files to a synthesis took a very long time in some certain circumstances hasbeen corrected. The problem occurred only if there were many files synthesized as a macro and if the Add sourcesfor hdlMacro components to synthesis option was selected on the Libraries tab of the Synthesis Option dialogbox. (SPT61601)

HDL Editor

Previously, the Print Preview option did not preserve the settings for the margin specified in the Page Setupwindow once a text document was closed and then reopened. Now, this issue is revised. (SPT50658)

An issue with displaying the last character of a comment was corrected. (SPT48315)

In very specific circumstances, using the Outdent option in the HDL Editor might result in deleting a line of code.This issue was corrected. (SPT49139)

A defect that caused that an undocked HDL Editor window disappeared from the Windows taskbar when the HDLEditor window was blocked above other windows with the Stay on top option was fixed. (SPT61619)

An issue causing an application error while adding/removing breakpoints or moving splitters was fixed.(SPT61774)

Block Diagram Editor

Previously, the probes displayed no signal values during simulation initialized in the post-simulation debug mode.This issue was revised. (SPT62177)

The Synthesize option available in the Generics tab of the Symbol Properties dialog box did not insert thesynopsys translate_on/off pragmas correctly if components of the unisim or unimacro library were instantiated ona block diagram. The issue was revised. (SPT61877)

An issue with generating VHDL code from block diagrams created in older versions of Active-HDL andcontaining declarations of generics defined in the special text blocks was revised. (SPT49362)

In specific circumstances, VHDL code generated for generic declarations could contain a redundant semicolon.The issue was corrected. (SPT47438)

An issue with code generation in case when an initial value for a generic contained multiple Don't care (-)characters was resolved.

In the previous versions, assigning synthesis attributes to pins or terminals of Verilog modules worked incorrectly.This version of Active-HDL resolves this issue. (SPT51250)

There was an issue resulting with incorrect VHDL code being generated for bus ports whose left-hand or right-hand indices were declared on the block diagram by using a minus (-) operator, e.g. PORT(INDEX-1:0). The issuemight occur when a top-down design strategy was followed, i.e. first the fub was drawn on the block diagram withsuch ports, and later on VHDL code was generated for that fub. This issue was resolved. (SPT50217, SPT50418)

Attempts to place SystemC modules from the Symbols Toolbox on a block diagram resulted in application crash.The issue was resolved. (SPT61002)

The following defects resulting in occurrence of an application error were fixed: SPT49386, SPT49540.

State Diagram Editor

The Trace Over Transition option did not work. This issue was corrected. (SPT61873)

Missing VHDL data types in the Port Properties dialog box were restored. (SPT61955, SPT62016, SPT62100,SPT62101)



An issue causing an incorrect generation of Verilog source code for state machines with output bus ports of aregistered type was corrected. (SPT62286)

Previously, when the ENUM_ENCODING type attributes without text concatenation (VHDL only) optionwas checked and Xilinx XST was selected in the Code Generation Settings dialog box, the State Diagram Editorissued an error reporting too many characters in a line of VHDL source code generated from a state diagramdocument. Now, the error is changed to a warning and the option inserting a synthesis attribute can be usedproperly. (SPT51209)

An issue was corrected that might obstruct opening state diagram files containing embedded bitmap images.(SPT47432)

Active-HDL Interfaces and Wizards

An issue in the Code2Graphics converter was revised that caused an application error while converting Verilogcode to a state diagram document.

The Code2Graphics converter incorrectly interpreted in source code the parameters declared with a rangespecification and converted them as parameters of a state machine instead of the values of a machine stateregister. This defect was corrected.

A defect causing an internal error during conversion of Verilog source code was corrected. (SPT49527)

An issue resulting in occurrence of an error while creating a subsystem library for System Generator was fixed.

A defect causing a co-simulation interface to Simulink to hang every two simulation runs was revised.(SPT50526)

Previously, modifying a Simulink model during co-simulation, e.g. by adding an HDL Black-Box or the SystemGenerator Black-Box module to a block diagram might cause the co-simulation interface to be frozen. Now, theissue is resolved. (SPT50920)

An issue that prevented from successful co-simulation finish in case of specific diagrams instantiatingcombinatorial HDL black-boxes was revised. (SPT50543)

An issue where the Code2Graphics Conversion Wizard did not convert a specific file was resolved. (SPT49483)

Standard Waveform Viewer

The setting of a decimal radix did not work properly. The issue was resolved.

Accelerated Waveform Viewer

An issue causing an application error while adding signals to the waveform viewer in case a simulation database(*.asdb) was located on a network drive was corrected. (SPT50588)

A defect causing an application error while adding signals to the waveform viewer that was first undocked andthen docked was resolved. (SPT60466)

A defect was fixed that caused that each add list command used after the wave command opened a new listwindow when the Tcl or the Compatibility mode was in use. (SPT61553)

An issue causing an application error while expanding virtual object containing an array of records was corrected.(SPT61637)

An issue with the use of the left/right buttons on mouse-scroll wheel was corrected. (SPT49081)

Previously, when a simulation database was generated on a network drive, the following error could occur whilesignals were added to the waveform:

ASDB: ASDB server error (Unknown ASDB server error).ASDB: No more events will be recorded. ASDB file may be damaged.

Now, this issue is resolved. (SPT49358)

An issue with forcing signals presented in a waveform in case a simulation database was located on a networkdrive was resolved. (SPT49728)

In previous versions, user-defined colors assigned to named-row objects were set to defaults when design fileswere recompiled and a simulation session was restarted. Now, the issue is corrected. (SPT50984)

Console

An issue with the Clear log file option in the Preferences dialog box being ignored was corrected. The issueresulted in console log file (console.log) being cleared, regardless of the setting of this option. (SPT49566)

Scripts

The performance of the addfile command has been improved. (SPT50433)

An issue with setting an SDF file with the designsdffile command has been resolved. The location other thandefault, i.e. different than the design folder can be chosen. (SPT60713)



An issue with filtering the results returned by the find command by port directions was fixed. (SPT50581)

The examine command returned incorrect values of vectors in the post-simulation debug mode. The issue wascorrected.

Previously, the scripterconf command executed from a macro run in the Do mode returned an incorrect messageinforming about a newly set working mode. Now, the message is presented correctly.

A defect in the scripterconf command executed from Tcl scripts was revised. (SPT49256)

An issue was corrected where the working mode of the command interpreter was not changed when requested bythe scripterconf command. This issue might occur when the command was called from a script file that was passedas a command line argument to Active-HDL. (SPT49256)

An issue with parsing file name arguments enclosed in the quotation marks has been resolved. (SPT50728,SPT60483)

Documentation

The missing description of the `ifdef _VCP compiler directive was added to the Compiler Directives topic of theActive-HDL Help | Using Active-HDL | Compilation | Verilog Compilation chapter in the on-line documentation.(SPT46092)

The list of the Source Revision Control systems supported by Active-HDL was updated in the on-linedocumentation. (SPT50336)

Information about compilation of VHDL files containing embedded PSL code was updated. (SPT47824)

The description of the VCP2905 warning message was added to the Message Reference Guide. The descriptioncan also be accessed from the Console, by using the msginfo command. (SPT50902)

Others

An issue was revised that caused that the Merge Design Source Files option did not work. (SPT62095)

The problem concerning

Active-HDL 9.1 Student Edition Release Notes

Documents

Transcript of Active-HDL 9.1 Student Edition Release Notes