A TCP/IP Based Multi-Device Programming Circuit

Department of Computer Science and Engineering

Applied Research Laboratory

A TCP/IP Based Multi-Device Programming Circuit

David V. Schuehler – Harvey Ku – John Lockwood

http://www.arl.wustl.edu/arl/projects/fpx



Goals

• Develop an efficient mechanism for programming multiple devices

• Program devices with identical content

• Allow devices to be placed throughout the Internet

• Support a hardware-based solution– No microprocessor or soft core



Solution

PCPCPCPCInternet

PCPCPCPC

ReconfigurableDevice 1

End Point



TCP/IPdata flow

• A hardware circuit which extracts device configuration information from TCP/IP data flow



System Configuration

• Programming Station– Transmits configuration file

• End Station– Terminates TCP/IP connection– Acts as data sink

• One or More Target Devices– Contains programmer circuit & target component

• Network Connectivity– IP route from programmer to each device and end station



Development Platform FPX Module

OscillatorsStatic Ram

NID (XCV600E)

RAD (XCV2000E)

PROM



FPX Internal Structure

SRAM

EC

Mo

du

le

EC

NID

Switch LineCard

Mo

du

le

RAD

VC VC

VCVC

RAD

Program

SDRAM SDRAM

Data Data

SRAM

Data

SRAM

Data

RAD: Reprogrammable Application Device

•Xilinx XCV2000E FPGA

•External SRAM/SDRAM

•Reprogrammable

NID: Network Interface Device

•XCV600E FPGA

•Controls FPX

•Programs RAD

•Forwards traffic



Programmer Circuit Components

ATM Cell Wrapper

Multi-Device Programmer

TCP Splitter

AAL5 Frame Wrapper

IP Wrapper

IP frames

Byt

e S

trea

m

IP frames

Programming Data



Testing Configuration

RAD

NID

RAD

NID

Programmer FPX Target FPX

TCP-FormattedData

Outgoing TCP-Formatted Data(to next device)

ReconfigurationBitstream

Field ProgrammableGate Array

Programmer

TCPSplitter

IP WrapperFrame WrapperCell Wrapper



Washington UniversityGigabit Switch Environment

StackedFPX Modules



Stacked FPX Devices

WUGS

I/O port I/O portWUGS Switch Elements

Two StackedFPX Devices NID RAD SRAM

SDRAM

NIDRADSRAM

SDRAM

Programmer

Target



Programmer ResultsProgrammer +

TCP-Splitter +

Protocol Wrappers

Post Place & Route Clock Frequency

71.76 MHz

Slice Flip Flops 5668 (14%)

LUTs 5210 (13%)

Block RAM 47 (29%)

Time to program 3 devices with 2.2MByte config file

1.102 seconds



Comparative Transmit Performance(1MByte bitfile) (wide area throughput = 8Mb/s) (switch delay = 100usec)

Devices Programmed(N)

One-at-a-time

Programming(N*filesize/bitrate)

Multi-Device

Programming(size/rate + N*delay)

1 1 sec 1 sec

10 10 sec 1 sec

100 1.7 min 1 sec

1,000 16.7 min 1.1 sec

10,000 2.8 hrs 2 sec

100,000 1.2 days 11 sec



Comparative Transmit Performance(1MByte bitfile) (wide area throughput = 80Mb/s) (switch delay = 100usec)

Devices Programmed(N)

One-at-a-time

Programming(N*filesize/bitrate)

Multi-Device

Programming(size/rate + N*delay)

1 .1 sec .1 sec

10 1 sec .1 sec

100 10 sec .1 sec

1,000 1.7 min .2 sec

10,000 16.7 min 1.1 sec

100,000 2.8 hrs 10.1 sec



Summary

• A hardware circuit has been developed which supports the simultaneous programming of multiple devices

• Devices can be dispersed throughout the Internet at disparate locations

• Programming information is transmitted once and received by all devices

• Simple to add or remove devices from programming chain



Multi-Device Programmer

PCPCPCPCInternet

PCPCPCPC


End Point



TCP/IPdata flow

• A hardware circuit which extracts device configuration information from TCP/IP data flow and programs remote devices



Configuration

RAD

NID

RAD

NID

Programmer FPX Target FPX

TCP-FormattedData

Outgoing TCP-Formatted Data(to next device)

ReconfigurationBitstream

Field ProgrammableGate Array

Programmer

TCPSplitter

IP WrapperFrame WrapperCell Wrapper

A TCP/IP Based Multi-Device Programming Circuit

Documents

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