A Presentation to EECS Faculty By G. Serpen 8 April 2009.

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A Presentation to EECS Faculty By G. Serpen 8 April 2009

Transcript of A Presentation to EECS Faculty By G. Serpen 8 April 2009.

Page 1: A Presentation to EECS Faculty By G. Serpen 8 April 2009.

A Presentation to EECS FacultyBy G. Serpen

8 April 2009

Page 2: A Presentation to EECS Faculty By G. Serpen 8 April 2009.
Page 3: A Presentation to EECS Faculty By G. Serpen 8 April 2009.
Page 4: A Presentation to EECS Faculty By G. Serpen 8 April 2009.

Why Use Student Learning Outcomes? Clear expectations for students and faculty Common institutional language Context for course design and revision Curriculum Map and Assessment Faculty self-assessment Curricular match with industry standards Accrediting Agency standards

Adapted from: http://depts.washington.edu/grading/slo/benefits.html

Page 5: A Presentation to EECS Faculty By G. Serpen 8 April 2009.

Student Learning Outcomes are Specific: Students will be able to <action

verb> <something> Prescribe artifacts to be analyzed:

Measurable characteristics Specified methods of evaluation: exam

responses, portfolio section, performance Indicator: Combined data indicating

relative degree of achievement.

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3 cr. hrs. Lecture, 1 cr. hr. Lab History and overview Number systems and binary arithmetic Switching theory Combinational logic circuits Modular design of combinational circuits Programmable Logic Devices Memory elements Sequential logic circuits

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SUBTOPICS

Number systems and codes

Binary arithmetic Boolean and switching

algebra Representation and

manipulation of switching functions

Minimization of switching functions

Incompletely specified switching functions

STUDENT LEARNING OUTCOMES Work with binary

number systems and arithmetic.

Derive and manipulate switching functions that form the basis of digital circuits.

Reduce switching functions to simplify circuits used to realize them.

Page 8: A Presentation to EECS Faculty By G. Serpen 8 April 2009.

SUBTOPICS

Basic logic gates (AND,OR,NOT,NAND,NOR)

Realization of switching functions with networks of logic gates

2-level networks: AND-OR,OR-AND,NAND-NAND,NOR-NOR

Multi-level networks Physical properties of

logic gates (technology, fan-in, fan-out, propagation delay)

Elimination of timing hazards/glitches

STUDENT LEARNING OUTCOMES Realize switching

functions with networks of logic gates.

Explain and apply fundamental characteristics of relevant electronic technologies, such as propagation delay, fan-in, fan-out, and power dissipation and noise margin.

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The list of outcomes that draw direct and substantial support from listed SLOs include: Outcome 3k (use modern engineering techniques,

skills, and tools) The list of outcomes that were partially

(nevertheless to a reasonable degree) supported by the SLOs include: Outcome 3b (conduct experiments, analyze and

interpret data) Outcome 3c (design a system, component, or

process) Outcome 3g (communicate effectively)

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SLO

a b c d e f g h

1 2 √3 √4 √5

Course Student Learning Outcomes (SLO) are used to demonstrate support forABET Engineering Criterion 3 Program Outcomes a through k.