A Physical Threshold Voltage Model for Short-Channel Undoped Symmetric DG MOSFETs

7/27/2019 A Physical Threshold Voltage Model for Short-Channel Undoped Symmetric DG MOSFETs

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2010 International Conference on Communication, Computers and Devices, Kharagpur, INDIA December 10-12

1

A Physical Threshold Voltage Model for Short-

Channel Undoped Symmetric DG MOSFETs

A.Choudhury, R.K.Baruah, N.Barman, M.SenapatiDept. of Electronics and Communication Engineering

Tezpur (Central) UniversityTezpur, India

[email protected]

Abstract — A compact, physics based short-channel threshold

voltage model is presented, for undoped symmetric double-gateMOSFET. The variation of threshold voltage with channel length,silicon thickness and oxide thickness is analyzed. The model is

verified by numerical device simulator with close agreement forchannel lengths upto 5nm for different values of silicon thickness andoxide thickness.

Keywords- Double-gate; MOSFET; undoped ; scale length;threshold voltage

I. INTRODUCTION

As the conventional single gate bulk MOSFET scaling isapproaching the limit imposed by short channel effects, DG

MOSFET is becoming an attractive candidate for future VLSI due toits better gate control over the channel [1]. In DG MOSFET, as theshort-channel effect (SCE) is controlled by the device geometry, anundoped (or, lightly doped) body is used to sustain the channel. Theattractive characteristics of undoped DG MOSFET in subthreshold

region [2, 3] has made it yet more promising device in the nanometerscale.

Many papers based on numerical simulations have been reportedon threshold voltage rolloff as an indicator of short-channel effects(SCE) [3]-[8]. A compact, physics based short -channel model ishighly desired for efficient circuit simulations. Meindl et al [9]

proposed a model based on analytic solution of 2D poisson equationwith the mobile charge term included. In DG MOSFETs ultrathinsilicon channel is preferred to be undoped or lightly doped asundoped channel also helps to alleviate several other problems relatedto nanoscale MOSFETs, e.g., mobility degradation, random dopant

fluctuations, compatibility with midgap metal gate, etc. The termqΨ/kT>>1so that the hole density is negligible for n MOSFET in

poisson equation, which Meindl et al did not consider.

With consideration of this the variation of threshold voltage withchannel length, silicon thickness and oxide thickness is approachingtowards numerical device simulator results. In this paper, we haveconsidered qΨ/kT>>1in poisson equation and modified the model by

Meindl et al., a compact short-channel model for undoped symmetricDG (SDG) MOSFETs.

II. SHORT CHANNEL THRESHOLD VOLTAGE

MODEL

The structure of the undoped Symmetric DG MOSFET with

coordinate system is shown in fig 1.

The poisson equation with inclusion of inversion charge term underthreshold condition is given by

2 2

2 2 i

si

d d q ndx dy (1)

Where is electrostatic potential referenced to fermi level in the

source,( )F

in n e is the electron density, ni is intrinsic

carriers in silicon, is inverse of thermal voltage (q

kT ), and

F

is the nonequilibrium quasi-Fermi level referenced to the Fermi levelin the source, satisfying the following boundary conditions [9]

(0, ) 0

( , )

F

F DS

y

L y V

(2)

Where VDS is the drain voltage.




2

The boundary conditions for Ψ are given by

,

2

,

,

( )( , )2

(0, )

( , )

si

siGS MS i

ox sit

ox y

bi i

bi i DS

t V x

x y

t y

y V

L y V V

(3)

Where VGS is the gate voltage, MS i

gate work function referenced

to intrinsic silicon. , /(1/ ) ln( / )bi i D S i

V N n is the build in

voltage, where ND/S is the source to drain density.

( , ) x y can be written as [3,7]

0 1( , ) ( ) ( , ) x y x x y (4)

0( ) x is the solution to the 1D poisson equation

0

2

0

2 i

si

d qn e

dx

(5)

With boundary conditions

,

,

(0)

( )

bi i

bi i

V

L V

(6)

and 1( , ) x y is the solution to the remnant 2D solution

0 1

2 2

( , ) 11 12 2

x yi

si

d d q n e edx dy

(7)

With the boundary conditions

1

1

, 1

2

(0, ) 0

( , ) 0

( )( , )2

si

siGS MS i

ox sit

ox y

y

L y

t V x

x y

t y

(8)

Solution of (5) is given by

/ 2

0

1( ) ln sin

biV

bi

Di

e x V x L

(9)

Where

0 ,

2 2lnm bi i

V

B

Where2

si Di

iqn

is intrinsic Debye length.

The overall minimum potential in the channel ( )m

y is given by

00

cosh 2

( )cosh

siGS MSi mm m

y

t V y

(10)

Where

1 2 tanh

si

si si ox

si si

t

L

t t

L t

The popular definition of threshold voltage is the gate voltage atwhich minimum sheet density of inversion carriers Qinv, reaches a

value Vth at which the device turns on. The inversion charge (incoulombs per square meter) at x = L/ 2 can be calculated from thethreshold model as shown below

( / 2, ) // 2

0

siq L y kT y t

TH i

y

Q qn e dy

(11)

Using the expression of in this equation gives

2

2 20 0

1ln

1TH

th m m

i si

QeV e e

e n t

(12)

III. THRESHOLD VOLTAGE SENSITIVITIES

The sensitivities of threshold voltage with respect to channel length,silicon thickness and oxide capacitance obtained from our model is

compared with the reported works [8,9]. Our results are muchapproached towards the numerical device simulator ATLAS.




3

Fig1: Variation of Threshold voltage with channel length

Fig2: Variation of Threshold voltage with silicon thickness

Fig3: Variation of Threshold voltage with Oxide thickness

Fig4: Threshold voltage Roll off with channel length for different tox

Fig5: Threshold voltage Roll off with oxide thickness forTsi=15nm, L=45nm

Fig 6: Threshold voltage Roll off with Silicon thickness forTsi=15nm, tox=1.5nm

The threshold voltage versus channel length curve (Fig 1) in ourmodel is more approaching towards numerical device simulator and

more continuous at body doping concentrations1510

A N /cm3.

Threshold voltage sensitivities to channel thickness and channellength is from published work is compared with our model

calculations, which is close to numerical device simulator ATLAS.

TABLE I

Comparisons of our model calculations with published work

[8,9]

Threshold Voltage Sensitivities to Silicon Thickness for

L=25nm, tox=1.6nm

tsi (nm) /TH si

V T (mV/nm)

[8] [9] Our Model

7 -21.8 -24.8 -23.6

10 -28.0 -29.6 -28.8

15 -40.4 -40.8 -40.6




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Threshold Voltage Sensitivities to Channel Length L=25nm,tox=1.6nm

tsi (nm) /TH

V L (mV/nm)

[8] [9] Our Model

7 6.8 7.6 7.2

10 13.0 13.6 13.415 28.0 26.8 27.4

IV. CONCLUSION

A compact, physics based threshold voltage model for short

channel undoped symmetric double-gate MOSFETs has beenreported with mobile charge term included in 2-D Poisson equation.Model calculations are compared to published work. The sensitivitiesto channel length, channel thickness and oxide thickness are analyzedand are found in close agreement with numerical device simulatorATLAS. It is seen that L causes 30–50% more variation than does t si

for the same process tolerance, while tox causes the least, relatively

insignificant amount of variation.

REFERENCES

[1] The International Technology Roadmap for

Semiconductors (2001), online.

[2] K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y.

Arimoto, “Scaling theory for double-gate SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 40, no. 12, pp. 2326–2329,

Dec. 1993.

[3] B.Ray and S.Mahapatra, “Modeling of Channel Potential

and Subthreshold Slope of Symmetric Double-GateTransistor”, IEEE transactions on Electron Devices, VOL. 56,

NO. 2, pp. 260-266, Feb 2009.

[4] D. J. Frank, S. E. Laux, and M. V. Fischetti, “Monte Carlo

simulation of a 30 nm dual-gate MOSFET: how short can Si

go?,” in IEDM Tech.Dig., 1992, pp. 553–556.

[5] B. Agrawal,V. K. De, and J. D. Meindl, “Opportunities for

scaling FET’s for gigascale integration (GSI),” in Proc. 24th

ESSDERC , 1993, pp.919–926.

[6] H.-S. Wong, D. J. Frank, and P. M. Solomon, “Device

design consideration for double-gate, ground-plane, and

single-gated ultra-thin SOI MOSFET’s at the 25 nm channel

length generation,” in IEDM Tech. Dig., 1998, pp. 407–410.

[7] Z. Ren, R. Venugopal, S. Datta, M. Lundstrom, D.

Jovanovic, and J. Fossum, “The ballistic nanotransistor: asimulation study,” in IEDM Tech. Dig., 2000, pp. 715–718.

[8] K. Takeuchi, R. Koh, and T. Mogami, “A study of thethreshold voltage variation for ultra-small bulk and SOI

CMOS,” IEEE Trans. Electron Devices, vol. 48, pp. 1995–

2001, Sept. 2001.

[9] Q.Chen,E.M.Harrel, J.D.Meindl, “A physical shortchannel threshold voltage model for undoped symmetric

double-gate MOSFETs”, IEEE Trans. Electron Devices, vol.

50, no.7,pp. 1631–1637, Sept. 2003.

[10] S. M. Sze, Physics of Semiconductor Devices, 2nd ed.

New York: Wiley, 1981.

A Physical Threshold Voltage Model for Short-Channel Undoped Symmetric DG MOSFETs

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