A novel low-input-resistance, high-output-resistance and wide-bandwidth current mirror using class-AB FVF cellCAFFEY JINDAL and RISHIKESH PANDEY*
Department of ECE, Thapar Institute of Engineering and Technology (TIET), Patiala, India
e-mail: jindalcaffey@gmail.com; rpandey@thapar.edu
MS received 20 January 2021; accepted 27 September 2021
Abstract. A novel low input and high output resistance current mirror using class-AB FVF cell is presented in
this paper. In the proposed current mirror, class-AB cascoded FVF cell acts as a current sensing cell and results
in low input resistance of the proposed current mirror. The proposed current mirror uses a regulated cascode
output stage to enhance its output resistance. The various other advantages offered by the proposed current
mirror are large current mirroring range with high accuracy, low THD, and wide bandwidth. The physical layout
of the proposed current mirror has been designed in the Cadence tool. The post-layout simulation results have
also been demonstrated to validate its performance.
Keywords. CMOS; current mirror; flipped voltage follower; input resistance; output resistance.
1. Introduction
had been realized in analog form are now implemented
digitally. But, there are many areas in which it is difficult to
replace analog circuits with their digital counterparts,
regardless of advancement in technology [1, 2]. Analog
signal processing is important because all naturally occur-
ring signals are analog and therefore, it is required in the
processing of natural signals, digital communication, sen-
sors, wireless receivers, optical receivers, etc. The
increased market demand has also renewed interest in
analog integrated circuit design. The major component of
analog integrated circuits is the current mirror because
current mirrors play a major role in the processing of cur-
rent signals in various applications with the advancements
in current-mode signal processing [3].
Current mirrors are the fundamental building blocks for
analog and mixed-signal circuits such as current conveyors
[4], operational amplifiers [5], analog filters [6], low-
dropout regulators [7], operational transconductance
amplifiers [8], analog-to-digital converters [9], etc. Current
mirrors are used for current amplification, current-mode
signal processing, generation of bias currents, and voltage-
to-current conversion. It is also used as an active load in
various differential amplifiers [10]. The current mirror is a
current-controlled current source and ideally, it replicates a
reference dc bias current with unity gain [11]. Also, by
adjusting the aspect ratios of transistors forming the pri-
mary current mirror, current amplification and attenuation
can be achieved [12]. The current mirrors are also more
economical than resistors because current mirrors require
less area and provide accurate copying of the current. The
properties of current mirrors with high performance are
accurate copy of the current, low input resistance, low input
and output compliance voltage, wide bandwidth, and high
output resistance [13]. These properties of the current
mirror have a great impact on the performance of the whole
system.
inadequate performance because of less accuracy in current
mirroring and low output resistance. It also suffers from
transistor mismatches and DC gain errors. Nowadays, with
the scaling of CMOS technology, short-channel MOSFETs
have been used which shows larger transconductance but
possess lower output resistance [12]. Thus, various current
mirror structures with improved performance have been
reported in the literature. George Wilson et al [14] pro-
posed Wilson current mirror by adding a transistor in the
conventional current mirror. It allows mirroring of current
more accurately and offers improved output resistance. But,
the asymmetric biasing of Wilson current mirror results in
DC errors. The improved Wilson current mirror consisting
of four transistors shows better current mirroring action as
compared to the conventional Wilson current mirror [15].
But, the error in the direct-current transfer ratio of output
current to input current when the fourth transistor is omitted
has not been quantified. Hart et al [16] overcome this
limitation but the improved Wilson current mirror has the
disadvantage of high input resistance. The cascode current
mirrors have also been discussed to enhance the output*For correspondence
Sådhanå (2021) 46:225 Indian Academy of Sciences
https://doi.org/10.1007/s12046-021-01751-9Sadhana(0123456789().,-volV)FT3](0123456789().,-volV)
Wilson current mirror, improved Wilson current mirror,
and cascode current mirror require high input and output
voltages which restricts their use in low-voltage applica-
tions. To overcome these disadvantages, self-biased high
swing cascode current mirror [17] and self cascode current
mirror [18], with high output resistances have been repor-
ted. The current mirrors have also been reported using level
shifter [19], bulk-driven technique [20], and floating-gate
technique [21, 22] which offer improved performance.
However, current mirrors based on these techniques suffer
from the limitations as level shifter increases the power
consumption, bulk-driven technique degrades the frequency
response and floating-gate technique suffers from initial
charge problem that leads to DC offsets. The current mir-
rors based on other topologies are advanced current mirror
[23], current mirror with current compensation
scheme [24], current mirror with improved bandwidth [25],
resistor based current mirror [26], and current mirror using
flipped voltage follower (FVF) cell [27–31]. Out of these,
the advantages of FVF cell are operation under low-voltage
and approximately unity voltage gain which make it suit-
able to be used at the input stage for the designing of
current mirrors [32]. The FVF cell also reduces the required
input voltage for the proper working of the current mirror.
However, the current mirror based on conventional FVF
cell does not offer low enough input resistance as desired. It
also shows poor current mirroring action due to the class-A
behavior of conventional FVF cell.
In this brief, a class-AB FVF cell [33] based novel cur-
rent mirror is proposed which overcomes the limitations of
current mirrors based on class-A FVF cell. The key
advantages offered by the proposed current mirror are low
input resistance, large current mirroring range with high
accuracy, low THD, wide bandwidth, and high output
resistance.
Figure 1 illustrates the proposed current mirror designed
using a class-AB FVF cell formed by transistors M1-4 at the
input. The FVF cell provides low input resistance and also
reduces the required input voltage for the proper working of
the proposed current mirror. The input resistance at node
‘D2’ of the proposed current mirror is reduced due to the
cascode transistor M4. The transistor M3 forms an adapt-
able current source of 2Ib to achieve the class-AB behavior
in FVF cell. The FVF cell is considered like a current
sensing cell (node ‘D2’ acts as a current sensing node) due
to its low output resistance. The fixed DC voltage Vb is
generated by the replica bias scheme [34], where the gate
terminals of transistor M3 and diode-connected transistor
Mb (replica of transistor M3) are connected. The bulk and
drain terminals of transistor Mb are also connected and
current source Ib is connected at its drain terminal.
The input current is given at the node ‘D2’ which is
converted to a voltage applied at the gate of transistor M5
(node ‘D4’). Then, this gate voltage generates a replica of
current Iin?Ib (flowing through transistor M2) in transistor
M5 since the transistors M2 and M5 are perfectly matched.
The gate terminal of transistors M6 is connected with the
gate terminal of transistor Mb to generate current Ib. The
transistor M6 splits the currents Iin and Ib and finally, Iout =
Iin is obtained at the output node. Further, the regulated
cascode structure [35] formed by transistors M7-8 shown in
figure 2 is employed at the output node to increase the
Figure 1. Proposed current mirror.
Figure 2. Proposed regulated cascode output based current
mirror.
output resistance. The transistors M1-8 are working in the
saturation region. Since the input and output voltage
requirements of the proposed current mirror are VDSsat2 and
VDSsat5 (few mV), respectively, it can be efficiently utilized
in the low-voltage environment.
3.1 Relation between input current and output current
Figure 3 is used to observe the relation between input and
output currents in the proposed current mirror. In the
model, the transconductances of transistors M1,2,4,5 and
output resistances of transistors M1-6 are denoted by
gm1,2,4,5 and ro1-6, respectively. The bulk terminals of
transistors M1,3,4,6 are connected to a different node rather
than the source terminal which results in transconductance
due to body effect i.e. gmb1,3,4,6. The current source Ib connected at node ‘D4’ can be replaced by transistor M9
with output resistance ro9. By applying KCL at nodes ‘D1’,
‘D2’ and ‘D4’ and assuming gmro 1, we obtain
vd2 gm1 þ gmb1ð Þ ¼ vd1 gmb3 þ gm4 þ gmb4ð Þ ð1Þ iin ¼ vd2 gm1 þ gmb1ð Þ þ vg2gm2 ð2Þ
vg2 ¼ vd1 gm4 þ gmb4ð Þro9 ð3Þ Using Eq. (1) and Eq. (2), the input current iinð Þ is
modified as
iin ¼ vd1 gmb3 þ gm4 þ gmb4ð Þ þ vg2gm2 ð4Þ Using Eqs. (3) and (4), Eq. (4) can be written as
iin ¼ gm2 þ 1
ro9
vg2 ¼ gm2vg2 ð5Þ
In Eq. (5), it is assumed that gm4 þ gmb4 gmb3 and
gmro 1.
By applying KCL at node ‘D1a’, we get
iout ¼ gm1a þ gmb1að Þvd5 ð6Þ By applying KCL at node ‘D5’, we get
gm1a þ gmb1að Þvd5 ¼ gm5vg2 ð7Þ Using Eqs. (6) and (7), the output current (iout) is
obtained as
iout ¼ gm5vg2 ð8Þ Since the transistors M2 and M5 are perfectly matched,
we can write gm2 ¼ gm5.
By comparing Eqs. (5) and (8), we get
iout ¼ iin ð9Þ From Eq. (9), it is observed that the output current (io)
follows the input current (iin).
3.2 Input resistance (Rin)
source (vin) is considered at the input terminal (drain of
transistor M2) which supplies current ðiinÞ as illustrated in
figure 4. By applying KCL at node ‘D1’ and ‘D4’, we get
vd1 vin
vd1
ro3
ro4 ¼ vd4
Assuming gmro 1 in Eq. (11), the drain voltage of
transistor M4 (vd4) can be written as
vd4 ¼ vd1 gm4 þ gmb4ð Þro4jjro9 ð12Þ Using the value of vd4 from Eq. (11) in Eq. (12) and
assuming gmro 1 and ro4 ro9, the value of drain volt-
age of transistor M1 (vd1) is given as
Figure 3. Small-signal equivalent model of the proposed current
mirror.
input resistance.
ð13Þ
iin gmb1vin gm1vin þ vd1 vin
ro1 ¼ gm2vd4 þ
ro2 ð14Þ
Substituting the values of vd4 and vd1 from Eqs. (12) and
(13), respectively in Eq. (14), the input resistance (Rin) is
given as
Rin ¼ gmb3
gm1 þ gmb1ð Þ gmb3 þ gm2gm4ro4 þ gm2gmb4ro4ð Þ ð15Þ
3.3 Output resistance ( Rout)
The calculation of the output resistance Routð Þ has been
performed using the small-signal equivalent model of reg-
ulated cascoded structure (figure 2) shown in figure 5. In
the model, gmb1a;8 are the transconductances of transistor
M1a,8 under body-effect, gm1a;7;8 are the transconductances
of transistors M1a,7, 8, and ro1a, 5, 7, 8 are the output resis-
tances of transistors M1a, 5, 7, 8.
The voltages at node ‘D7’ is written as
vd7 ¼ gm7ro7v 0 d1a ð16Þ
Applying KCL at nodes ‘‘D8’, ‘D1a’ and ‘D5’, we get
iout ¼ gm8 vd7 vd5ð Þ gmb8vd5 þ vout vd5
ro8 ð17Þ
ro1a ð18Þ
ro5 ¼ iout gm1avd5 þ gmb1avd5ð Þ þ vd1a vd5
ro1a ð19Þ
Using Eqs. (18) and (19), the voltage at node ‘D5’ is
written as
vd5 ¼ ioutro5 ð20Þ Substituting Eq. (20) in Eq. (18), the voltage at node
‘D1a’ is written as
vd1a ¼ gm1a þ gmb1að Þro1a þ 1ð Þro5iout ð21Þ Using Eqs. (16), (17), (20) and (21), the output resistance
ðRout) is expressed as
Rout ¼ vout
iout ¼ ro5 þ ro8 þ ro5ro8 gm8 þ gmb8ð Þ
þ ro5ro7ro8gm7gm8 þ ro1aro5ro7ro8gm7gm8
gm1a þ gmb1að Þ ð22Þ
3.4 Transfer function ( Ai sð Þ) Figure 6 shows the high-frequency small-signal model of
the proposed current mirror where gate-to-source capaci-
tances of transistors M1,2,4,5 are denoted by Cgs1,2,4,5
whereas, the body-to-source capacitances of transistors
M1,3,4,6 are represented by Cbs1,3,4,6. By applying KCL at
nodes ‘D1’, ‘D4’ and ‘D2’ (assume gm ro 1), we get
Figure 5. Small-signal equivalent model for the calculation of output resistance.
225 Page 4 of 10 Sådhanå (2021) 46:225
vd2 sð Þ gm1 þ gmb1ð Þ ¼ vd1 sð Þ gmb3 þ gm4 þ gmb4 þ sCbs3 þ sCgs4 þ sCbs4
ð23Þ
¼ vd1 sð Þ gm4 þ gmb4ð Þ ð24Þ
iin sð Þ ¼ vd2 sð Þ gm1 þ gmb1 þ sCgs1 þ sCbs1
þ vg2 sð Þgm2
ð25Þ The body effects of transistors M1,4 can be neglected
because gm1;4 gmb1;4 and Cgs1;4 Cbs1;4. Also, as the
transistors M2 and M5 are perfectly matched, we can
assume Cgs2 ¼ Cgs5. Using these assumptions, Eqs. (23),
(24), and (25) can be modified as
vd2 sð Þgm1 ¼ vd1 sð Þ gmb3 þ gm4 þ sCbs3 þ sCgs4
ð26Þ
iin sð Þ ¼ vd2 sð Þ gm1 þ sCgs1
þ vg2 sð Þgm2 ð28Þ Using Eqs. (26) and (27), the voltage vd2 sð Þ can be
expressed as
ro9 þ 2sCgs2
gm1gm4
ð29Þ Using Eqs. (28) and (29), we get
gm1gm4iin sð Þ ¼ vg2 sð Þ s3 2Cgs1Cgs2Cgs4 þ 2Cgs1Cgs2Cbs3
þ s2
ro9 þ Cgs1Cbs3
Figure 6. High-frequency small-signal model of the proposed current mirror.
Figure 7. Physical layout diagram.
Sådhanå (2021) 46:225 Page 5 of 10 225
On applying KCL at nodes ‘D1a’ and ‘D5’ (assume
gmro 1), we obtain
iout sð Þ ¼ vd5 sð Þ g 0 m1 þ g
0 mb1
ð31Þ
vd5 sð Þ gm1a þ gmb1að Þ þ gm5vg2 sð Þ þ vd5 sð Þ sCgs1a þ sCbs1a
¼ 0
ð32Þ Using Eqs. (31) and (32), we get
iout sð Þ ¼ gm1a þ gmb1að Þgm5vg2 sð Þ gm1a þ gmb1a þ sCgs1a þ sCbs1a
ð33Þ
given as
iout sð Þ ¼ gm1agm5vg2 sð Þ gm1a þ sCgs1a
ð34Þ
Using Eqs. (30) and (34), the transfer function (Ai sð Þ) of the proposed current mirror is expressed as
3.5 Bandwidth ( wo)
In Eq. (35) by assuming Cbs3 Cgs4; 1=ro9 ¼ gm2 and
gmb3 2gm4, the poles of the proposed current mirror are
written as
ð36Þ The location of poles (wp1;2;3;4) can be written as
wp1
Cbs3
ð37Þ The relation of bandwidth (wo) with poles and zeros can
be generalized [36] as
Substituting the values of wp1;wp2;wp3 and wp4 from
Eq. (37) in Eq. (38) and assuming gm1a ¼ gm1;Cgs1a ¼ Cgs1
the bandwidth (wo) is given as
wo ¼ 1ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1
The proposed current mirror is designed in 180 nm CMOS
technology and simulations have been performed in the
Cadence tool. The biasing currents Ib and Ib1 are chosen as
20 lA and 100 lA, respectively. Figure 7 depicts the
physical layout of the proposed current mirror occupying an
area of 32.39 lm 9 25.46 lm.
The DC characteristics for input current varying from 0
to 220 lA are illustrated in figure 8 and it shows that the
output current mirrors the input current. The plot of DC
Ai sð Þ ¼ iout sð Þ iin sð Þ ¼ gm1agm1gm4gm5
ðgm1a þ sCgs1aÞ
ro9 þ Cgs1Cbs3
ro9 þ gm4Cgs1
225 Page 6 of 10 Sådhanå (2021) 46:225
error in percentage for the entire range of input current is
shown in figure 9 and relative DC error is obtained as
0.58%.
operation of the proposed current mirror is 0.39 V-0.40 V
as shown in figure 10. Figure 11 shows the output I-V
characteristics for the different values of input current.
From figure 11, it can be seen that the minimum required
output voltage is 0.2 V.
The gain versus frequency plot of the proposed current
mirror is depicted in figure 12 and 3-dB bandwidth is
measured as 278 MHz. The proposed current mirror offers a
Figure 8. DC characteristics.
Figure 9. DC error (in percentage) for the entire range of input
current.
Figure 11. I-V characteristics at the output node.
Figure 12. Gain versus frequency plot.
Figure 13. Output resistance versus frequency plot.
Sådhanå (2021) 46:225 Page 7 of 10 225
low value of input resistance of 53 X. The proposed current
mirror also offers high output resistance of 40 MX as
shown in figure 13 due to the use of a regulated cascode
output stage.
Figure 15. Settling time response.
Figure 16. Sinusoidal transient response.
T a b le
1 .
C o m p ar is o n b et w ee n re p o rt ed
st ru ct u re s o f cu rr en t m ir ro r an d th e p ro p o se d w o rk .
P ar am
et er s;
S u p p ly
V o lt ag e (V
) 1
T ec h n o lo g y (l m )
0 .1 8
0 .1 8
0 .1 8
0 .1 8
0 .1 8
0 .1 8
0 .1 8
0 .1 8
C u rr en t R an g e (l A )
0 .0 1 to
In p u t R es is ta n ce
Xð Þ
) 0 .1 1
– 0 .2
O u tp u t R es is ta n ce
Xð Þ
1 .8
(M H z)
2 1 2
2 7 8
– 4 1 3
Figure 14 shows the transient plots of input and output
currents when a square pulse of 0 to 220 lA is given at the
input of the proposed current mirror. The settling time (2%
of their final value) of the output current is 15 ns as
observed from the transient response shown in figure 15.
From figure 16, the THD is observed as 0.9 % when a
sinusoidal input current is applied.
The comparison between reported structures of the cur-
rent mirror and proposed work is done in table 1. It is
observed from the table that the power dissipation of
reported current mirrors [22, 26, 27] is lower than the
proposed circuit but the current mirrors [26, 27] shows
disadvantages such as limited current mirroring range, high
input resistance, large error, limited bandwidth, and low
output resistance. The proposed circuit offers better per-
formance in terms of minimum output voltage and output
resistance than the reported current mirror [22]. Also, the
other reported current mirror structures [20, 21, 25, 32]
have various limitations such as limited current mirroring
range, large error, high input resistance, poor bandwidth,
more power dissipation, and low output resistance. The
proposed circuit overcomes the limitations of existing
current mirrors and offers low input resistance, large cur-
rent mirroring range with high accuracy, low THD, wide
bandwidth, and high output resistance.
5. Conclusions
A novel current mirror designed using a class-AB FVF cell
and a regulated cascode output stage has been presented in
this work. The proposed current mirror offers several
advantages like low input resistance, large current mirror-
ing range with high accuracy, low THD, wide bandwidth,
and high output resistance. Due to its inherent advantages,
it can be widely used in the designing of various low-
voltage analog/mixed-signal circuits.
supported by the Council of Scientific and Industrial
Research (CSIR), New Delhi, India (File No.
09/677(0039)/2019-EMR-I). The author is grateful to
CSIR, India, for financial support.
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