A new polymer insulated gate fieldeffect transistorM. Aktik, Y. Segui, and Bui Ai Citation: Journal of Applied Physics 51, 5055 (1980); doi: 10.1063/1.328356 View online: http://dx.doi.org/10.1063/1.328356 View Table of Contents: http://scitation.aip.org/content/aip/journal/jap/51/9?ver=pdfcov Published by the AIP Publishing Articles you may be interested in Ambipolar organic field-effect transistor using gate insulator hysteresis Appl. Phys. Lett. 86, 143513 (2005); 10.1063/1.1899773 Dual insulated-gate field-effect transistors with cadmium sulfide active layer and a laminated polymer dielectric Appl. Phys. Lett. 84, 2922 (2004); 10.1063/1.1704875 Field-effect transistors on rubrene single crystals with parylene gate insulator Appl. Phys. Lett. 82, 1739 (2003); 10.1063/1.1560869 Ferroelectric switching of a fieldeffect transistor with a lithium niobate gate insulator Appl. Phys. Lett. 59, 3654 (1991); 10.1063/1.105610 Offset channel insulated gate fieldeffect transistors Appl. Phys. Lett. 41, 360 (1982); 10.1063/1.93513

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A new polymer insulated gate field-effect transistor M. Aktik, Y. Segui, and Sui Ai Laboratoire de Genie Electrique associe au CNRS. 2 rue Camichel. 31000 Toulouse. France

(Received 15 February 1980; accepted for publication 9 April 1980)

This paper describes the fabrication of a plasma-polymerized siloxane insulated-gate field-effect transistor which permits the study of the polymer-silicon interface. Preliminary results are reported on both fixed surface charge density (1.7X 1012 cm -2) and hole mobility (500 cm2 IV sec) in a P-channel metal-insulated semiconductor field-effect transistor.

PACS numbers: 73.4O.Qv, 85.30.Tv, 81.15.Jj

A plasma-polymerized polysiloxane insulated-gate field-effect transistor has been fabricated on silicon in order to study polymer-semiconductor interface properties. Pre­liminary studies of a P-channel metal-insulated semiconduc­tor field-effect transistor (MISFET) give the values of the flat-band voltage VFB and of a charge density at the insula­tor-semiconductor interface QT which are in good agree­ment with those obtained by C-V measurements. Further­more, the difficulties encountered in the C- V method due to the hysteresis are eliminated and additional information is obtained on minority-carrier mobility. The values of VFB ,

QTI and,up given by the output characteristics of the device are, respectively, +19 V, -1.7X 1012 cm -2, and 500 cm2/V sec. The device fabrication process, the experimental conditions, and the method for evaluating these quantities are presented.

Transistors have been fabricated on N-type epitaxial silicon of surface orientation (111). The epilayers are phos­phorus doped (0.45 n cm) and have a thickness of 4.5 ,urn. Figure 1 shows the device geometry. A polysiloxane deposit obtained by glow discharge, as described in preceding pa­pers l

-3 insulates the gate from the channel of 1.8-mm length

and 3-mm width. The polymer thickness is about 1500 A. The plasma-polymerized siloxane has a resistivity of7 X 10 14

n cm at 1 X 106 V Icm. Its dielectric permittivity is 2.5, while the breakdown field ranges between 3 and 7 X 106 V Icm.

SOD windows mask

L=1.8mm

Channel area cleaning mask

Z=3mm

DiffUSion mask Electrodes

FIG. I. MISFET device geometry.

Source and drain are boron diffused (NA = 3 X 1019 cm -3)

to a depth of 3.6 ,urn. The different stages of device preparation shown sche­

matically in Fig. 2 are (a) chemical cleaning of the substrate in a boiling solution ofHN03, then in a solution ofNH40H­:H20 2:H20 in the volume ratio 1: 1:5 at 90 ·C for 10 min and finally in a solution of HCl:H20 2:H20 in the volume ratio 1: 1:6 at 40 ·C for 4 min; (b) oxidation at 80 ·C with H 20 + O2 yielding 5000 A. ofSi02; (c) etching of windows on drain and source reiions and boron diffusion; (d) oxida­tion to more than 500-A thickness for substrate passivation; (e) etching ofSi02 on the channel area [Fig. 2(a)]; (f) deposi­tion of plasma-polymerized siloxane of 1500-A. thickness 1.2;

(g) aluminum metallization of2000-A. thickness and engrav­ing for source and drain windows [Fig. 2(b)]; (h) etching of polymer by rf discharge in a PDE 100 gaseous mixture4 and chemical etching ofSi02 [Fig. 2(c)]; (i) aluminum metalliza­tion of 44OO-A. thickness and source-gate-drain electrode engraving.

N

Substrate

( a)

Al mask Polymer

r"'~"'~:"M),,' ( b)

Polymer and Si 02 etching

~ ~ t,·:!<~~m1W~ j

( c )

FIG. 2. Fabrication steps for a P-channel MISFET: (a) channel area clean­ing after source and drain diffusion; (b) deposition of a polymer layer and aluminum mask engraving; (c) polymer and Si02 etching for source and drain connections.

5055 J. Appl. Phys. 51(9). September 1980 0021-8979/80/095055-03$01.10 © 1980 American Institute of Physics 5055

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" r..=_-___ -:

-30 -20 -10 o

C (pF) 1200

--- ------- - -- - - - -,,:"-

1000 :

:

800

, I , , ,

/' ,

10 20 30 40

V(V)

FIG. 3. C(V) characteristics on gate electrode when source and drain are connected to the substrate. Theory: solid curve-; broken curve,- - - - ; AC signal frequency: 10 kHz; triangular voltage sweep rate: 4.5 V Is.

The most critical stages of this process are the cleaning of the channel area and the deposition of the polymer layer, which determine the insulator-semiconductor interface quality. In our case, the channel surface oxide is etched by a commercial solution of "Transene HF Buffer," trademark of BSI Electronique, 52 avenue de New York, 75016 Paris, France.

The polysiloxane is formed by glow discharge in hexa­methyldisiloxane vapor under the following conditions: dis­charge frequency-2 kHz; discharge current and voltage-4.2 rnA rms and 340 V rms; discharge duration-15 min; monomer pressure--O. 5 Torr. The polymerization occurs at room temperature. A dry etching method described in a pre­vious paper4 is used for opening windows through the poly­mer layer in order to make source and drain connections. The conditions for the rf discharge for etching are gas pres­sure-5 Torr, discharge power-400 W at 13.5 MHz, and duration-l min.

A wide dispersion of the MISFET output characteris­tics are observed. This dispersion is related to insulator-se­miconductor interface preparation conditions. In these de­vices we have obtained channel conductance and transconductance values from stabilized network character­istics after about 10 h for given bias conditions. Channel transconductance is obtained by measuring the variation of drain current I D which corresponds to a 10-V gate voltage modulation in a linear region of the output characteristics on a curve tracer with maximum drain voltage of -0.1 V. Mi­nority carrier mobility is deduced using the approximate ex­pression for transconductance for small drain voltages5

:

aID I g -m- aVG Vo=cle

(1)

where Z and L are, respectively, the width and the length of the channel, Ci the insulator capacitance per unit surface area relative to the gate, VD the drain source voltage when the source is connected to the substrate, and V G the gate

5056 J. Appl. Phys., Vol. 51, No.9, September 1980

voltage. The insulator capacitance is obtained by measuring the gate capacitance in the accumulation mode VG > 0, which gives about 1.45 X 10-8 flcm2

, when source and drain are connected to the substrate (Fig. 3). The minority­carrier mobility calculated is then 500 cm2/V sec and the relative error is estimated to be about 20%. The experimen­tal C- V curve (Fig. 3) presents a sizeable hysteresis. Accord­ing to Sanchez et al.,6 the fact that the hysteresis loop is counterclockwise indicates the injection of carriers from the metal electrode. This injection induces a negative charge at the interface when the gate is negatively biased and can ex­plain the experimental curve-tracer characteristics (Fig. 4). The zero voltage gate bias curve indicates the presence of an inverted surface caused by space charge in the insulator in the vicinity of the interface. Otherwise, at VG = 0, I D would be zero, up to breakdown. The small hysteresis observed in these characteristics indicates the presence of a charge drain­age phenomenon due to the gate bias applied to the insulator layer during drain voltage sweep. The sweep frequency is 110Hz for a complete cycle of drain voltage change at a given gate bias.

In the linear region of the output characteristics, the channel conductance is given by5:

aID I Z g = -- = - -!lpCi(VG - VT ),

aVD v" ~ ete L (2)

when VT is the turn-on voltage5:

Vr = VFB + 2t/JB - (2EoE,qNDI 2t/JBI)1/2/C,. (3)

In Eq. (3) Eo is the free space permittivity, E, the semiconduc­tor permittivity, N D the donor impurity density, t/JB the bulk potential expressed as (kT /q) 10g(ND/nI).

The flat-band voltage calculated from Eq. (3) with ex­perimental values for channel conductance, hole mobility, and insulator capacitance is + 19 V. The charge density per unit surface area, deduced from the relation

(4)

is 1.7X 1012 cm -2, assuming the metal-semiconductor work function difference <PMS to be negligible. Assuming negligible surface states, QT represents the fixed surface

/ --..-

~ ;,V-

J I FIG. 4. Output characteristics ofpolysiloxane insulated gate FET. Ordi­nate: drain current, 50/lA/div; abiscissa: source-drain voltage, 0.5 V Idiv; gate bias: I V Istep. From bottom curve to top curve gate voltage is, respec­tively,O, I, -2 V, and -3 V. Curves present little hysteresis.

Communications 5056

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charge at the interface and the low mobility or fixed charge in the insulator.

In conclusion, the fabrication of a polymer insulated­gate field-effect transistor permits the study of the polysilox­ane-silicon interface under conditions which suppress the hysteresis effects which affect C- V measurements. Neverthe­less, a precise determination of the hole mobility by plotting static drain current versus gate bias for small drain voltage is not possible because of carrier injection from the metal elec­trode. The high value of the measured mobility agrees with a volume mobility of 450 cm/V sec to within experimental error. This result can be explained by the fact that the semi­conductor surface is not SUbjected to an annealing treatment during the device preparation. We plan to study the polysi-

5057 J. Appl. Phys., Vol. 51, No.9, September 1980

loxane-silicon interface as a function of two important pa­rameters, the cleaning of the channel area and the plasma­polymerized siloxane deposition conditions.

The authors wish to thank the staff of "Groupe Techno­logique" du L.A.A.S. for their help in MISFET device preparation.

'M. Maisonneuve, Y. Segui, and Bui Ai, Thin Solid Films 33,35 (1976). 'Y. Segui and Bui Ai, 1. App\. Polym. Sci. 20,1611 (1976). 'Yo Segui and Bui Ai, Thin Solid Films 50,321 (1978). 4M. Aktik, Y. Segui, and Bui Ai, 1. App\. Phys. 50, 6567 (1979). 'A. S. Grove, Physics and Technology a/Semiconductor Devices (Wiley, New York, 1967), p. 346.

"D. Sanchez, M. Carchano, and Bui Ai, 1. App\. Phys. 45, 1233 (1974).

Communications 5057

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