Partially based on Prof . Vishwani D. Agrawal lecture VLSI Testing
A DSP-Based Ramp Test for On-Chip High-Resolution ADC Wei Jiang and Vishwani D. Agrawal Auburn...
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![Page 1: A DSP-Based Ramp Test for On-Chip High-Resolution ADC Wei Jiang and Vishwani D. Agrawal Auburn university.](https://reader036.fdocuments.net/reader036/viewer/2022062320/56649d4e5503460f94a2d227/html5/thumbnails/1.jpg)
A DSP-Based Ramp Test for On-Chip High-Resolution ADC
Wei Jiang and Vishwani D. Agrawal
Auburn university
![Page 2: A DSP-Based Ramp Test for On-Chip High-Resolution ADC Wei Jiang and Vishwani D. Agrawal Auburn university.](https://reader036.fdocuments.net/reader036/viewer/2022062320/56649d4e5503460f94a2d227/html5/thumbnails/2.jpg)
Motivation
• Testing analog-to-digital converter (ADC)– Linear ramp to cover full range of ADC– Slow slope for static testing– Histogram-based non-linearity error
• Proposed DSP-based ramp test– Characterizing ADC using linear function– Estimating coefficients of the function
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Non-linearity Error
• Least significant bit (LSB)
• Signal values at lower and upper edges of each codes
• Non-linearity errors– Differential non-
linearity (DNL)– Integral non-linearity
(INL)
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kkk
k
ikk
kkk
kkk
kk
kk
DNLINL
LSBDNL
LSB
LSB
2
ˆˆ2
ˆˆ2
ˆˆ
5.0ˆ
5.0ˆ
1
1
2
1
1
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Typical ADC Testing Architecture
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TPG
ORA
TEST CONTROL
MUX
MUX
DAC
ADC
MIXED SIGNAL
MUX
ANALOG SYSTEM
ANALOG SYSTEM
MUX
BIST Results
Digital System
Input and Output
Analog System
Input and
Output
Analog Loopbacks
DSP
DIGITAL SYSTEM
Digital loopback
Digital input
Loopback controls
Test pattern control
Response control
Digital outputAnalog signals
Analog loopback
Analog system loopback
Analog output
Analog input
under-test
under-test
under-test
* F. F. Dai and C. E. Stroud, “Analog and Mixed-Signal Test Architectures,” Chapter 15, p. 722 in System-on-Chip Test Architectures: Nanometer Design for Testability, Morgan Kaufmann, 2008.
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Ramp Test Structure for ADC
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Similar to structures for histogram approach
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Ramp Test
• Histogram Test for high-resolution ADC– A large amount of code to be tested– Multiple samples for each code– Very low-slope ramp testing signals required
• Comparable to thermal noise
• Proposed Approach– Linear function to characterize ADC– Coefficients of the function are easy to calculate– Only part of codes measured; speed up testing
time
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Linear Function
• Linear ramp function– T is the sampling
time
• Measured output– K is the maximum
code
• Reconstructed ramp function using measured samples
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Kk
KkkfM
K
kMNADCKk
12
1..1
00
0
bkTakf
qeLSBkMkf ˆ
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Division of Measurements
• Divided full-range of ADC codes into two equal-size sections
• Sum up measurements of each section
• Lower bound M(0) and upper bound M(K) are discarded because of possible out-of-range measurements
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KbaTKKLSB
kfLSB
kMs
KbaTKKLSB
kfLSB
kMs
K
Kk
K
Kk
K
k
K
k
2
122
8
11
1
2
12
8
11
1
1
2/
1
2/0
2/
1
2/
10
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Calculation of Coefficients
• Two syndromes obtained from sums
• LSB, K and T are all known parameters
• Estimated coefficients calculated from syndromes
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2
421
1
2
41
1
3
24
11
011
0
011
010
KK
SSKS
LSBb
TKK
S
LSBa
baTKLSB
ssS
aTKKLSB
ssS
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BIST Steps - measurements
• Reset ramp testing signal generator• Detect first non-zero ADC output
(lower-bound of samples)• Measure all subsequent samples• Stop at the maximum ADC output
(upper-bound of samples)• DSP collects all valid measurements
and start to processing data
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BIST Steps – processing data• Divide measured samples into two
equal-size parts• Accumulate measurements of each part
to obtain two sums• Calculate two syndromes from two sums• Calculate two estimated coefficients of
the linear ramp function• (Optional) Compare each measured data
to estimated one from ramp function
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Design of Ramp Signal Generator
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Switch for resetting ramp
I I
I/30
ΔV+Vth ΔV
Range: 0 v~ Vdd-ΔV
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Simulation Results
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Simulation Results
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Other considerations
• Minimal number of samples– More samples, less quantization noise, more
accurate estimation– Not all codes need to be sampled in order to
reduce testing time– At least 2N-2 samples are found necessary in
practice
• The same idea may be used with low-frequency sinusoidal testing signals instead of ramp signal– More overhead and complexities with
sinusoidal generator
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Conclusion
• Proposed Approach– For high-resolution ADC– Less samples required comparing to
histogram approach– Simple algorithm to calculate
coefficients and make estimation
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THANK YOU
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