A 5.3 GHz Programmable Divider for

HiPerLAN in 0.25µm CMOS

N. Krishnapura1 & P. Kinget 2

Lucent Technologies, Bell Laboratories, USA.

1 Currently at Columbia University, New York, NY, 10027, USA.

2 Currently at Broadcom, Irvine, CA, USA.

high input frequency(5.15 - 5.3 GHz)

ProgrammabilityD: {220,…224}

Programmable divider for a HiPerLANcarrier synthesizer(5 channels)

~ 300 mVpk(~ 0 dBm)

23.5294 MHz

loop filter

phase detector

÷D

VCOD·fref

fin = D·fref

fref

Low V dd (~ 1.8V)

0.25µµm CMOS

Outline

• Divider architecture:

– Phase switching.

– Timing issues.

– Solution: Signal retiming.

• Circuit implementation:

– High speed ÷2(D-Flip Flop) stage.

• Measurement results.

• Comparison & conclusions.

Phase switching divider

• K phase switches per output cycle: ÷ (4N + K)

+ No high speed feedback loops around multiple flip-flops.

/20o

90o

180o

270o

fin fin/(4N+K)

output cycle

MUXfin/4

rising edgesseparated byone input cycle

DECODER

fin/2

/N

PULSEGENERATOR

4 STATEMACHINE

K pulses per[Craninckx, JSSC ’96]

Divisionfactor D

pulse width = 4Tin or 5Tin

5.3 GHz 2.6 GHz 23 MHz1.3 GHz

Glitches

• Change clocks only when both clocks are in the same state.

Retiming

X

Y

SY

OUT

SY

OUT

SY

OUT

YON

elongated pulse

spurious pulse

modified

fin

1/4 fin

control timing

X

Y

4 Tin 4 Tin 4 Tin5 Tin

corr

ect

inco

rrec

t

5 Tin

Phase switching divider with retiming

• Retimer inserted after the second stage: enforces controltiming.

/20o

90o

180o

270o

fin fin/(4N+K)

output cycle

MUX

rising edgesseparatedby 1 input cycle

DECODER

fin/2

Divisionfactor D

PULSEGENERATOR

K pulses per

RETIMER

4 STATEMACHINEun-synchronized

control signals

retimed clocksand controls

/N

Retimer: Implementation

• New control generated when both clocks are high.

• Clock and control go through identical stages.

• Feedforward operation for high speed.

XY

SY

Y11

to MUX

YON

CY

0

0

clocks

unsynchronizedcontrol signal synchronized

clock & control

clock bufferwith same delayas the controlgenerator

High speed ÷2 stages / latches

• Goals: Low Vdd(1.8 V) & high speed(5.5 GHz)

• pMOS: much smaller drive than nMOS.

CLK OUTVdd

CLK

DQ Q

D

Vdd

D D

Q Q

Vdd

CLKBCLKIbias

pMOS in signal path

stacked devicestoo little headroom

(source coupled logic)(Razavi ’95)

(TSPC)

Pseudo-nMOS low voltage latch

• 0.25µm CMOS, Vdd = 1.8 V: 3 stage ring osc.

– CMOS: 2.8 GHz.

– pseudo-nMOS: 6 GHz.

CLK CLK

CLKB

Vdd

D D

Q Q

5.5 GHz ÷2 stage

• 5.5 GHz ÷2 with 300mVpk (SE) inputs at Vdd = 1.8V.

• Disabled by pulling CLK, CLKB inputs to the rails.

CLK CLK

CLK

CLKB

CLKBCLKB

Vdd

VddCLKBCLK

0o 180o

Vdd

input accoupling

Programmable divider

• {220, …, 224} = 216 + {4, …,8} = 23 · 33 + {4, …,8}

• ÷3 stages: similar to ÷2, with gated input branches.

/20o

90o

180o

270o

fin/2

fin/(216+K)

4 to 8

output cycle

MUX

DECODER

fin/2

Divisionfactor D

/3 /3 /3

PULSEGENERATOR

pulses per

RETIMER

4 STATEMACHINE

÷3 stage

• AND gate: combined with the DFF input branches.

D Q

Q

D Q

Qfclk

fclk/3

D1

D2

CLK CLK

CLK

CLKB

CLKB

CLKB

Vdd

Vdd

D1 D2D1

D2

QQ

Q

Q

differentialrealization

LOGIC IMPLEMENTATION

Chip Photograph

divider~0.09 mm 2

1st ÷÷2 retimer other logic ckts.

o/p buffer

2nd ÷÷2

last 4stages

inp

inn

out

gnd

Measurements: Sensitivity

2 2.5 3 3.5 4 4.5 5 5.5 60

0.1

0.2

0.3

0.4

0.5

Vi,

pk (

SE

) / V

f / GHz

Vdd

= 1.8VV

dd = 2.0V

Vdd

= 2.2V

• 5.5 GHz operation with Vdd = 2.2 V, 300mVpk(SE) input.

• Changed technology: major discrepancy betweenmodels and process.

3.5 4 4.5 5 5.50

0.1

0.2

0.3

0.4

0.5

Vi,

pk (

SE

) / V

f / GHz

Vdd

= 1.8VV

dd = 2.2V

Phase noise measurement setup

• Divider contributes phase noise inside the loop bandwidth.

DIVIDER 2

DIVIDER 1

HP PHASE NOISEMEASUREMENT SYSTEM(HP 3048)

DETECTORPHASE

PHASESHIFT

SIGNALANALYZER

SPECTRUMANALYZER

90oclock

• Measured noise = twice the noise of each divider.

• Input referred phase noise(@ 5.5 GHz): + 47dB (220x).

Measurements: Phase Noise

• o/p phase noise from 2 dividers & o/p buffers.

• ~ -131 dBc/Hz @ 1 kHz offset.

• 1/f behavior down to 1Hz.

Summary

Technology 0.25 µm CMOSChip Area 0.09 mm 2

Vdd 2.2 VI(Vdd) 37 mAfin, max 5.5 GHz

Sensitivity 300 mV pk., SEo/p phase noise

(5.5 GHz signal i/p)-131 dBc / Hz

@ 1 kHzVdd 1.8 V

I(Vdd) 24 mAfin, max 4.5 GHz

Sensitivity 300 mV pk., SEo/p phase noise

(4.5 GHz signal i/p)-133 dBc / Hz

@ 1 kHz

Comparison of CMOS dividers

Tech. fin, max

GHzVdd

VPd

mWInputVpk

Phase Noise(input ref.)

dBc/Hz@1kHzThis work ÷220

...÷224

0.25 µm 5.5 2.2 82 0.3 -83.2

De Muer ‘98 ÷8/9 0.7 µm 1.5 5.0 55 0.16 -93.9Kurizu ‘97 ÷4 0.15 µm 11.8 2.0 20 1.0

Craninckx ‘95 ÷2 0.7 µm 1.7 3.0 7.5 -87.9Razavi ‘95 ÷2 0.1 µm 13.4 2.6 26 1.3Foroudi ‘95 ÷16 1.2 µm 1.5 5.0 13 0.35H. Cong ‘88 ÷4/5 0.4 µm 4.2 3.5 0.5Maeda ‘97 ÷256 0.2 µm

GaAs14.5 0.6 22 1.0

Conclusions

• Programmable divider for HiPerLAN in CMOS.

• Retiming circuit for reliable phase switching.

• 5.5 GHz low voltage ÷2 stage in 0.25µm CMOS.

• Low phase noise achieved at a high input frequency.

Acknowledgments

• W. Fischer for layout, V. Boccuzzi for testing.

• A. Dunlop, M. Banu, R. Melville, H. Wang for testequipment and support.