5.5: A 3.2 to 4GHz, 0.25µm CMOSFrequency Synthesizer for IEEE

802.11a/b/g WLAN

Manolis Terrovitis, Michael Mack, Kalwant Singh, andMasoud Zargari1

Atheros Communications, Sunnyvale, California1 Atheros Communications, Irvine, California

Outline

■ System Requirements

■ Architecture and CircuitDescription

■ Measurements

■ Conclusions

Design Goals

■ Tuning Range 3.2 - 4.0 GHz

■ Reference Frequencies:13.33M, 6.66M, 3.33M, 10M

■ Drive LO Buffers at fVCO andI,Q LO Buffers at fVCO/2

■ Low Phase Noise

■ Low Spurs

Synthesizer Block Diagram

PFD CP VCOLPF

Reg1

I Q

P & S

16/17 Divider

fVCO

fVCO/4To LO BuffersControl

Logic LockDetector

Xtal Osc

8/8.5Divcounters

Reg2

/2

RefDiv

40MHz

FF

FF

Design Choices

■ Low VCO gain• Good VCO phase noise

• Low LPF resistor noise contribution

■ High charge pump current• Low LPF resistor noise contribution

• Low charge pump noise

Voltage Controlled Oscillator (VCO)

Vc

Regulated VDD (2.5V)

CMIM CMIM

7-bitcontrol

High-Frequency Divide-by-2

from VCO

I

QI

VDD

L

∆L

∆L

∆L

s0

s1

s2

D

q

clk clk

q

D

D

q

q Q

D

D

D

q

q

H. Rategh and T. Lee “Superhar-monic Injection-Locked FrequencyDividers”, JSSC, June 1999.

Adjustable Tuning

Rp=LωQ

Adjustable C Adjustable L

Equivalentparallelresistance

freq

ampl

freq

ampl

Multi-tap Inductors

t1 t2at2bt2c

Charge Pump

Regulated VDD

+ -

Replica Bias

dn

dn

up

up

IBIAS

ControlVoltage

MN

MP

CP

CN

Programmable Integrated LPF

...

......

CparallelCseries

Rseries

Vc Vc

8/8.5 Dual Modulus Divider

/2PhaseMulti-

f4 If4 Qf4 I

f4 Q

f2 I

StateMachine

/4

fVCO/16 or

div17

fVCO/17fVCO/2

plexerf2 I

/2f2 Q

f2 Q

J. Craninckx, M. Steyaert “A 1.75-GHz/3-V Dual-Modulus Divide-by-128/129 Prescaler in 0.7-µm CMOS”, JSSC, July 1996.

Phase Multiplexer

s0 s0

s2 s2s4

f4 I

s1 s1

s3 s3s5

f4 Q

VDD

outout

VDD VDD

f4 I f4 Q

Control Logic

■ Successive approximation search for the 7 bitsthat control the VCO tuning capacitors

■ Coarse digital alignment of the feedback clockwith the reference clock

■ Optimize for the control voltage value

■ Take corrective action when the controlvoltage drifts out of the acceptable range orwhen no-lock is detected

Measurement Setup

802.11a Transmitter

4.8 - 6 GHzRF output

BBI

BBQ

Synthesizer

DCInput

40MHz

fVCO

I QfVCO/2

● Measured Phase Noise at RF output is ~3.5 dB higher

than at the VCO frequency.

Output Spectrum (1)

-60

-40

-20

0

20

5.40 5.42 5.44 5.46 5.48

Frequency (GHz)

Po

wer

(d

Bm

)

40MHz,<-70 dBc

13.3MHz,<-75 dBc

Fo=5.44GHz, Fref=13.3MHz, (S=0)

Output Spectrum (2)

-60

-40

-20

0

20

5.29 5.30 5.31Frequency (GHz)

Fref/2,<-64 dBc

Po

wer

(d

Bm

)Fo=5.30GHz, Fref=13.3MHz, (S=9)

Measured Phase Noise (1)

-130

-120

-110

-100

-90

1K 10K 100K 1M 10M

Frequency Offset (Hz)

Ph

ase

No

ise

(dB

c/H

z)

-115 dBc/Hz

-107 dBc/Hz

-105 dBc/Hz

Fout=5240MHz, Fref=13.3MHz

Measured Phase Noise (2)

-130

-120

-110

-100

-90

-80

1K 10K 100K 1M 10M

Frequency Offset (Hz)

Ph

ase

No

ise

(dB

c/H

z)

-121 dBc/Hz

Low Loop BW

Fout=5240MHz, Fref=13.3MHz

VCO Phase Noise: -121 dBc/Hz @ 1MHz offset, 5.24 GHz carrier

Measured Phase Noise (3)

-130

-120

-110

-100

-90

1K 10K 100K 1M 10M

Frequency Offset (Hz)

Ph

ase

No

ise

(dB

c/H

z) Fout=5745M, Fref=3.33M

Fout=5250M,

Fout=5240M, Fref=13.3M

Fref=6.66M

Performance SummaryTechnology 0.25 µm CMOS, 1P5M,

MIM capacitors

Power Dissipation 93 mW

Area 1.7 mm2

Spot Phase Noise Fout= 5240MHz, Fref=13.3 MHz -105/-107/-115 dBc/Hz @

10K/100K/1M

Integrated PN (from 1K to 10M) Fout= 5240MHz, Fref=13.3 MHz

Fout= 5250MHz, Fref=6.66 MHz

Fout= 5745MHz, Fref=3.33 MHz

-45.3 dBc (0.31o)

-43.3 dBc (0.40o)

-40.9 dBc (0.54o)

Spurs <-64dBc

Settling Time <150µs

Synthesizer Micrograph

VCO

VCORegulator

High FreqDiv-by-2

8/8.5Div

CP

LPF

CP Regulator

Co

ntr

ol

Lo

gic

Conclusions

■ Fully integrated, wideband, 0.25µm CMOSsynthesizer

■ Excellent phase noise, spur performance andsettling time

■ Design highlights:

• On-chip voltage regulation

• Tuning with switching inductors

• Low noise VCO

• Charge pump topology

Acknowledgment

Support of the wireless team at Atheros. In particularD. Weber, S. Mehta, W. Si, B. Kaczynski, H. Dieh and J.Lu.