A 490-nA, 43-ppm/◦C,Sub-0.8-V Supply Voltage Reference

Pinar Basak Basyurt, Devrim Yilmaz AksinDept. of Electronics and

Communications EngineeringIstanbul Technical University

Istanbul, TurkeyE-mail: basyurt@itu.edu.tr

Edoardo Bonizzoni, Franco MalobertiDept. of Electrical, Computer and

Biomedical EngineeringUniversity of Pavia

Pavia, ItalyE-mail: edoardo.bonizzoni@unipv.it

Abstract—This paper presents a low power bandgap referencegenerator with 193-mV output voltage. The nominal supplyvoltage is 0.8 V, but the circuit can work with a supply down to0.65 V. The circuit has been fabricated with a standard 0.18 µmCMOS technology and achieves a temperature coefficient of43 ppm/◦C for temperatures ranging from 0 to 120◦C. A sampled-data amplifier consuming 140 nA and a reversed current-mode bandgap scheme draining 350 nA enable the achievedperformance.

I. Introduction

Along with the rapid development of modern communi-cation systems and consumer products, the market demandfor battery-operated circuits has been increased. Circuits formobile electronics require ultra-low power consumption andneed to work with a very-low supply voltage. It would beoptimal to use a supply voltage on the order of 0.5 - 0.6 Vbecause this is the voltage range at the output of a single solarcell [1]. Digital circuits can work with such low voltages,since their required supply voltage is just a bit more thanthe threshold of an n-channel or a p-channel transistor. Onthe contrary, conventional analog blocks such as amplifiersand reference circuits need higher supply voltage due to therequired overheads at the output stage and the necessary outputswing.

Voltage references are one of the critical building blocksof many systems on chip (SoCs) and mixed-signal integratedcircuits (ICs) such as data converters and voltage regulators asthey constitute a stable reference voltage for other sub-circuitsto generate predictable and repeatable results. However, thetechnology scaling and the demand for low power applicationslead to lower supply voltage, which makes traditional bandgapreference (BGR) architectures no more suitable. Indeed, whenthe temperature effects have been canceled, the value of thereference voltage for traditional BGRs is approximately equalto the extrapolated bandgap voltage of silicon at 0 K, 1.205 V.

Different approaches have been proposed to overcome thisproblem. One of them uses the resistive subdivision methodthat allows scaling down the reference voltage [2] in the outputbranch. This circuits are referred to as current-mode referencessince they generate a temperature-independent current, whichis then mirrored to an output resistor to create a sub-1V outputvoltage. Another solution consists of implementing the reversebandgap voltage principle (RBVP), as described in [3], [4],

which adds a thermal voltage (VT ) to an attenuated base-to-emitter voltage (VBE) instead of adding a VBE to a scaledVT . The problem of these circuits is the need of high gainNPN or PNP devices which are mostly unavailable in standardCMOS processes. There is also a range of solutions that usedifferent and low threshold MOS devices to meet low powerand supply voltage requirements. However, these solutions areprone to large output voltage spread at process corners, sincethe threshold of MOS transistors are typically poorly controlledin the fabrication process.

Increasing requirements for reference generators workingwith very low supply voltage and very low power should besatisfied by new circuit solutions using standard technologies.This work focuses on the design of a bandgap voltage gener-ator. This solution uses a current mode scheme with PMOStransistors in deep sub-threshold region. The circuit, imple-mented with a standard 0.18-µm CMOS technology, achievesa temperature coefficient (TC) of 43 ppm/◦C in the temperaturerange 0 − 120◦C and consumes 390 nW. The nominal supplyvoltage is 0.8 V, but the circuit operates properly down to0.65 V.

II. Proposed Bandgap Voltage Reference

Fig. 1 shows the schematic diagram of the circuit. Theconventional current mode bandgap [2] is reversed so that thereference voltage is generated across the output resistors ROUT .Transistors MP1 and MP2 operate in the sub-threshold regionto provide the diode-like voltage-current response, as required

CS

VCTRL

R1 R1

Ro

ROUT ROUT

MP2MP1 1:N

�A �D�S

SAMPLED-DATAAMPLIFIER

VO1VO2

VDDMLDO

VA MN0

VX

Fig. 1. Schematic diagram of the reversed current-mode bandgap scheme.

978-1-4799-5696-8/14/$31.00 ©2014 IEEE 115

VDD

VA

MN1

�A

�A

�A

�D

C2

R3 R4

RNL

MN2

MN3 MN4

C1�A MN5

MN6

MN7

MIN MN9

MN8

MN10

MN11

MP3 MP4 MP5 MP6 MP7

ICTAT

�A

�D

�S

VO1

VO2

ICTAT Generator�A

IQIINR2

Fig. 2. Schematic of the sampled-data amplifier and control phases time diagram.

to give rise to PTAT and CTAT currents. An LDO, consistingof the transistor MLDO and its control circuitry, generates thevoltage Vx. The loop equates the two output voltages, VO1and VO2. The operation of the LDO incorporates the start-up function. The direct transformation of PTAT and CTATcurrents into voltage with a reversed architecture avoids theuse of current mirrors, often source of inaccuracy, [5]. Theoutput voltage of the current mode bandgap, given by

VO1 =ROUT

R1

[VGS 1 +

R1

R0nVT ln (N)

](1)

where N = 16 and R1/R0 = 3.6, is first order temperatureindependent.

A. Sampled-Data Amplifier

When the signal band is small, like in the case of a bandgapcircuit, it can be convenient to use sampled-data operation. Inthis case, the sampled data technique is utilized at the op-amplevel. It results in the output voltage of the op-amp changing ina discrete manner under the control of a clock with a frequencyhigher than the frequency of the system. However, since theproposed voltage reference circuit is a continuous system, it isnot setting an operation frequency limitation for the op-amp.

The sampled-data amplifier (SDA) of Fig. 2 can operatewith low input common mode, provides a low output voltagelevel for low VDD, and performs auto-zero. The single endedscheme uses a bias current (IIN) of 100 nA. There are threephases of operation: during ΦA, the input transistor MIN isdiode connected while the top plate of the auto-zero capacitorC1 is charged to VO1. The duration of the amplification phase,ΦD, is half of the clock period, T . The signal current, id,added to the quiescent current IQ and mirrored to charge thecapacitor C2 (which is discharged to during ΦA) for the fixedtime set by ΦD. The bias current IQ determines the quiescentdischarge voltage. The switched capacitor output structure (see

also Fig. 1), controlled by ΦS , provides the output. The DCgain of the SDA is

A0 =IINT

2nVT C2(2)

where n is the sub threshold slope factor. Trade offs of thisdesign lead to C2 = 0.15 pF and T = 20 µs. It results in aDC gain A0 of 41 dB. The quiescent output voltage of theamplifier is equal to

VQ = VDD −IQT2C2

(3)

For the current design, VA quiescent is set to 410 mV withIQ = 5 nA and, if desired, it can easily be fine-tuned using theΦD duration. The minimum of the output voltage VA dependson the operation in the triode region of MN10.

The quiescent output voltage, VQ, of the sampled-dataamplifier has a negative temperature dependency. This meansthat the quiescent discharging current, IQ, is increasing withthe temperature. This is an expected result due to the thresholdvoltage variation of PMOS transistors used in the currentmirror that provides the circuit bias current. It is, indeed, wellknown that the transistor threshold voltage decreases with atemperature increase. By using a CTAT current to bias theamplifier along with choosing its quiescent output voltageequal to the nominal VGS of MLDO reduces the input errorvoltage magnitude due to the temperature dependence of theamplifier output voltage.

B. CTAT Generator

In the proposed voltage reference topology, the approachconsists in biasing the sampled-data amplifier with a CTATcurrent in order to compensate for the temperature dependencyof the SDA quiescent output voltage controlling MLDO. Fig. 2

116

includes the CTAT generator designed for this purpose. It isan improved version of the CTAT scheme described in [6].

In the circuit, a CTAT current is generated on R3 exploitingthe gate-to-source voltage of transistor MN3. MP4, MN4 andRNL compensate for the high temperature nonlinearity of thegenerated CTAT current. Resistor R4 is added to have the samebiasing conditions for MN3 and MN4. The absolute value ofthe CTAT current can be adjusted through the resistor R3, asfollows:

ICT AT =VGS ,N3

R3(4)

The nominal bias current is 12 nA at room temperature. Thesimulated CTAT temperature coefficient is −37 %/◦C in thetemperature range from 0◦C to 120◦C.

C. Supply Voltage Limit

The minimum supply voltage depends on the requiredoutput level and a number of practical limits. By inspection ofFig. 1, it results that:

VDD = VO2 + VGS ,MP1 + VDS ,MLDO (5)

In our design, an output voltage of 200 mV, 300 mVacross the PMOS diode, and a voltage drop as low as 100mV across MLDO lead to a supply voltage down to 0.6 V.This, however, it is not the only constraint in the circuit.The condition (VDD − VCTRL) > Vth,n + Vov (Vov being theoverdrive voltage) has to be satisfied for transistor MN0 inFig. 1 and a similar relation can be written for MLDO as well.Moreover, switching-on of transistors MN5 and MN6 in Fig. 2requires (VDD − VO1,O2) > Vth,n + Vov. The last condition isthe dominant for determining the minimum supply voltage.In the used technology, the thresholds of the P-channel andthe N-channel transistors are −0.45 V and 0.4 V, respectively.With an overdrive voltage of 50 mV, the minimum supplyvoltage is, hence, 0.65 V. However, this value increases for lowtemperatures as the transistors threshold voltage also increases.

0 10 20 30 40 50 60 70 80 90 100 110 120192

192.5

193

193.5

194

194.5

Temperature [°C]

V O1 [m

V]

Meas SimsVdd = 0.8VVdd = 0.75VVdd = 0.7VVdd = 0.65V

Fig. 3. Measured output voltage as a function of temperature.

101 102 103 104 105 106 107−65

−60

−55

−50

−45

−40

−35

−30

Frequency [Hz]

PSR

[dB

]

Fig. 4. Measured PSR.

III. Experimental Results

This bandgap voltage reference has been fabricated in astandard 0.18 µm CMOS technology with 6 metal 2 polylayers. The clock frequency is 50 kHz and the auto-zero phase,ΦA, period is set to 25% of the clock period.

Measurements with the chip temperature controlled bythe Thermo-Stream T-2800 give rise to the waveforms ofFig. 3 in which the measured output voltage as a functionof temperature for different supply voltages is provided. Inthe range from 0◦C to 120◦C, the achieved TC is 43 ppm/◦C.The same performance holds for the nominal supply voltageand for lower supply voltages. Simulation results, also givenin Fig. 3, for the same operating conditions show a goodmatch with experimental results. However, for low supply andlow temperature, the loop control does not work properly: therequired value of VA becomes very low because the thresholdvoltage of MLDO is higher than the value of the performedstatistical simulations at low temperatures.

Fig. 4 shows the measured power supply rejection (PSR)at the nominal supply voltage. The output is filtered with a6 pF capacitor. The PSR is −50 dB at 100 Hz and −36 dB at10 MHz.

Fig. 5 plots the supply current as a function of thetemperature when the supply voltage is 0.8 V. Thanks to theCTAT biasing of the control circuit, it changes only by 2%

0 20 40 60 80 100 120480

482

484

486

488

490

492

494

496

498

500

Temperature [°C]

Supp

ly C

urre

nt [n

A]

Fig. 5. Measured supply current as a function of the temperature.

117

191.5 192 192.5 193 193.5 194 194.5 1950

1

2

3

4

5

Output Voltage [mV]

Occ

uren

cies

Average value = 192.96mVStandard deviation = 0.53mV

Fig. 6. Measured output voltage level distribution.

CTAT CURRENT GENERATOR

BANDGAP CORE

SAMPLED-DATA AMP

Fig. 7. Chip microphotograph.

over the entire temperature range. The average value of thesupply current is 491.8 nA. At room temperature, the supplycurrent is about 490 nA, thus bringing the power consumptionto 390 nW.

Fig. 6 gives the distribution of the output voltage level forthe 20 available samples without any device trimming or phaseduty cycle calibration. Measurements have been collected atroom temperature, with a supply voltage equal to 0.8 V and aduty cycle of ΦD equal to 50 %. The mean value is 192.96 mVwhile the standard deviation is 0.53 mV. The 3σ inaccuracy is0.8 %. This is due to chip-to-chip mismatches; calibration ofthe duty cycle of ΦD can reduce the inaccuracy to less than0.1 %.

Fig. 7 shows the chip microphotograph with main circuitblocks highlighted. The active area, dominated by the resistorsused in the CTAT current generator, is 450 × 430 µm2.

The performance summary of the designed circuit andits comparison with other sub-1V voltage reference circuitsreported in the open literature is given in Table I. Thecomparison shows that the voltage reference proposed in thispaper achieves a reference voltage with temperature coefficientcomparable with existing solutions published values. The mea-sured power consumption is well below 0.5 µW and, moreimportantly, the circuit is able to operate at 0.8 V despite theuse of transistors with relatively high threshold voltage.

IV. Conclusion

This work demonstrated a new low power bandgap gen-erator capable of operating with very low supply voltage

TABLE I. Performance comparison with sub-1V bandgap referencesimplemented in standard CMOS technologies.

This work [5] [7] [8] [9]Technology [µm] 0.18 0.13 0.18 0.6 0.35

Ref. Voltage [mV] 193 256 221 603 190.1

Min. Supply0.65 0.75 0.85 0.98 1

Voltage [V]Sup. Current [µA] 0.49 0.2 3.9 18 0.25

TC [ppm/◦C] 43 40 194 15 16.9

Temperature0-120 -25-85 -20-120 0-100 -40-80

Range [◦C]PSR @ 100Hz [dB] -50 N/A N/A -44 -41PSR @ 10MHz [dB] -36 N/A N/A -17 -17

Untrimmed0.8 3 N/A N/A N/A

Accuracy (3σ)[%]Area [mm2] 0.195 0.07 0.0228 0.24 0.049

and achieving a temperature coefficient of 43 ppm/◦C in thetemperature range 0 − 120 ◦C. The minimum supply voltagelevel is limited at low temperatures by the threshold voltage ofthe used transistors. This design, implemented with a standard0.18 µm CMOS technology without any special process step,is able to operate properly over the 0 − 120 ◦C range withVDD=0.8 V. Lower supply voltages limit the temperature rangebecause of the increased Vth.

Acknowledgment

This work is partially supported by The Scientific andTechnological Research Council of Turkey under InternationalResearch Fellowship Programme-2214.

References[1] N. Bourgoine, “Harvest Energy from a single Photovoltaic Cell”, Journal

of Analog Innovation, vol. 21, no. 1, April 2011.[2] H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, and

K. Sakui, “A CMOS Bandgap Reference Circuit with sub-1V Operation”,IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 670-674,May 1999.

[3] R. J. Widlar, “Low Voltage Techniques”, IEEE Journal of Solid-StateCircuits, vol. SC-13, no. 6, pp. 838-846, Dec. 1978.

[4] K. Sanborn, M. Dongsheng and V. Ivanov, “A Sub-1-V Low-NoiseBandgap Voltage Reference”, IEEE Journal of Solid-State Circuits,vol. 42, no. 1, pp. 2466 -2481, Nov. 2007.

[5] V. Ivanov, R. Brederlow, and J. Gerber, “An Ultra Low Power BandgapOperational at Supply from 0.75 V”, IEEE Journal of Solid-StateCircuits, vol. 47, no. 7, pp. 1515-1523, July 2012.

[6] G. A. Rincon-Mora, “Voltage References: from Diodes to PrecisionHigher-Order Bandgap Circuits”, New York: Wiley-IEEE, 2001.

[7] P. H. Huang, H. Lin, and Y. T. Lin, “A Simple Subthreshold CMOS Volt-age Reference Circuit with Channel Length Modulation Compensation”,IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53,no. 9, pp. 882-885, Sep. 2006.

[8] K. N. Leung and P. K. T Mok, “A Sub-1-V 15-ppm/◦C CMOS BandgapVoltage Reference without Requiring Low Threshold Voltage Device”,IEEE Journal of Solid-State Circuits, vol. 37, no. 4, pp. 526-530,Apr. 2002.

[9] H. W. Huang, C. Y. Hsieh, K. H. Chen and S. Y. Kuo, “A 1V 16.9ppm/◦C250nA Switched-Capacitor CMOS Voltage Reference”, IEEE Inter-national Solid-State Circuits Conference Digest of Technical Papers,pp. 438-440, Feb. 2008.

118