L.  Picolli,  A.  Rossini,  F.  Maloberti,  F.  Borghetti,  P.  Malcovati,  A.  Baschirotto:  "A  10-­Bit   Pipeline   A/D   Converter   Without   Timing   Signals";   IEEE   International  Symposium   on   Circuits   and   Systems,   ISCAS   2006,   Kos,   21-­‐24   May   2006,   pp.  5355-­‐5358.  

 

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A 10-Bit Pipeline A/D Converter without TimingSignals

L. Picolli, F. Maloberti, A. Rossini F. Borghetti, P. Malcovati A. BaschirottoDepartment of Electronics Department of Electrical Engineering Department of Innovation Engineering

University of Pavia, Pavia, Italy University of Pavia, Pavia, Italy University of Lecce, Lecce, Italyluca.picolli@unipv.it fausto.borghetti(unipv.it andrea.baschirotto@unipv.it

andrea.rossini@unipv. it piero.malcovati@unipv.itfranco.maloberti@unipv.it

Abstract-This paper presents a novel 10-bit pipeline A/D spectrometers, which would be beneficial especially forconverter for low noise, self-triggered applications. The astronomical applications on satellites, where powerproposed A/D converter does not require any timing signal consumption, size and weight have to be minimized.(clock) in order to carry out the conversion, assuming that asampled signal is provided at the input. The circuit basically This paper presents an innovative AID converteropleras as "combinatorial logic, propagating the pasical architecture for self-triggered sensor applications. This A/Doperates a n atorial through the partial converter is based on the pipeline structure, which canconversions and the residues through the various stages achieve a good accuracy (10-12 bits), properly adjusted inasynchronously. The presented ADC has been designed in a order to operate without any clock signal. The onlystandard 0.35,um CMOS technology and the conversion period reretsofrt e thht the inputsignal he ois lower than 5OOns (i.e. 2MHz data rate). The power requirements ofthis structure are that the input signal has toconsumption is 39mW from a 3.3 V power supply. The total be already sampled and a trigger signal has to be provided tochip area without pads is 2.24 mm2. start the conversion. The block diagram, reported in Figure

1, shows a typical application of the proposed A/Dconverter (X-ray spectrometer), while Table I summarizes

I. INTRODUCTION the main design requirements.X-ray or y-ray spectrometry, is gaining importance in

several application fields, ranging from astronomy to CD

medicine. In such spectrometers, a large array of Jsemiconductor sensors is used for detecting events, which Analog Row/Column Aoccur randomly with Poissonian distribution. The energy of - Seeeach event has to be measured very accurately in order to -l-- ChEbuild an energy spectrum. Therefore, the sensors aretypically connected to very-low-noise front-end circuits,which provide an output dc voltage proportional to the ¢ Analog Row/Column Analog Row/Columnenergy of the event (through a peak-and-hold circuit) as well Chain Slector|[ICha ltoas a trigger signal which informs the system that an event = -==has occurred. Spectrometers are therefore a typical case ofself triggered applications, where the timing signals are 3pgenerated by the system itself asynchronously. Theintegrated circuits for X-ray or y-ray spectrometers available Logicso far [1], [2] provide at the output the analog signalproportional to the energy obtained at the output of peak-and-hold using analog multiplexers and buffers, while A/Dconversion is performed externally, typically with multi- Figure1 AtypicalapplicationoftheA/Dpipelineconverterchannel analyzers. The reason for this is that that clock The key concept in the proposed structure is that asignal required for on-chip A/D conversion would introduce . Asevere disturbances that would degrade the noise plinaD behave aspacominato lgc Thquence ofperformance of the front-end circuit. On the other hand, A/D ockrsignal it iv proper tint the sequenceaofconverters, which inherently do not require a clock signal if operations. If itiS provided that the operations arethe input signal iS already sampled, such as full flash A/D copee wihi a cetiieso,thntecokcnbthe input signal is alread sampled,suchar removed, obtaining the proposed structure. The proposedconverters, do not achieve a sufiIcient accuracy for I I I Icovres do no aciv a sufcin acurc novel concept requires an improved block design in order tospectrometry. Therefore, a fast and accurate A/D convertercapable of operating without a clock signal would be guarantee timing operation.extremely useful to achieve fully integrated X-ray or y-ray

0-7803-9390-2/06/$20.00 ©2006 IEEE 5355 ISCAS 2006

* ResM sVThH j

Soc Analog EOCDelay

ThH / _ _ | . \/ThL J

Reside RsEu esdeResiu _vResde WResde _SResde Residu \ .

Figure 2 Block diagram of the A/D converter

The 1.5 bit conversion stage consists of a flash ADCTABLE I A/D CONVERTER SPECIFICATION with a resolution of 1.5 bits, a DAC, an adder and a gain

___________________________ ___________ - stage with a gain equal to 2. The ADC is realized with twoParameter Value continuous-time comparators with hysteresis [4], which

___________________________ ___________ - compare the input signal with two thresholds. The hysteresisResolution 10 bits has been introduced to avoid oscillations when the inputDNL <0.5 LSB signal is very close to the threshold. Such a comparatorINL <0.5LSB hysteresis can be introduced since with the digital error________________________ __________. correction technique, the actual value of the ADC thresholdConversion time < 1 ps - voltage does not affect the accuracy of the complete A/D

converter. On the other hand this strongly reduces the timeII. CIRCUITDESCRIPTION required for the comparator decision, in order to speed-up

Figure 2 shows the block diagram of the proposed A/D also the residual calculation, and then the operation of theconverter. The circuit consists of nine conversion stages, an next stage. The amplitude of the hysteresis is 10OOmVarray of flip-flops and a ripple-carry adder. Digital centered on the threshold voltage level.correction is implemented to reduce threshold voltage b1 b1 +variation sensitivity. The key requirement of the circuit 7 6design is to ensure the operation completition with the b15 b14 +scheduled time slot. In details, it can be seen that the b13 b12±residual calculation is the most critical operation, since itb1 b,±produces the signal for the following stage. The complete l o+conversion time slot is then obtained as the sum of the bog bos +residual calculation of each stage. Notice that this operation = = = = = b,07 b,06 =±requires that the comparator decision is taken as soon asb0 b4±possible, and it does not change during transient. This has to () (4be achieved with careful circuit design. b03 b02±

Each of the first eight stages resolve 1.5 bits, while the V T 1 T T T b01) b0last one is a 2-bit flash ADC. The output bits of the nine 009 000o07 006 j 005 004 0o3 002 oi [ Ooostages are sampled by a register of flip-flop controlled by a Fgr rnil fteerrcreto oidelayed version Of the start-of-conversion signal and addedfollowing the scheme reported in Figure 3 in order to The DAC consists of three transmission gates, whichachieve the final 10 output bits with digital error correction connect three reference voltage values to the output. The[3]. The schematic diagrams of one of the first eight stages adder subtracts the voltage generated by the DAC from theas well as ofthe last stage are shown in the insets of Figure input signal, generating the residual voltage, which,2. amplified by two, represents the input signal of the next

stage. The adder and the gain stage are realized with anoperational amplifier in close-loop configuration as shown

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in Figure 4. The two resistors used in the feedback path are To calculate the maximum conversion time and henceequal. determine the delay required for sampling the output bits in

the flip-flops, the converter was simulated with severalThe Ast sag e pipeline converteiamplea2obi different static input signals (this is the case under theflasth ADCtmaes upiof thre ontinuustimecmaaour hypothesis that the input signal is sampled). With all the

winthrhyst input signal values and in all the process corners theintervals. conversion lasts less than 500ns. It was considered as theconversion time the time interval after which all theVin - + \ eighteen bits, coming from the nine stages of conversion,

Residue become still. At this point the data passed by the array ofR ' flip-flop to the adder are correct.

VDAC/0.3

R ~~~~~~~~~~~~~~~~~~0.2

0.1

Figure 4 Schematic of the adder and gain stage 0 0

As already mentioned, the eighteen bits provided by the 7--J0.1nine conversion stages are sampled by an array of flip-flops z 0.2and provided to the digital adder. The signal used to drive Z -0.2the flip-flops is obtained by delaying the start of conversion 03signal through an analog block. This block consists of anRC network followed by a comparator equal to those used -0.4in the main ADC. The amount of delay has been selected in -order to match the delay of the pipeline chain, thus ensuring -05 2 4 6 8 100 10that the output bits are stable when they are sampled by the ° Output Codeflip-flops.

Figure 6 INL of the proposed A/D converterIII. SIMULATION RESULTS

The proposed A/D converter has been intensivelysimulated at transistor level in order to determine theintegral (INL) and differential (DNL) non-linearities as wellas signal-to-noise ratio (SNR).

0.5

o 200 400600 800 1000 1200~~~~~~~~2

0.4

0.3..

0.2

Z 0.1

-j~~~~~~~~~~~~~~~~~~~~~~~~~~~6

-03

0 2 3 4 5 6 7 8 9 10-04 Frequency [HzI0.5

0 200 400 600 800 1000 1200 Figure 7 Spectrum ofthe proposed A/D converter output signalOutput Code

Finally, Figure 7 shows the spectrum of the A/DFigure 5 DNL ofthe proposed A/D converter converter output obtained by applying a sampled sinusoidal

input. The obtained SNR is equal to 59.6dB, correspondingto 9.6 effect1ve bits of resolution. The power consumptioninput of the ADC a ramp with a 0.25 LSB amplitude step. othsfrtpeinayccualmlmnainis3 V

Figure 5 and Figure 6 show the achieved results. Both INL fro a 3XVpwrspl.Tepwrcnupinian ,N r oe hn05LBoe h hl nu mainly due to the circuits required to provide the reference

signal range. voltages to the DAC.

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IV. LAYOUT (AR 7 0.17 (4)The proposed A/D converter was designed in a standard R ) 13130

0.35ptm CMOS technology. Figure 8 shows the lavout of the Therefore, the mismatch on the ratio between the twochip whose active area (without pads) is 2.24mm The chip resistors R in Figure 4 which determine the gain G of theis presently being fabricated. residue amplifier, is given by:

l ll1|111 1 l ( ~~~~~~~~~~~~AGAR Al?

g-l 1| | 1|sl s *|l||_s==l | ~~~~~~~~~~~~~~~~~~~~(5)l_l~ ~ ~~~ ~ ~ ~~~~~~~~~~~~~~~.~ (Tl AR, J2,,,.0.1 0.24

which is lower the maximum allowable value.

Figure 8 Layout of the proposedA/D converter

The eight 1.5 bit stages and the last 2 bit flash ADC canbe observed in the layout. The flash ADC is much smaller________than the 1.5 bit stages because it does not include the Lresidue amplifier. Particular attention was devoted to thelayout of the resistors used in the closed-loop amplifierbecause they generate the residue, which in turn determines Figure 9 Layout ofthe 1.5 bit stagethe accuracy of the A/D converter. Each resistor consists ofeight 12.5kQ stripes for a total value of 1OOkQ withdummies resistors all around to minimize the border effects V. CONCLUSIONS[5], as shown in Figure 9. High resistive polysilicon was In this paper a novel A/D converter architecture for low-used to realize the resistors because it features the lowest noise, self-triggered applications, such as X-ray or y-raymismatch factor among the materials available in the used spectrometry is presented. This converter, assuming that aCMOS technology. The mismatch between two equal sampled input signal is provided, operates without the clock

resistors*can be written as: signal, which is usually source of severe disturbances in(ARA AR low-noise circuits. The A/D converter was designed in a

C6 = /(1) standard 0.35ptm CMOS technology and the chip areaR sW-L- without pads is 2.24 mm2. The time required for a

where W is width of the resistor, L is the length and AR is conversion is in the worst case lower than 5OOns. The powerthe mismatch parameter (for the high resistive polysilicon consumption of the circuit is 39mW from a 3.3V powerused AR= 7). supply.

To calculate the maximum allowed mismatch between REFERENCESthe two resistor of the first stage of the pipeline, which isobviously the most critical, the following relation was used: [1] "Proceeding of the 11th International Workshop on Room

Temperature Semiconductor X and Gamma Ray Detectors and

Mismatchm -0 2 (2)1.2 Associated Electronics", in R. James, P. Siffert ed., Nuclearmax 29 Instruments and Methods A, vol. 458, Elsevier Science, 2001.[2] M. Prydderch, P. Seller, "A 16 channel analogue sparse readout IC

Considering a 1.2V input voltage swing, a maximum for Integral", IEEE Nucl. Sc. Symp. and Med. Imag. Conf, 1, pp. 65-mismatch of 2.4%o can be tolerated. Then to determine the 68,1994.width and the length of the resistors the following relation [3] R. van de Plassche, Integrated Analog-to-Digital and Digital-to-was used: Analog converters, 2nd ed., Kluwer, 2003.

( AR 8 A8Z\r A( i\r 8 [4] F. Maloberti, Analog Designfor CMOS VLSI System, Kluwer, 2001.CT (3) [5] A. Hastings, The Art ofAnalog Layout, Prentice Hall, 2005.

where r is one of the eight 12.5kQ stripes of each resistor.Choosing 13pim of width and 13O0pm of length (leadingexactly to 12.5kQ), the obtained value ofa is:

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