A 2.4GHz Fully Integrated CMOS Power Amplifier Using ...

Matsuzawa& Okada Lab.

A 2.4GHz Fully Integrated CMOS Power Amplifier Using

Capacitive Cross-Coupling

JeeYoung Hong, Daisuke Imanishi, Kenichi Okada, and Akira Matsuzawa

Tokyo Institute of Technology, Japan

2010/08/31

1


Contents

Introduction

PA design

Measurement results

Conclusion

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Introduction

PA (Power Amplifier): A circuit used to convert a low-power RF signal into a larger signal of significant power at transmitter

2.4GHz– the frequency band which require no license– various wireless communication standards: WiMAX, WLAN, Bluetooth, etc.

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Introduction

The reason for using capacitive cross-coupling

High reliability of the voltage stress at output end

Using self-biased cascode topology

Area increase by bypass capacitor

Using Cross-coupling Capacitor

Reduce an area of bypass capacitor

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Schematic

In+

VDD

VBias1VBias2 VBias1

In-

VBias3

Out

VBias4

2 : 1VDD

VDD=3.3V

Class-A bias(1st stage), Class-AB bias(2nd stage)

Differential topology for achieving 3dB larger Pout

Impedance matching by L, C, R

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Proposed circuitTo achieve a high output power– Differential topology

– 2-stage configuration

– Transformer

The 1st stage The 2nd stage

Transformer

In+

VDD

VBias1VBias2 VBias1

In-

VBias3

Out

VBias4

2 : 1VDD

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Transformer

out

DD

sat Z

V

P

2

2 ⎟⎠⎞

⎜⎝⎛

=

Relation between Psat & Zout

Theoretical maximum output power Psat

)()( 50412

2332

41

2

22

××

⎟⎠⎞

⎜⎝⎛ ×

=⎟⎠⎞

⎜⎝⎛

=.

out

DD

sat Z

V

P• Turn ratio=2:1• Zout (50Ω)→ ¼ Zout(12.5Ω)

]dBm[4.29]W[8712.0 ==

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Transformer

Measurement and simulation results agree with each other.

-10

-8

-6

-4

-2

0

0 1 2 3 4 5Frequency [GHz]

Max

imum

Ava

ilabl

e G

ain

[dB

]

Sim.Meas.

-180

-120

-60

0

60

120

180


Phas

e [d

egre

e]

Phase(S31) meas. Phase(S32) meas.Phase(S31) sim. Phase(S32) sim.

Coupling coefficient = 0.7Maximum Available Gain(MAG) = -1.05 dBConversion efficiency= =78.5 %10010 10 ×)-1.05dB(

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Proposed circuitTo sustain voltage stress– Cascode topology

– Thick gate-oxide transistors

– Self-biased topology

CascodeSelf-biased cascode

Thick gate-oxide transistor

In+

VDD

VBias1VBias2 VBias1

In-

VBias3

Out

VBias4

2 : 1VDD

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Self-biased cascode

dgdbypass

gdg v

CCC

v+

=

VBias

Vdd

Cgd

Cbypass

vg

vd

vs

Volta

ge

at the 2nd stage

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Loss of Gain Area increase by Cbypass

Alleviation of voltage vgd

Prevention of transistor’sentering to triode region

[ Conceptual diagram of voltage waveforms ]

If Cgs is neglected,

[1] T. Sowlati, et al., “A 2.4-GHz 0.18-µm CMOS Self-Biased Cascode Power Amplifier,” IEEE Journal of Solid-State Circuits, pp. 1318-1324, 2003

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Amplitude adjustment

Voltage waveform

0

1

2

3

4

5

6

7

8

0 0.2 0.4 0.6 0.8 1Time [nsec]

Volta

ge [V

]

Vd2Vg2Vd1

[Self-biased cascode]

• Vg amplitude=19% of the Vd amplitude

• Cbypass=14.5pF2010/08/31

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Gain degradation

24

25

26

27

28

29

30

31

32

-35 -25 -15 -5 5Pin [dBm]

Gai

n [d

B]

Standard cascodeUsing crosscouplingSelf-Biased

Self-biased cascode method degrades the gain compare with standard cascode method using fixed bias voltage.

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Capacitive cross-couplingUsing capacitivecross-couplingSelf-biased cascode

dcgdbypass

cgdg v

CCCCC

v)( −+

−=d

gdbypass

gdg v

CCC

v+

=

Cc is tuned to vg amplitude≒18% of vd amplitudeCgd is reduced, thus Cbypass is decreased

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Amplitude adjustment 2

Pin=5dBmVDD

Cgd

Cbypass

vg2

vd2VBias

-vdCc

vd1

0

1

2

3

4

5

6

7

8

9

0 0.2 0.4 0.6 0.8 1Time [nsec]

Volta

ge [V

]

Vd2Vg2Vd1Self-biased cascode with

capacitive cross-coupling[ ]• Vg amplitude=18% of the Vd amplitude

• Cbypass=8.6pF2010/08/31

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Chip micrograph

Transformer1:2

2nd stage

DC pad

Transformer1:2

DC pad

UsingMIM capacitor(1fF/µm2)

Bypass capacitor Cbypass = 14.5pF→8.6pF

Cross-coupling capacitor Ccc = 1.5pF2010/08/31

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S-parameter measurement results

0

10

20

30

40


S21 [

dB]

Sim.Meas.

-14

-12

-10

-8

-6

-4

-2

0


S22 [

dB]

Sim.Meas.

Measurement results are roughly in accordance with simulation results

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Measuring systemLarge signal measurement setup

N-3.5mm adopter

• Input and output losses are measured separately, and are calibrated from results.

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Large signal measurement result

20

25

30

35

40

1.8 2 2.2 2.4 2.6 2.8

Freqency [GHz]

PAE m

ax [%

], P s

at [d

Bm

]

maxPAEPsat

・ PAEmax ＞ 31 %

・ Psat ＞27 dBm

Near 2.4 GHz

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Large signal measurement result

2.4 GHz

-10

0

10

20

30

40

-30 -20 -10 0 10Pin [dBm]

Pout

[dB

m],

Gai

n [d

B]

0

10

20

30

40

50

PAE

[%]

Pout(Meas.) Pout(Sim.)Gain(Meas.) Gain(Sim.)PAE(Meas.) PAE(Sim.)

・ P1dB = 25 dBm・ Psat = 27.7 dBm・ Gain = 26.5 dB・ PAE1dB = 26.8 %・ PAEmax = 34.3 %

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Comparison of CMOS PAs

[2] [3] [4] [5] This workTechnology 90nm 130nm 180nm CMOS

VDD 3.3 V 1.2 V 3.3 V 3.3 V 3.3 VFrequency 2.4 GHz

P1dB 27.7 dBm 24 dBm 24.5 dBm 27 dBm 25.2 dBmPsat 30.1 dBm 27 dBm - 31 dBm 27.7 dBm

PAEpeak 33 % *32 % 31 %@1dB 27 % 34.3 %Area 4.3 mm2 1.7 mm2 1.7 mm2 2.0 mm2 1.6 mm2

* Drain efficiency

[2] D. Chowdhury, et al., “A Single-Chip Highly Linear 2.4GHz 30dBm Power Amplifier in 90nm CMOS,” IEEE International Solid-State Circuits Conference, pp. 378-380, 2008

[3] G. Liu, et al., “Fully Integrated CMOS Power Amplifier With Efficiency Enhancement at Power Back-Off,” IEEE Journal Of Solid-State Circuits, vol. 43, No. 3, pp. 600-609, Mar. 2008

[4] J. Kang, et al., “A Single-Chip Linear CMOS Power Amplifier for 2.4GHz WLAN,” IEEE International Solid-State Circuits Conference, pp.761-769, 2006

[5] K. An, et al., “A 2.4 GHz Fully Integrated Linear CMOS Power Amplifier With Discrete Power Control,” IEEE Microwave and Wireless Components Letter, vol. 19, No. 7, pp. 479-481, July. 2009

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ConclusionDesigning 2.4GHz PA with high output power

Circuit design

– Using TSMC 0.18µm CMOS process

– High output power：Differential topology, 2-stage configuration, Transformer

– Improvement of withstanding voltage：Cascode, Thick gate-oxide transistor, Self-biased cascode

– Reduce of area for Cbypass：Capacitive cross-coupling

Results

– P1dB = 25.2dBm, Psat = 27.7dBm, PAEpeak = 34.3%

– Needed Cbypass = 14.5pF→8.6pF(41%↓)2010/08/31

A 2.4GHz Fully Integrated CMOS Power Amplifier Using ...

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