A 1.25-V Micro Power Gm-C Filter Based on FGMOS Transistors Operating in Weak Inversion

8/7/2019 A 1.25-V Micro Power Gm-C Filter Based on FGMOS Transistors Operating in Weak Inversion

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100 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004

A 1.25-V Micropower Gm

-C Filter Based onFGMOS Transistors Operating in Weak Inversion

Esther Rodriguez-Villegas, Alberto Yfera, and Adoracion Rueda, Member, IEEE

AbstractThis paper presents a novel linearized transcon-ductor architecture working at 1.25 V in a 0.8- m CMOStechnology with very low power consumption. The special featuresof the floating-gate MOS (FGMOS) transistor are combinedin weak and strong inversion leading to a simplified topologywith fewer stacked transistors and a very low noise floor. Thedesign methodology is thoroughly explained, together with theadvantages and disadvantages of working with the FGMOS tran-sistor. Furthermore, second-order effects arising from nonidealbehavior of the device are analyzed and limits for the perfor-mance are established. Experimental results from a second-orderlow-pass/bandpass filter that was implemented using the transcon-ductor show a tunability of over one and a half decades in theaudio range, a dynamic range of over 62 dB, and a maximumpower consumption of 2.5 W. These results demonstrate thesuitability of the FGMOS transistor for implementing analogcontinuous-time filters, while at the same time pushing down thevoltage limits of process technologies and simplifying the circuittopologies to obtain significant power savings.

Index TermsContinuous-time filter, filters, FGMOS, micro-power, MOS devices, MOS integrated circuits, weak inversion.

I. INTRODUCTION

L OW-POWER and low-voltage (LP/LV) analog and digitalcircuits have been increasing in number and scope in therecent years. This has been mainly motivated by the demand for

portable equipment which must consume as little power as pos-sible in order to extend battery life. Hence, the current circuit

design philosophy is driven by the challenge of retaining circuit

performance while power consumption decreases [1], [2]. Fil-

ters are among the fundamental building blocks in the design of

high-performance LP/LV electronic systems [3], [4]. Depending

on the desired signal processing, several filter realizations exist

[5]. The choice of which of them to use will be determined by

the desired performance.

Weak inversion mode is especially suited for the design

of continuous time micropower filters for several reasons.

The term micropower defines a class of circuits with power

consumption of just a few microwatts. In order to obtain

these power levels, the maximum current that the circuit can

handle has to be very small. The weak inversion region is very

convenient when these requirements have to be met, for the

following reasons.

Manuscript received March 27, 2003; revised September 4, 2003.E. Rodriguez-Villegas is with the Department of Electrical and Electronic

Engineering, Imperial College of Science, Technology and Medicine, LondonSW7 2BX, U.K. (e-mail: [email protected]).

A. Rueda and A. Yfera are with the Instituto de Microelectrnica deSevilla (IMSE-CNM), 41012 Sevilla, Spain (e-mail: [email protected];[email protected])

Digital Object Identifier 10.1109/JSSC.2003.820848

1) Assuming the required power consumption sets a very

small fixed value for the current, the maximum operating

frequency of a single transistor is determined by the gate-

oxide capacitance and . In order to maximize

the device bandwidth, and need to be kept

as small as possible, which implies a small device area.

Assuming the minimum transistor width is chosen, the

designer must choose a length of transistor and level of

inversion in the channel that meets the current constraint.

If the designer reduces the level of inversion, the length

of the transistor may also be reduced. This reduces

and , which in turn increases the bandwidth.2) The maximum voltage drops between the terminals of a

device working in the weak inversion region are smaller

than the values demanded by strong inversion operation.

This allows for lower supply voltages, which also reduces

the power consumption.

3) The fact that the behavior of the transistor is ruled by an

exponential law is very interesting, as its derivative gives

rise to another exponential function. Hence, it is possible

to use nonlinear processing internally to implement linear

state-space equations, in a simple form [6]. By doing this,

the internal nodal voltage excursions can be reduced and

less power is needed to charge and discharge the nodes.

This paper is devoted to exploring the potential of the

floating-gate MOS (FGMOS) transistor operating in weak

inversion for the design of low-voltage micropower contin-

uous-time filters. It will be demonstrated that using FGMOS

in weak inversion as an alternative to conventional MOS

relaxes the constraints relating to voltage supply and frequency

response. Moreover, the increased number of terminals in the

device permits a simplification in the topologies required to

realize a certain mathematical function. This brings with it

a reduction in power consumption, as well as other advan-

tages such as a reduced noise floor. The paper begins with a

reformulation of the Translinear Principle (TP), which is an

ideal technique for implementing nonlinear functions usingcurrents in FGMOS. The advantages of FGMOS for low

voltage design relative to a normal MOS implementation are

then discussed. Section III describes a novel linearized -

integrator topology that is based on the TP and implemented

with FGMOS. Second-order effects, such as degradation of

the power supply rejection ratio (PSRR), and total harmonic

distortion (THD), are analyzed in Section IV. The design of a

second-order low-pass/bandpass filter is shown in Section V,

followed by the experimental results of a prototype working at

1.25 V fabricated in a 0.8- m CMOS technology.

0018-9200/04$20.00 2004 IEEE


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RODRIGUEZ-VILLEGAS et al.: A 1.25-V MICROPOWER - FILTER BASED ON FGMOS TRANSISTORS OPERATING IN WEAK INVERSION 101

Fig. 1. FGMOS translinear loop.

II. FGMOS TRANSLINEAR PRINCIPLE

In 1975, Gilbert applied the name translinearto an emerging

class of circuits whose large-signal behavior was based on

the exponential currentvoltage characteristic of the bipolar

transistor and the linear voltage law ruling a voltage loop [7].

By combining both principles, a nonlinear product of current

densities within different loops can be obtained that serves as

basis for many nonlinear circuits, including wide-band analog

multipliers, RMS-DC converters, vector-magnitude circuits,

etc. [8][12]. The general circuit principle describing the

specific topological arrangement for the exponential devices

which gives rise to the desired mathematical function is called

the Translinear Principle (TP). This section will explain how

the TP can be used advantageously when FGMOS devices are

available [13], [14].

Consider two FGMOS transistors M0 and M1 with grounded

source and a common input, at M0 and at M1, as illus-

trated in Fig. 1. M0 has and M1 has inputs. The Kirchoffs

voltage law in this trivial loop is

(1)

Under the assumptions that the parasitics to the floating gate

are very small compared to the input capacitances and that the

charge trapped during the fabrication process is negligible, thedrain current in these FGMOS devices working in weak inver-

sion saturation mode is given by [15]

(2)

where the weight is given by the ratio between the th input

capacitance and the total capacitance seen by the floating gate,

[13], [14], andparameters , , and have their usual

meanings [16], [17]. Expressing the voltages in the translinear

loop as a function of the currents flowing through the transistors

gives

(3)

where , are the equivalent weights for the inputs and

in transistors M0 and M1, respectively. Rewriting (1) using (3)

and rearranging the terms gives

(4)

This is the nonlinear relationship between currents which is the

objective of the TP. The first advantage of using the FGMOS to

implement the translinear loops is that it is possible to realize

the exponents in the current function with capacitance ratios.

There is no need to use the source terminal in the loop. This fact

is quite significant for two different reasons. The first is that

the voltage requirements are reduced since only a (gate-to-

source voltage drop) is needed in the loop. The second is that thelack of internal nodes simplifies and improves the frequency re-

sponse and eliminates instabilities in certain circuit topologies.

This is because the and capacitors are now tied to

a constant voltage, in contrast to translinear circuits designed

with MOS transistors in which the frequency response exhibits

an undesired and even unstable behavior at a few kilohertz due

to the effects of these parasitics [18].

III. - FGMOS INTEGRATOR USING

TRANSLINEAR CIRCUITS

A. State-Space Filter Equations

The basic mathematical equation ruling the behavior of a- integrator is

(5)

where isa state variable, is the externalexcitation which can

be an independent source, another state variable, or any combi-

nation of these, and parameters and are related to the filter

specifications. In order to make the filter less sensitive to noise

and enlarge the linear range at the input, a fully differential op-

eration is chosen. Equation (5) has to be rewritten as

(6)

Assuming that all these signals are voltages that have been ob-tained from current signals, the following variable change is

introduced:

(7)

where , , are the currents and is a constant. These

parameters are discussed in detail later. Using (7) and applying

the variable change to the right-hand side (RHS) of (6), the final

differential equation is obtained:

(8)

Then, multiplying both sides in (8) by (physically an inte-

grating capacitor) allows the left-hand side (LHS) of (8) to be

identified with the current flowing through this capacitor :

(9)

Equation (8) is symbolized in Fig. 2 using ideal circuit elements.

Referring to Fig. 2, it can be seen that Kirchoffs current law is

evaluated in nodes and according to (8) and (9).

B. FGMOS Blocks

1) Nonlinear Transconductor: The circuit proposed to per-

form the current-to-voltage conversion required by (7) is shown


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Fig. 2. Schematic of an ideal circuit that performs the first-order state-spaceequation (8).

Fig. 3. (a) FGMOS circuit for variable change. (b) Symbol.

in Fig. 3. If the three FGMOS transistors are working in the

strong inversion saturation region and all of them have the same

input weights, given by , ,

the currents flowing through them will be

(10)

(11)

where , and second-order effects, such as

the parasitics to the floating gate, the possible residual charge

trapped in the interface oxide-silicon, and the nonzero outputconductance, have been neglected. If all the constant terms in

the previous equations are grouped together, a new effective

threshold voltage can be defined given by

(12)

Equation (12) shows a reduced value of the threshold voltage

obtained by connecting one of the inputs to the maximum

voltage available in the circuit ( ). This allows the operation

of the transistor in the strong inversion region even under

the tight constraint of the small supply voltage. Taking the

difference between and , and after a few calculations, a

relationship between the differential voltage and current can be

found with the desired general form of (7):

(13)

where is defined as the common-mode current derived from

and . It senses the common-mode voltage of both

voltage signals. Equation (13) represents a nonlinear relation-ship between voltages and currents. From now on, we will refer

to the circuit that realizes (13) as the nonlinear transconductor

(NG-circuit), and its symbol is shown in Fig. 3(b). Each NG-cir-

cuit has a transconductance given by

(14)

2) Circuit: Now, the RHS of (8) can be easily imple-

mented using adding/subtracting currents in a summing node.

The circuit required by (13) has to realize an -type oper-

ator, which can be obtained using the TP previously depicted for

the FGMOS in weak inversion saturation. Each RHS term in (8)

has the general form

(15)

where or , , and .

Multiplying both sides in (8) by a capacitance will give a

dimensionally correct equality if

and

(16)

where are nondimensional factors and are inde-

pendent currents. An alternative form of (8) is thus obtained, as

follows:

(17)

Two currents are required to implement (17), one for the coef-

ficient and another for . A circuit whose output has the general

form of any of the RHS terms in (17) is shown in Fig. 4(a). In

(17), is any differential current associated with a state

variable, is its associated common-mode current, and is

an independent current source. The independent voltage sources

are used for shifting the threshold voltage and controlling the

circuit gain. All the FGMOS transistors have to be working in

the weak inversion saturation region. The corresponding singleoutput currents for the circuit are now given by

(18)

where depends on the constant reference voltage sources at

the inputs of the FGMOS transistors. Considering the same total

capacitance and sizes for all the FGMOS, the input capacitors

are chosen to give the weights in Fig. 4, and all the extra inputs

are set to a value given by an independent voltage source

(except ):

(19)


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Fig. 4. (a) y =p

x circuit with FGMOS-based TL loops. (b) Symbol.

is chosen to ensure weak inversion operation. and

are used for tuning. Hence

and

(20)

Negative values of can be easily implemented with cur-

rent mirrors. The symbol for the circuit in Fig. 4(a) is shown in

Fig. 4(b).

C. Transconductor

The circuit that implements each term in the space-state equa-

tion is shown in Fig. 5. From now on, it will be called the

FG-block. The transconductance of this cell is given by

(21)

where is a constant that scales the magnitude of the cur-

rents coming from the NG-blocks. It is set by the ratio between

the sizes of the output and input transistors in a pMOS current

mirror that provides the input to the square-root block. The fact

that this is a large signal transconductor makes it very useful in

the context of LV designs, since having a linearized structure in-

creases the input range for a given value of distortion, which is

one of the critical factors as the supply voltage is scaled down.

D. State-Space Circuit

The final circuit for implementing (8) is shown in Fig. 6(c).

Two equal G-blocks have been used, one for each voltage-node:

Fig. 5. FGMOS transconductor.

the state variable and the input voltage . The G-block shown

in Fig. 6(a) and (b) is just an FG-block with an added cascode

output stage that provides the differential currents. It can be

shown that the use of cascode FGMOS transistors improves the

output resistance (with all the consequences that this fact has in

the frequency response of a higher order filter designed with it).

Also, the output swing is enlarged and the common-mode feed-

back circuitry (required due to the fully differential structure) is

simplified. One of the inputs to each transistor is connected to

the outputof the common-mode feedback block (CMFB) shown

in Fig. 7. The CMFB consists of a differential pair whose input

FGMOS transistor Mf1 senses the value of the common mode

at the output and compares it with a reference generated by the

weighted addition of and ground in Mf2. If they are dif-

ferent, the difference is amplified and corrected by the negative

feedback. The FGMOS devices at the input of the CMFB are

also advantageous because one of their inputs can be used to

generate a reduced effective threshold voltage. This makes it

possible to have high enough bandwidth to maintain stability,

even under low supply voltage constraint.

IV. SECOND-ORDER EFFECTS

A. Offset and Nonlinearities

The currents injected into the integrating capacitors could

suffer deviations from their ideal behavior and expressions,

mainly caused by the following.

1) mismatch between the input capacitances, and the effects

of the parasitics ( );

2) mismatch between the transistors ( and );

3) output resistances (degradation of the square and expo-

nential laws);

4) dependence of the parameter on gate voltage ( ).

This section will focus on the analysis of how these effects can

affect the performance of the transconductor.

1) Mismatch Between the Input Capacitances and the Ef-

fect of the Gate-to-Drain Coupling in Diode-Connected Transis-

tors: If mismatch between the input capacitances is taken intoaccount, the currents given by (10) and (11) have to be rewritten

as

(22)

(23)

where the parameters represent the percentage of mismatch,

is the common mode of and , and the difference

between both of them. These expressions also take into account


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Fig. 6. Differential transconductor. (a) G-block. (b) Symbol. (c) Implementation of equation (6).

Fig. 7. Common-mode feedback circuit.

the deviations of the effective threshold voltages with respect to

their nominal values. Now

and

(24)

In the square-root block, the influence of mismatch will be

demonstrated through the exponents of the currents in the

nonlinearfunctions since they will differfrom the expectedideal

values. However, there will be another cause contributing to this

variation: the gate-to-drain parasitic coupling in thosetransistors

that have one of their inputs connected to drain. Both sources of

error canbe studied together since theeffect they havein thefinal

response is qualitatively the same. The general expression for

the weights, when all these deviations are taken into account, is

(25)

Fig. 8. THD versus the common-mode signal and the variation in theexponents of I and I . [Equation (26), A = 0 : 2 5 V].

Therefore, the new function implemented by the circuit

is

(26)

2) Mismatch Between the Transistors: Mismatch between

the transistors will cause a different multiplicative constant for

the currents, which can be included in the value of .


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TABLE IFORMULAS FOR THE DIFFERENT PARAMETERS USED IN (26)(32)

3) Output Resistance: The main contribution to degrada-

tions in the output resistance in the FGMOS is the capacitive

coupling between drain and gate. For the diode-connected tran-

sistors, it has been analyzed previously in (25). In the case of the

output transistors, their output resistances have been improvedby cascoding, hence their influence will be negligible.

4) Dependence of the Parameter With Gate Voltage: The

dependence of the parameter with the voltage at the floating

gate of the transistors generating and can be taken into

account by using the following equation to model it instead of

:

(27)

(28)

can be considered as constant since the dependence with the

differential input is weak (it is scaled by the percentage of mis-

match, and also is very small compared to 0.5).

Taking all the previous considerations into account and after

a few laborious derivations, the following conclusions can bedrawn.

1) Mismatch causes an offset, the value of which can

be calculated using the previously derived expressions to be

approximately

offset

(29)

The magnitude of this offset depends upon the common mode

of the signal through . Definitions for those variables that have

not been defined previously are given in Table I.


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Fig. 9. Second- and third-order harmonics when the exponents x and x [Equation (26)] change in a different form in the negative and positive part of theNG-block ( x p = 0 : 0 5 ).

Fig. 10. Offset versus different values of the exponents x and x for G =8 e 0 1 0 A = V.

2) There isvariation inthe gain ofthe block. The new gain is

(30)

3) The second-order harmonic should be zero, since the

structure is fully differential. However, due to mismatching,

now it is

HD2

(31)

4) The third-order harmonic, which is a source of intermod-

ulation distortion, can be expressed as

HD3

(32)

All these analytical results are illustrated in Figs. 811 using thedesign values of the fabricated prototype. Simulations of the cir-

cuit were also run for different values of mismatch in order to

verify the validity of these equations and surfaces. They were

consistent with the analytical results. The total harmonic distor-

tion (THD) due to the variations in the exponents (but in ab-

sence of mismatch) is shown in Fig. 8. The deviations in the

exponent of the linear term in the NG-block will be the main

source of distortion. This is smaller than 1%, and itcan be as low

as 0.2%, provided that the common-mode signal is under 1 V.

(On the other hand, it has to be under 1 V to prevent the output

from saturation.) Figs. 911 show the different harmonics that

result when not only one of the exponents differs from the ideal

value, but the deviation is different in the positive and the neg-ative parts of the circuit (subscripts and , respectively). The

second harmonic will dominate if mismatch exists between both

the parts. The figures show that the main source of distortion is

the changes in the exponent . Hence, special care was taken

when the prototype was designed in order to minimize the value

of the parasitics as well as to match both the blocks (mainly the

inputs involved in the ratios generating the linear term in the

NG-block). The offset when is shown in Fig. 10. Again,

it is important to keep under control the mismatch between the

capacitors that affect the exponents that set the state-space cur-

rents, otherwise the offset could be a significant term. In any

case, will always be smaller than 1 and this will reduce its


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Fig. 11. Second and third-order harmonics versus input amplitude and deviation in the exponent of I when a mismatch of 2% is considered in the otherparameters.

Fig. 12. Differential gain when the power supply is changing, versus the

percentage of mismatch ( " ) in one of the capacitances connected to V andin the multiplicative constant for every term in the state-space equation.

effect. All these figures have been obtained for an input ampli-

tude V, a common-mode c urrent o f 225 n A, a nd

a common-mode voltage of 0.625 V. An example of the nonlin-

earities that arise when different input amplitudes are applied is

shown in Fig. 11. Again, the matching in the exponents of

and is the important factor to take into account. Hence, in

general, the THD will be dominated by the second harmonic,

even when the structure is fully differential. This term is mainly

the consequence of the mismatch between the exponent of the

singleoutput currents when they are processed by the NG-block,

so the capacitances involved in this ratio have to be designed

carefully. Furthermore, the parasitics should be minimized, or

at least they should be as equal as possible in both single sides.

B. PSRR+

The study of how the variations at the positive voltage supply

could affect the performance is also important as is con-

nected to some FGMOS inputs. These connections were re-

quired either to scale up the values of the currents [(19)], or to

scale down the effective threshold voltage [(12)]. Taking mis-

match into account, (8) gives rise to two new equations for the

positive and negative side:

and

(33)

Considering the case when the input signal is zero (this is valid

as is taken as the input), only the coefficients have to be

determined. If is the sum of all the relative weights for

inputs connected to , would be given by

(34)

Whenever the voltage supply variations are small enough com-pared to the nominal value ( ), the variation in the differ-

ential output when changes is

(35)

(36)

Hence, the PSRR will depend upon the percentage of mismatch,the transconductance values, and also the common-mode level

at the output. This has been an approximated analysis that only

takes the dependence of the transconductance values to

into account. Other possible PSRR+ contributions common to

any other structures using p current mirrors have been ignored.

This analysis only takes into account the contribution of the

FGMOS on the total PSRR+. The nonzero differential gain

when different parameters changed with respect to their ideal

values is shown in Fig. 12, where represents the percentage

of mismatch. (The variable inside the parentheses shows the

parameter it is associated with.) The PSRR will depend on

the differential gain, fixed by the transconductance values,


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Fig. 13. Second-orderfilter circuit withthe proposed FGMOS transconductor.

Fig. 14. Photograph of the second-order prototype.

and the output resistance. For example, the PSRR+ would be

36 dB for a differential gain of 100, and ,

. The graph has been obtained for a

value of time constant equal to 1 ms. Different percentages

of mismatch were introduced in the netlist of the filter and

HSPICE simulations were run for each different one. The

values of PSRR+ obtained were in agreement with those shown

in Fig. 12.

V. SECOND-ORDER FILTER PROTOTYPE

The design procedure described in previous section was used

to implement a second-order filter prototype. The frequency

response of the filter was specified to be in the audio frequency

range. The power supply, for this application, is less than

1.25 V, in a 0.8- m CMOS (AMS CXQ) technology with

nominal values for the threshold voltages of V and

V. The starting point for the design was thefollowing equations:

and

(37)

Hence, the frequency parameters and maximum gains for the

low-pass and bandpass outputs and , respectively, were

(38)

Fig. 15. Experimental (a) LP and (b) BP filters transfer functions. Peakfrequency programming.

The circuit realizing (37) is shown in Fig. 13, where

(39)

(40)

The and tuning can be performed through either the refer-

ence voltages or the independent current sources. The circuit is

composed by two equal capacitors and four transconductors

designed according to the filter specifications. For this applica-

tion, the relatively low-frequency range requires high output re-

sistances in order to preserve the low time constants of the filter.

A value of 3.4 pF forcapacitors waschosen. For theNG-circuits,

A V for the M1M3 FGMOS transistors in Fig. 4and 50- and 100-fF input capacitors were chosen for the 0.25

and 0.5 weights, respectively. For the circuits in Fig. 3,

the FGMOS transistors were sized to give A V ,

A V , and A V . These different

aspects add a multiplicative factor to the coefficients which

has been omitted in the equations for simplicity. A photograph

of the final circuit layout is shown in Fig. 14. The total area

was 0.23 . The chip was tested with spectrum analyzers

HP3589A and HPSR770. Fig. 15(a) and (b) represents the LP

and BP transfer functions. The distortion for the LP function can

be observed in Fig. 16, for a sinewave input signal of 200 Hz in

a filter with cutoff frequency of 1 kHz. The maximum value was


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Fig. 16. THD versus differential input amplitude in the LP filter.

Fig. 17. Q-programming for (a) LP and (b) BP functions for f = 0 : 7 5 kHz.

dB for half range of the power supply. Figs. 17 and 18 show

the quality factor and gain programming for both transfer

functions, respectively. The noise floor is shown in Fig. 19. The

cursor marks the output for a single input amplitude of 0.1 mV

which is used as the reference. The performance is summarized

in Table II. The experimental results were in agreement with the

simulations. For detailed information regarding the simulation

and modeling of circuits that include FGMOS transistors, refer

to [13] and [14]. The deviations in gain, , and cutoff frequency

Fig. 18. Gain-programming for (a) LP and (b) BP functions forf = 0 : 7 5 kHz.

Fig. 19. Noise floor. Cursor mark in an input amplitude of 0.1 mV.

were smaller than 10% with respect to the nominal values. The

values of distortion and PSRR+ were also below the limits pre-

dicted by thetheoreticalstudies carried out in Section IV. Taking

into account thetradeoff between thesupply voltage, powercon-

sumption, input range, and signal-to-noise ratio, the overall per-

formance of thenew filter designwas seen to be superior to other

existing realizations [19]. This is a direct consequence of using

FGMOS technology.


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TABLE IISUMMARY OF THE SECOND-ORDER FILTER PERFORMANCE

VI. CONCLUSION

A second-order wide-range 1.25-V micropower contin-

uous-time filter has been presented. The performance of the

system has been obtained by exploiting the special features

of the FGMOS transistor. The advantages of the device have

been illustrated with this particular topology and are listed as

follows.

1) The operating point at the gate of the transistors can be

shifted. This allows for operation of the device in any

region that thedesigner wishes, irrespective of thedc levelof the effective input, because one of the inputs provides

a bias voltage.

2) The translinear loops can be implemented without using

the source terminal. Only two transistors have to be

stacked to get the desired function, with all the implica-

tions this has for low voltage design.

3) Fewer devices are needed to get a nonlinear ratio between

currents thanks to the different possible weights in the

transistor.

4) The functions can be programmed by using the different

inputs in the transistors.

5) The common mode sensing and feedback are simpler to

implement.

The main drawbacks are a larger PSRR+ and THD due to

the mismatch between the input capacitances in the FGMOS

devices. The performance of this filter proved successfully the

suitability of the FGMOS to implement very low-power weak

inversion filters, and showed that it is a powerful device to easily

implement and control complex nonlinear functions.

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[9] R. Konn and R. Genin, High-performance aperiodic frequency multi-plying, Electron. Lett., vol. 15, no. 6, pp. 187189, 1979.

[10] R. F. Wassenaar, E. Seevinck, M. G. van Leeuwen, C. J. Speelman, andE. Holle, New techniques for high-frequency RMS-to-DC conversionbased on a multifunctional V -to- I converter, IEEE J. Solid-State Cir-cuits, vol. 23, pp. 802815, June 1988.

[11] D. R. Frey, Explicit log-domain root-mean-square detector, U.S.Patent 5,585,757, Dec. 17, 1996.[12] J. Mulder, A. C. van der Woerd, W. A. Serdijn, and A. H. M. van Roer-

mund, An RMS-DC converter based on the dynamic translinear prin-ciple, IEEE J. Solid-State Circuits, vol. 32, pp. 11461150, Apr. 1997.

[13] E. Rodrguez, G. Huertas, M. J. Avedillo, J. M. Quintana, and A. Rueda,Practical digital circuit implementations using nMOS threshold gates,

IEEE Trans. Circuits Syst. II, vol. 48, pp. 102106, Jan. 2001.[14] E. Rodriguez-Villegas, Low voltage and low power analog and digital

design with the floating gate MOS transistor (FGMOS), Ph.D. disser-tation, Univ. Seville, Seville, Spain, 2002.

[15] B. A. Minch, Analysis, synthesis, and implementation of networksof multiple-input translinear elements, Ph.D. dissertation, Calif. Inst.Technol., Pasadena, 1997.

[16] E. A. Vittoz, Analog VLSI signal processing: Why, where, and how?,Analog Integrat. Circuits Signal Processing, vol. 6, pp. 2744, 1994.

[17] Y. Tsividis, Operation and Modeling of the MOS Transistor. New

York: McGraw-Hill, 1987.[18] R. M. Fox and M. Nagarajan, Multiple operating points in a CMOSlog-domain filter, IEEE Trans. Circuits Syst. II, vol. 46, pp. 705710,June 1999.

[19] N. Krishnapura and Y. P. Tsividis, Noise and power reduction in filtersthrough the use of adjustable biasing, IEEE J. Solid-State Circuits, vol.36, pp. 19121920, Dec. 2001.

Esther Rodrguez-Villegas graduated from the De-partment of Physics, University of Seville, Seville,

Spain, in 1996, where she received the Ph.D. degreein 2002.

In 1997, she received a professional researchgrant from the Spanish government and joined theMicroelectronic National Centre (CNM), whereshe worked for six years. There she was involvedin several successful international industrial andESPRIT projects. From 1999 to September 2002,she was an Assistant Professor at the University of

Seville. In 2000, she started a collaboration with the Circuits and Systemsgroup at Imperial College London, U.K., involved in biomedical projects. SinceOctober 2002, she has been a Tenure Lecturer in the Department of Electricaland Electronic Engineering, Imperial College London.

Dr. Rodrguez-Villegas chaired the Biomedical Circuits and Systems track atthe IEEE International Symposium on Circuits and Systems (ISCAS) in 2003.She is also part of the technical committee of the 2004 IEEE International Con-ference on Electronics, Circuits and Systems (ICECS).


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Alberto Yfera received the Ph.D. degree from theDepartment of Electronics and Electromagnetism,University of Seville, Seville, Spain, in 1994.

He joined the Department of Electronics and Elec-tromagnetism, University of Seville, in 1988 as anAssistant Professor. In 1991, he became an Assis-tant Professor in the Department of Electronic Tech-nology, University of Seville, where he became anAssociate Professor in 1998. In 1989, he became a

Researcher in the Department of Analog Design, Na-tional Microelectronics Center (CNM), now the In-stitute of Microelectronics at Seville (IMSE). He has participated in researchprojects financed by the Spanish CICYT and in ESPRIT Projects. He has pub-lished technical papers in main international journals and conferences. His cur-rent research interests include analysis and design of analog integrated circuitsand systems for signal processing, biomedical circuit applications, and devel-opment CAD tools for analog circuits.

Adoracion Rueda (M87) received the Ph.D. degreefrom the University of Seville, Seville, Spain, in1982.

From 1984 to 1996, she was an Associate Pro-fessor with the University of Seville, where she isnow a Professor in electronics. In 1989, she becamea Researcher in the Department of Analog Design,National Microelectronics Center (CNM), now theInstitute of Microelectronics at Seville (IMSE). She

has participated in several research projects financedby the Spanish CICYT and by different programs ofthe European Community. She has published about 135 papers in international

journals and major conferences or books. Her research interests currently focuson the areas of design and test of analog and mixed-signal circuits, behavioralmodeling of mixed-signal circuits and development of CAD tools.

Dr. Ruedawon the Best Paper Award of the 10th IEEE VLSI TestSymposiumin 1992.

A 1.25-V Micro Power Gm-C Filter Based on FGMOS Transistors Operating in Weak Inversion

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