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Transcript of A 10Gb/s Eye-Opening Monitor in 0.13 m CMOS · A 10Gb/s Eye-Opening Monitor in 0.13 ... • Jose...
A 10Gb/s Eye-Opening Monitorin 0.13µm CMOS
B. Analui1, A. Rylyakov2, S. Rylov2, M. Meghelli2, and A. Hajimiri1
1. California Institute of Technology, Pasadena, CA2. IBM T. J. Watson Research Center, Yorktown Heights, NY
OutlineOutline
•• Motivation Motivation •• EyeEye--Opening Monitor Opening Monitor
––ConceptConcept––ArchitectureArchitecture
•• Prototype MeasurementPrototype Measurement•• ConclusionConclusion
Adaptive Equalization
Modal DispersionModal Dispersion
Multi-mode Fiber (MMF)
Modal Dispersion is the dominant source of ISI in MMF
Output of over 800m MMF @ 10Gb/s
BER > 10-5
EqualizationEqualization
3-tap Transversal (FIR) Filter
in
out
MMF
BER ≈ 10-5
BER < 10-12
*H. Wu, et al. [ISSCC’03] *S. Reynolds, et al. [ISSCC’05]
coefficients
Adaptive EqualizationAdaptive Equalization
Advantages of AdaptabilityAdvantages of Adaptability• Equalization of unknown channel response
– MMF: fiber length or launch condition
• Adjustments to channel response variations
inerror
out
LMS AdaptationWhy is LMS Undesirable?Why is LMS Undesirable?
• error is a function of decision Convergence issues in high BER
• Internal loading of the FIR filter
111 −−− ⋅⋅+= ik
iik
ik xerrorCC δ
Data
Clock
New coefficients
Adaptive Equalizer Architecture
EyeEye--Opening Monitor (EOM)Opening Monitor (EOM)
Objective:Objective:An architecture that evaluates An architecture that evaluates the received signal qualitythe received signal quality
in
outfast link
slow link
EOM AdvantagesEOM Advantages
• Not loading filter internal nodes
• Actual signal quality evaluation
• Choice of algorithm
Monitoring TechniqueMonitoring Technique
Any data transition inside a rectangular mask is counted as error
Eye monitoring algorithm (I) :Eye monitoring algorithm (I) :
Adjust mask size Count & Recorderrors
Mask Error Rate (MER)
stransitiontotalcount errorMER ≡
Eye Opening isthe mask size
for a given MER
EOM is designed such that it can provide:EOM is designed such that it can provide:
• Horizontal Eye Diagram Opening• Vertical Eye Diagram Opening• Two-Dimensional Map of the Eye Diagram
2D Eye Diagram Error Map2D Eye Diagram Error Map
Effective Eye Opening:Effective Eye Opening:Combination of the masks with the same MER
MERMER Effective Eye OpeningEffective Eye Opening 2D Map of the Eye2D Map of the Eye
Effective Eye Openingfor various MERs
The algorithm can judge signal quality based on the 2D error mapThe algorithm can judge signal quality based on the 2D error map..
10-3
10-4
10-5
10-6
10-7
MERMER
VH
VL
φearly φlate
Mask
φearly
0 1 0 0 1 0 1
SH,earlySL,earlySH,lateSL,late φ
latem: Mask mm m m m m m
Mask Error DetectionMask Error Detection
XOR
Variable comparator references
Variable sampling phases
LH SSerror ⊕=
right and left sides of the mask move independently
Asymmetric eye diagramsare captured
Mask Shape SweepMask Shape Sweep
•• 1 control signal steps reference voltages (1 control signal steps reference voltages (vertical openingvertical opening))•• 2 control signals independently step sampling phases (2 control signals independently step sampling phases (horizontal openinghorizontal opening))
Total number of masks that can be measured:
7 x ( 15 + 15 ) = 210 e.g. 600 with off-chip references
= 3.4ps phase resolution @ 10Gb/s= 3.4ps phase resolution @ 10Gb/s7-level differential DAC
15-levelPhase rotator
100ps
30
VH
VL
Sampling Clocks
data VH
VLdata
VBVB VB
CML Buffer
dataVHVL
DACVcontrol
next_ref +VH
-VH
-VL
+VL
Vertical OpeningVertical Opening--ComparatorComparator
Swapping references
VBVB
x7
s0
s6
s6s0
DAC
Comparator
verticalopeningcontrol
VH VL
(shift registers not shown)
full-rate clock
I Q
/2
Q15
15
I
s0
VBVBx15
s0 s14
s14
Horizontal OpeningHorizontal Opening-- RotatorRotator
φout φout
φ1 φ2 φ2φ1
Phase Interpolator-core
φ φ
full-rate clock
I
Q
I
φearly
φlate
Each of the φearly and φlatecover half of the eye
φφearlyearly φφlatelate
MS-DFF2
MS-DFF1
D2
D1 Q1
Q2
D
Complete ArchitectureComplete Architecture
logicretime
/16
logicretime
/16
Combine/M
dataVH
clock
DAC
I Q
D Q
D Q
D Q
D Q
M=1, 4, 16, 64
sel0 sel1
earlyearly
latelate
QVcontrol
next_ref next_φearly
phase set registers
next_φlate
error_out
clock_out
DFF
DFF
DFF
DFF
I
φearly
φearly φlate
φlate
φ φ
horizontal openingcontrols
/512
/2
VL
Chip Layout Chip Layout
Slicer
DFFs
/2 &rotators
CMOS
660µm
400µm
Data
Data
Clockclock_outerror_out
VH VL
next_φlate
next_φearly
OutlineOutline
•• Motivation Motivation •• EyeEye--Opening Monitor Opening Monitor
––ConceptConcept––ArchitectureArchitecture
•• Prototype MeasurementPrototype Measurement•• ConclusionConclusion
Adaptive Equalization
Phase Rotator MeasurementPhase Rotator Measurement
Add Jitter 10.0GHz
PRBS Source
clock
data
data
next_φlate next_φearly
error_out
Spectrum Analyzer
clock_out
VH VLPower Supply
EOM chip
Oscilloscope
Trigger
Oscilloscope
clock delay
∆t
∆t
delay line
Accumulated clock_out
40ps 80mV~50ps
3MHznext_φlate
10GHzclock
φlate covers half of the eye
150mv
φ early
,0 φlate,0φ early
,14
φlate,14
10Gb/s 231-1 with 40ps peak-to-peak jitter
20ps
500m
v
500m
v10µs50µs
error_out error_out (zoomed)
next_φearlynext_φlate
next_φearlynext_φlate
Error frequency increases
Qualitative Eye OpeningQualitative Eye Opening
• error_out frequency (MER) increases as mask gets wider
no-error zone
0 15
120mVVH - VL
10GHzclock
Measured eye opening for different input jitterdifferent input jitter
010203040506070
0 10 20 30 40 50 60
1%0.50%0.1%
MERLimited by delay resolution
Desired monotonic response
Measured Eye OpeningMeasured Eye Opening
RateBitratiodivouterrorfreqMER
××
=5.0
_)_(
Peak to Peak Jitter [ps]
Mea
sure
d Ey
e O
peni
ng [p
s]
-6
-5
-4
-3
-2
0 0.5 1-50
-25
0
25
50
-6
-5
-4
-3
-2
0 0.5 1-50
-25
0
25
50
150mv20ps
maximum masksize
10Gb/s 231-1 with 40ps Jitter
horizontal mask size [UI]vert
ical
mas
k si
ze [m
V] Log(MER
) [10-x]
Error diagram
φearly and φlate are stepped separatelyto capture asymmetrical eye shape
Jitter
Measured 2D Error MapMeasured 2D Error Map
000,000,000 Hz
12.5GHz
PRBS Source
clock
data
dataB
next_φearlynext_φlate
error_outVH VL
Pulse Generator
Frequency Counter
Power Supply
5’ SMA Cable
GPIB BUS
EOM chip
Controller
~70dB MER dynamic range~70dB MER dynamic range
-10 -5 0-10
-8
-6
-4
-2
0
MER vs. BER MER vs. BER vd
10
log10BER
log 1
0MER
vd=0.2
VL
VH
=σ21QBER
)2
1(
)2
1()2
1(
σ
σσd
dd
vQ
vQvQMER
−≅
+−
−=
( ){ }LVnoiseprob ≥+0
( ){ }HVnoiseprob ≤+0
vd=0.4
vd=0.6
vd=0.8
Comparators’ Impact Comparators’ Impact
20 40 60 80
0.1
0.2
0.3
0.4
0.5
0.6
-8
-6
-4
-2
t [ps]
vd
G=2.5 f-3dB=8GHz
Input BER=10-12
The expected MER when input BER is 10The expected MER when input BER is 10--1212
with comparator with comparator noisenoise and and gaingainxxbandwidthbandwidth limitationlimitation
{ }
+−⋅
−≅
≠=
Ld
Hd
LH
vtAQvtAQ
SSprobMER
σσ 2)(1
2)(
Log(MER
) [10-x]
VH comparatorVL comparator
t
VL
VH
A(t)
0 0.5 1-15
-10
-5
0
5
10
15
-1.1
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
20ps40mv
input eye12.5Gb/s 231-1 w/ 57ps SJ & 5ft SMA cable
horizontal mask size [UI]
vert
ical
mas
k si
ze [m
V]
Log(MER
) [10-x]
Measured by the EOM
Sampling point [UI] Sampling point [UI]
Measured by commercial BERT
Sam
plin
g th
resh
old
[mV]
before 10% digital error after 10% digital error
Unlike in a BERT, digital errors do not affect the EOM operation
Performance Summary Performance Summary
1-1.5VSupply
275mATotal Current
0.13µm CMOSProcess
50mV-500mVInput
Dynamic Range
68dBMER
Dynamic Range
1-12.5Gb/sData Rate
The EOM die photograph1.7mm
1.7mm
Conclusion Conclusion
• Eye-Opening Monitor:– 2-dimensional map correlated to signal quality– Various optimization algorithms– Evaluates actual signal quality– Special sequences are NOT necessary
• CMOS implementation of the architecture achieves 70dB error dynamic range and operates to 12.5Gb/s
Acknowledgements Acknowledgements
•• Jose Jose TiernoTierno, Thomas , Thomas ZwickZwick, Mike , Mike BeakesBeakes, IBM T J Watson Research Lab.
•• John John EwenEwen, JDSU
•• Jeremy Jeremy SchaubSchaub, , PetarPetar PepeljugoskiPepeljugoski, Dan Friedman, Sudhir Gowda, Jeff , Dan Friedman, Sudhir Gowda, Jeff KashKash, Mehmet Soyuer, Modest , Mehmet Soyuer, Modest OpryskoOprysko,, IBM T J Watson Research Lab.
•• IBM MicroelectronicsIBM Microelectronics
•• Lee Center for Advanced Networking, CaltechLee Center for Advanced Networking, Caltech