A 100 W Decimator for a 16 bit 24 kHz bandwidth Audio ...nagendra/papers/isc10-decfil-sl.pdf ·...
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A 100 µW Decimator for a 16 bit 24 kHz
bandwidth Audio ∆Σ Modulator
Shankar Parameswaran,
Nagendra Krishnapura
Department of Electrical EngineeringIndian Institute of Technology, Madras
Chennai, 600036, India
2010 International Symposium on Circuits and Systems,
Paris, France
Shankar Parameswaran, Nagendra Krishnapura EE, IITM, India
Outline
Brief overview of ∆Σ Modulators & Decimators
Architectural optimizations in decimator to reduce power
Simulation results
Fabricated chip results
Conclusions
Shankar Parameswaran, Nagendra Krishnapura EE, IITM, India
Block diagram - Continuous Time ∆Σ Modulator
Σ
Vin(t)
m bitsfs
+
_
OutputADCm bit
DACm bit
Loop FilterL(s)
Oversampling
Noise shaping
Low resolution internal ADC
Shankar Parameswaran, Nagendra Krishnapura EE, IITM, India
Spectrum of the ∆Σ Modulator output
102
103
104
105
106
−200
−170
−140
−110
−80
−50
−20
10
40
60
Frequency (kHz)
Sp
ectr
al M
ag
nitu
de
(d
B)
Inband
3rd order L(s) , 4 bit ADC, fs = 3.072 MHz
Inband Signal to noise ratio (SNR) = 96 dB
Decimator - Low pass filtering & downsampling
Shankar Parameswaran, Nagendra Krishnapura EE, IITM, India
Decimator requirements
Modulator[1] Decimation Filter
Order 3 Downsampling
Factor
64
Sampling rate 3.072 MHz Passband ripple 0.05 dB
Nyquist rate 48 kHz Passband edge 21.6 kHz
SNR 93 dB SNR 96 dB
Power 90 µW Power < 100 µW
[1] - S. Pavan, N. Krishnapura, R. Pandarinathan, and P. Sankar, "A power optimized continuous-time ∆Σ converter
for audio applications," IEEE Journal of Solid-State Circuits, vol. 43, no. 2, pp. 351 360, 2008
Shankar Parameswaran, Nagendra Krishnapura EE, IITM, India
Block diagram of the decimator
H2(z) 2 H3(z)
H1(z): SINC4
H2(z): First Halfband filter
20
H4(z)16
H4(z): Equalizer
24
S
S
: Scaling block
24 2416H1(z)
4
H3(z): Second Halfband filter
Input Output2
Multistage decimation
Shankar Parameswaran, Nagendra Krishnapura EE, IITM, India
SINC4 filter
SINC, H(z) - 16 tap moving average filter
SINC4, H4(z) - Cascade of 4 SINC filters
Removes quantization noise shaping
Downsampling of 16 - Hogenauer structure
H(z) =1 − z−16
1 − z−1
H(f ) =sin(16πf )
sin(πf )
Shankar Parameswaran, Nagendra Krishnapura EE, IITM, India
SINC4 - Hogenauer structure
Input
Output
Σ+
clk clk clk clk
clk/16
z-1
clk/16 clk/16 clk/16 clk/16
z-1 z-1 z-1
z-1
z-1 z-1 z-1 z-1
++
+
+
+
+
+
+
_ _
+
_
+
_
+
accumulators
differentiators
Σ Σ Σ
Σ Σ Σ Σ
Retiming, Pipelining save 46% power in SINC4
Optimal Datawidth = Bin + k log2N = 20
Shankar Parameswaran, Nagendra Krishnapura EE, IITM, India
Frequency response of SINC4
0 200 400 600 800 1000 1200 1400 1600−250
−200
−150
−100
−50
0
Frequency (kHz)
Magnitude R
esponse (
dB
)
Shaded Area - Noise aliasing bands
Shankar Parameswaran, Nagendra Krishnapura EE, IITM, India
Halfband filters
FIR filters
6 dB bandwidth = fs4
Alternate tap weights are 0
Two halfband filters downsample by 2 each
First halfband filter
Initial filtering10th order
Second halfband filter
Sharper filtering
50th order
Shankar Parameswaran, Nagendra Krishnapura EE, IITM, India
Halfband filter implementation
Polyphase structure, downsampling by 2 within filter
Tap weights in Canonical Signed Digits (CSD)
Example: 0.875 = 2−1 + 2−2 + 2−3 = 20− 2−4
(Reduces Multiplication Complexity)
Nested Multiplication, Horners rule
Example: 2−5− 2−7 = 2−5(1 − 2−2)
(Reduces Truncation Error)
2−1 is dropping a bit in the multiplicand
Shankar Parameswaran, Nagendra Krishnapura EE, IITM, India
Datawidth in halfband filters
q1 bits
q2 bits
N1(f)
N2(f)
R dB
0.5fs0.25fs
Ma
gn
itu
de
(dB
) N1(f ) = 10−6q1
10
N2(f ) = 10−6q2
10
R = 10 logN2
N1
q2 = q1 +R
6
To attenuate a portion of quantization noise floor of a q1=16 bit
signal by 48 dB in some band needs q2=24 bit in the filter.
Shankar Parameswaran, Nagendra Krishnapura EE, IITM, India
Frequency response of halfband filters
0 20 40 60 80 100−120
−100
−80
−60
−40
−20
0
20
Frequency (kHz)
Magnitude R
esponse (
dB
)
Halfband1Halfband2
Shaded Area - Noise aliasing bands
Shankar Parameswaran, Nagendra Krishnapura EE, IITM, India
Scaling block
∆Σ Modulator - Maximum Stable Amplitude (MSA=85%)
Signal swing at modulator output is MSA × fullscale
96 dB SNR at Nyquist rate only with fullscale amplitude
Scale by MSA−1 after first halfband filter
Lesser number of bits from modulator (4) and high
frequency noise prevents scaling at the initial stages of
decimator
CSD & Nested Multiplication
Shankar Parameswaran, Nagendra Krishnapura EE, IITM, India
Equalizer
Droop of SINC4 in the passband
Maximum passband ripple = 0.05 dB
Inverse SINC4 designed with Parks McClellan method
48th order filter
CSD & Nested Multiplication
Shankar Parameswaran, Nagendra Krishnapura EE, IITM, India
Frequency response of the equalizer
0 4 8 12 16 20−2
−1.5
−1
−0.5
0
0.5
Frequency (kHz)
Ma
gn
itu
de
Re
sp
on
se
(d
B)
Equalizer ResponseUnequalized ResponseEqualized Response
0 4 8 12 16 20−0.06−0.04−0.02
00.020.040.06
Shankar Parameswaran, Nagendra Krishnapura EE, IITM, India
Synthesis
Technology: 1.8 V standard cells UMC 0.18 µm CMOS
CAD tools
Design Synthesis - Design Compiler
Place & Route - SoC Encounter
Power Consumption - PrimePower
96.7 µW - ∆Σ modulator input is a tone at 1.6 kHz100 µW - ∆Σ modulator input is a white noise
Active area = 0.46 mm2
Shankar Parameswaran, Nagendra Krishnapura EE, IITM, India
Layout of the fabricated chip
Shankar Parameswaran, Nagendra Krishnapura EE, IITM, India
Picture of the test board
Shankar Parameswaran, Nagendra Krishnapura EE, IITM, India
Measurement results from the chip
Chip works correctly at 1.8 V supply and works reliably
down to 0.9 V at 3.072 MHz
Current consumed with 1.8 V supply = 58 µA (104.4 µW)
Current consumed with 0.9 V supply = 26 µA
Shankar Parameswaran, Nagendra Krishnapura EE, IITM, India
Decimated output spectrum from the chip
0 4 8 12 16 20 24−25
0
25
50
75
100
125
Frequency (kHz)
Spectr
al M
agnitude (
dB
)
Tone at 4.125 kHz
Shankar Parameswaran, Nagendra Krishnapura EE, IITM, India
Conclusion
100 µW decimator for audio ∆Σ ADC
No handcrafted circuits - completely implemented with
automated CAD tools
Works down to 0.9 V supply
50% power reduction with a linear power regulator
Shankar Parameswaran, Nagendra Krishnapura EE, IITM, India
References
S. Pavan, N. Krishnapura, R. Pandarinathan, and P. Sankar, "A power optimized continuous-time ∆Σ
converter for audio applications," IEEE Journal of Solid-State Circuits, vol. 43, no. 2, pp. 351 360, 2008
S. Pavan and P. Sankar, "A 110µW Single Bit Audio Continuous-time Oversampled Converter with 92.5 dB
Dynamic Range" Proceedings of the European Solid State Circuits conference, September 2009.
Ronald E. Crochiere, Lawrence R. Rabiner, "Interpolation and Decimation of Digital Signals - A Tutorial
Review," Proceedings of the IEEE vol. 69, NO. 3, March 1981.
Carol J. Barrett, Low-power decimation filter design for multi-standard transceiver applications, Master of
Science Thesis, University of California, Berkeley.
James C. Candy, "Decimation for Sigma Delta Modulation," IEEE transactions on communications, vol.
com-34, no. 1. January 1986.
Eugene B. Hogenauer, "An economical class of digital filters for decimation and interpolation," IEEE
transactions on acoustics, speech, and signal processing, vol. assp-29, no. 2, April 1981.
Keshab K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, John Wiley & Sons,
1999.
Reid M. Hewlitt, Earl S. Swartzlander, Jr.,"Canonical signed digit representation for fir digital filters," IEEE
Workshop on Signal Processing Systems, 2000,SiPS 2000.
Shankar Parameswaran, Nagendra Krishnapura EE, IITM, India