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I. 

Objectives:  To write a BCD to 7-segment decoder  To describe the use and syntax of User ( Implementation) Constraint File

  To extend the usage of Nexys2 board

II. 

Submission: submit by email within 5 days after the lab. Email subject formatshould be Lab04_XXXX_YYYY_ZZZZ. 

III. 

Background:  FPGA development board reference manual and lectures on VHDL

IV.  Procedure (part A)Write VHDL code for BCD to seven segment decoder and implement it on

 Nexys2 board making use of slide switches as input and one of the 7-segment display as

its output.

V. Exploratory Exercises:1.  Use two seven segment displays to show numbers greater than 9 as two

digit decimal numbers.

2.  To use more than one seven-segment displays you will have to use

advanced technique as data lines are only 8-bit and are multiplexed. Codesnippets are some hints are given in the following:

Help will also be given during the lab.

Code for Clock division:-- clock division block

--divides the clock of 50MHz by 64K i.e. down to ~780 Hz-- to avoid operating seven segment displays at high frequencies (in MHz range) process (clk50)

 begin

if clk50'event and clk50 = '1' then

khertz_count

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-- This block shows an example to illustrate multiplexing output to more than one 7-

segments

-- This block shows how to multiplex output to different 7-segments process (khertz_en, ChangeDigit)

 begin

if khertz_en'event and khertz_en = '1' then

ChangeDigit