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SPICE Device Model SUM110N06-04LVishay Siliconix

This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriatedata sheet of the same number for guaranteed specification limits.

Document Number: 70523 www.vishay.com

09-Jun-04 1

N-Channel 60-V (D-S) 200C MOSFET

CHARACTERISTICS

N-Channel Vertical DMOS Macro Model (Subcircuit Model)

Level 3 MOS

Apply for both Linear and Switching Application Accurate over the 55 to 125C Temperature Range Model the Gate Charge, Transient, and Diode Reverse Recovery

Characteristics

DESCRIPTION

The attached spice model describes the typical electricalcharacteristics of the n-channel vertical DMOS. The subcircuit

model is extracted and optimized over the 55 to 125Ctemperature ranges under the pulsed 0 to 10V gate drive. Thesaturated output impedance is best fit at the gate bias near thethreshold voltage.

A novel gate-to-drain feedback capacitance network is used tomodel the gate charge characteristics while avoiding convergencedifficulties of the switched Cgd model. All model parameter valuesare optimized to provide a best fit to the measured electrical dataand are not intended as an exact physical interpretation of thedevice.

SUBCIRCUIT MODEL SCHEMATIC

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SPICE Device Model SUM110N06-04LVishay Siliconix

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SPECIFICATIONS (TJ= 25C UNLESS OTHERWISE NOTED)

Parameter Symbol Test ConditionsSimulated

DataMeasured

DataUnit

Static

Gate Threshold Voltage VGS(th) VDS= VGS, ID= 250 A 2.1 V

On-State Drain Currenta

ID(on) VDS>5 V, VGS= 10 V 1751 A

VGS= 10 V, ID= 30 A 0.0026 0.0028

VGS= 4.5 V, ID= 20 A 0.0037 0.0040

VGS= 10 V, ID= 30 A, TJ = 125C 0.0044Drain-Source On-State Resistance

a rDS(on)

VGS= 10 V, ID= 30 A, TJ = 200C 0.0058

Forward Transconductancea gfs VDS= 15 V, ID= 30 A 132 S

Forward Voltagea VSD IS= 110 A, VGS= 0 V 0.93 1.1 V

Dynamicb

Input Capacitance Ciss 7380 7500

Output Capacitance Coss 1079 1050

Reverse Transfer Capacitance Crss

VGS = 0 V, VDS= 25 V, f = 1 MHz

616 700

pf

Total Gate Chargec Qg 149 150

Gate-Source Chargec Qgs 25 25

Gate-Drain Chargec Qgd

VDS= 30 V, VGS= 10 V, ID= 110 A

45 45

nc

Turn-On Delay Timec td(on) 67 20

Rise Timec tr 84 135

Turn-Off Delay Timec td(off) 100 80

Fall Timec tf

VDD= 30 V, RL= 0.40

ID110 A, VGEN= 10 V, RG= 2.5

127 150

Reverse Recovery Time trr IF= 110 A, di/dt = 100 A/s 55 75

ns

Notes

a. Pulse test; pulse width 300 s, duty cycle 2%.b. Guaranteed by design, not subject to production testing.c. Independent of operating temperature.

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SPICE Device Model SUM110N06-04LVishay Siliconix

Document Number: 70523 www.vishay.com

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COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED)

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Document Number: 91000 www.vishay.comRevision: 18-Jul-08 1

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