4 Different i a Lamp

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Differential Amplifiers



Contents

DifferentialAmplifiers

Single-ended and Differential Operation

Basic Differential Pair Qualitative Analysis

Common-mode Response

Differential Pair with MOS Loadser e



Contents

Introduction


- One of the most important circuit inventions- Has many useful properties

- -

- Provide logic levels to a digital circuit

ec ves

- Analysis and Design of CMOS differential amplifiers

- Basic differential pair, small signal and large signal behavior

- Common mode rejection for differential amplifiers- Differential pairs with diode-connected and

-



Amplifier With Bias Stabilizing Neg Feedback Resistor

• Single transistor common-emitter or common-source amplifiers often use a bias

stabilizing resistor in the common node leg (to ground) as shown below

– Such a resistor provides negative feedback to stabilize dc bias

– But, the negative feedback also reduces gain accordingly

• We can shunt the common node bias resistor with a capacitor to reduce the negative

impact on gain

– Has no effect on gain reduction at low frequencies, however

– Large bypass capacitors are difficult to implement in IC design due to large area

• Conclusion: try to avoid using feedback resistor R2 in biasing network




• Differential amplifiers are pervasive in analog electronics

– Low frequency amplifiers

– g requency amp ers

– Operational amplifiers – the first stage is a differential amplifier

– Analog modulators

– Logic gates

• Advantages

– Large input resistance

– High gain

– Differential input

– Good bias stability

– Excellent device parameter tracking in IC implementation

• Examples

– Bipolar 741 op-amp (mature, well-practiced, cheap)

– CMOS or BiCMOS op-amp designs (more recent, popular)



Differential Amplifier Topology

• In contrast to the single device common-

emitter (common-source) amplifier with

previous slide, the differential ckt shown atleft provides a better bypass scheme.

– Device 2 provides bypass for active device 1

– Bias provided by dc current source

– Device 2 can also be used for input, allowing

a differential input –

might be current sources (current mirrors)

• The basic differential amplifier topology can

be used for bipolar diff amp design or for

CMOS diff amp design, or for other activedevices, such as JFETs



Differential Amplifier with Two Simultaneous Inputs

• The differential amplifier topology shown at

the left contains two inputs, two active

devices, and two loads, along with a dc

current source

• We will define the

– differential mode of the input vi,dm = v1 – v2

– common mode of the input as vi,cm= ½ (v1+v2)

• Using these definitions, the inputs v1 and v2

can be written as linear combinations of the

– v1 = vi,cm + ½ vi,dm

– v2 = vi,cm – ½ vi,dm

• These definitions can also be a lied to the

output voltages – Differential mode vo,dm = vo1 – vo2

– Common mode vo,cm = ½ (vo1 + vo2)

• Alternately, these can be written as

– vo1 = vo,cm + ½ vo,dm

– vo2 = vo,cm – ½ vo,dm



Single-ended vs. Differential Signals

• Single-ended signal: Measured with respectto a fixed otential t icall round.

• Differential signal: Measured between two

opposite signal excursions around a fixed potential, called a “common-mode” level)



Why Differential?

• In a single amplifier V DD fluctuations appear directly on the amplified signal.

• In a differential pair, if we measure V -V Y

the fluctuations cancel out.



Supply voltage noise reduction

• If V DD varies by ΔV , V out changes bythe same amount. (susceptible to noise on V DD)

• If circuit is symmetric, noise affects V and V Y

but not V X -V Y



Why Differential?

• In a single CS amplifier,the maximum swing is V DD-(V GS -V TH )

• In a differential pair it can be shown that

the swing of V X -V Y can reach 2[V DD-(V GS -V TH )].



Clock Noise Reduction



Other advantages of differential amplifying

• Sim ler biasin

• Higher linearity• Thou h it a ears that differential am occu ies

2x area of single-ended amplifier

su ression of non-ideal effects b differentialoperation results in smaller area than of

a brute-force single-ended design.



Simple Symmetric Differential Pair won’t do!

Good features:

fluctuations,Larger swing.

Ke roblem:

Input signal

common-mode affects

,differential

amplification.



Important Attributes of Differential Pair

1. Max and Min output levels are well defined

DD an DD- D SS

2. Small signal gain is max for V in1 = V in2

then graduallyÆ0 as |V in1 - V in2 | increases

.e., c rcu ecomes non near ,

if input voltage swing increases



Common-Mode Response

in,CM




Current source is implemented with

3

If V in,CM = 0, both M1 and M2 are OFF, ID3 = 0

If V in,CM > V TH , both M1 and M2 turn ON,

ID1 and ID2 increase, V also increases.



V in,CM must be large enough for M3 to be in

saturation

M1,M2 operate like Source Followers: V P increases

as V in,CM increases – must be larger than V b-V TH3

or proper opera on in,CM GS1 GS3 - TH3



V in,CM must not be too large to keep M1 and

M2

from entering Triode Mode

min SS V V I

V V V V V +−≤≤−+

Allowable value of V in,CM

2,



Consequences of Vin,CM going “off range”

• s ong as common mo e vo age s w n

the permitted range, differential gain is

.

• Once too small or too large – gain falls off.

- . .



Common-Mode Input vs. Output Swing

Tradeoff Each drain voltage can go

DD

as low as V in,CM -V TH . n,

the smaller the swing.

Desirable to have V in CM low

Trade-off between V in,CM and differential gain

•

a n o eren a pa r propor ona ovoltage drop across R D

• , in,



Quantitative Analysis:

Two t es of Differential Gains

“Single-ended”:

with respect to

ground.

?)( 21 =−

= out out v

V V al differenti A

21−

inin

?)( 1 == out v

V d SingleEnde A

21 − inin



Current Division Mechanism

V P =V in1-V GS1=V in2-V GS2

Therefore V in1-V in2=V GS1-V GS2

= D1 D2 SS




Assuming that M1 and M2 are both

,

(V GS -V TH )2 = I D/(0.5k n’W/L)

TH

n

DGS V

W k

I V +='

2




Given the inputs and

SS : o ve two

equations with two

transistor currents:

'

2

'

121

22 D Dinin W

I

W

I V V −=−

nn

I I I

L L

+=




( ) ( )21

2

21 22

D DSS inin I I I V V −=−

'

'

n

Lk

( ) 21

2

21 2

2

i.e., D DSS inin

n

I I I V V L −=−−

thatnotingandagainsides bothSquaring

( )2

21

2

2121214

D DSS

D D D D D D

I I I I I I I I I

−−=−−+=




2

( ) ( ) ( )2

21

'4

21

'2

21 4 ininnSS ininn D D

V V L

k I V V L

k I I −+−⎟ ⎠

⎜⎝

−=−

( ) ( ) ( )2

21'

21

'

212

inin

n

SS ininn D D V V

W

k

V V L

k I I −−−⎟ ⎠

⎜⎝

=−

I D1-I D2 is an odd function of V in1-V in2

D1- D2 = w en in1= in2

when |V in1-V in2| increases |I D1-I D2| also increases



Current Division Solution

If V in1≥ V in2 andtransistors in

Saturation:

2

21211 )(')(' ininnSS ininnSS

D V V W

k I V V W

k I

I −−−+=

2


D V V W

k I V V W

k I

I −−−−=



Currents and g m Plot

2


D V V W

k I V V W

k I

I −−−+=

2

21212 )(4

')(4

'2

ininnSS ininnSS

D V V W

k I V V L

W k

I I −−−−=



Currents Plot

If ΔV =V -V becomes lar e enou h

M2 will “steal” all the current.That is, I D2=I SS , and M1 cuts off ( I D1=0).



Common-Mode Analysis

Goal: No common-mode signal at amplifier’s



Goal: No common mode signal at amplifier s

out ut

• amp er s no symme r c,

CM signals will not be fully cancelled out.

• If the DC current source

(biasing the amplifier) is not ideal(that is, has a finite output resistance)

then CM signal appears at

each single-ended output.

Single-ended Common-Mode Response of a



g p

symmetric amplifier

Consider a small-

signal analysis for the- .

Current source is

represente y ts

output resistance RSS




g p

symmetric amplifier

As V in,CM changes so

does V P . As a result,

D ,

and V X and V Y

chan e.

V X - V Y continues to

.




g p

symmetric amplifier

To find V as function

of V in,CM

we may do a

“half circuit analysis”,

splitting RSS into two

parallel 2 RSS resistors,

,

connect transistors in

arallel as shown .

Single-ended Common-Mode Gain of a



symmetric amplifier assuming λ =0 and γ=0

Y X out CM V

V V V A ===

D

CM inCM inCM in

R−=

2/

,,,

SS m R g +)2/(1

M1+M2 has

twice the width

,

therefore g m is

.

Most Primitive Differential Amplifier: Resistor



p

in lace of current source

. DD , 1 2 .

µnC ox = 50µA/V2, V TH = 0.6V, λ = 0, γ = 0, RSS = 500Ω

ecause D1

= D2

= . m , we ave:

V V W

I V V TH

DGS GS 23.1

2 121 =+==

Loxn



“Resistor current source” example

V V W

I V V TH D

GS GS 23.12 121 =+==

Loxn

Also: V S = I SS RSS = 0.5V

Bias volta e at ates V =V +V =1.73V ,

This voltage creates the necessary 0.5mA currentin each of the transistors.

“Resistor current source” example –



differential gain design

Ω==

6322 1 Doxnm I

LC g μ

If R D= 3.16K Ω then differential voltage gain = g m R D = 5

“Resistor current source” example – with such



R D are transistors in Saturation?

out1= out2= DD - D D= . > in,CM – TH =1.73 – 0.6 = 1.13V by 290mV (the overdrive)





(c) If V in,CM increases by 50mV,what will happen to each output?


d




Large CM gain.

to the small

R

RV A Dout

CM V

2/, −=

Δ=

mV mV R

V V

g

DCM in X

SS mCM in

8.9694.1)50(2/

|| ,

,

=⋅=Δ=Δ⇒SS m

Common-Mode Response with



as mmetric assumin λ=0

ΔV X = −g m R D

in ,CM m SS

ΔV Y = − g m ( R D + Δ R D)in ,CM m SS

mY X g V V Δ−Δ

21,

D

SS mCM in R g V +Δ

RSS above represents the current source – need large RSS


ith t i R



with asymmetric R D

CM Response depends on

- t e output mpe ance o ta current source

- asymmetries in the circuit

Effects:

- Variation of output CM level

- convers ons o npu var a ons o

differential components at output


ith as mmetric R



with asymmetric R D

CM input noise corrupts the amplified

,


with finite tail capacitance



with finite tail capacitance

For high-frequency Common-Mode input need to take into

account parasitic capacitance effects, even if RSS is large. C1 is

1, 2 SS

“seen” by the CM signal.

Mismatches in W/L, V TH and other transistor

t ll t l t t i t h i



arameters all translate to mismatches in

P CM inm D V V g I −= )( ,11 Small-signal

P SS P CM inmmSS D D

P CM inm D

V RV V g g R I I V V g I

=−+=+⇒

−=

))(()()(

,2111

,22

ana ys s


t ll t l t t i t h i




SS CM inmm V RV V g g 21 ))(( =−+

CM inSS mm

P V R g g

V ,21 )( +=⇒

SS mm 21






D P CM inm X RV V g V ,1 )( −−= D P CM inmY RV V g V ,2 )( −−=

CM in D

SS mm

m V R R g g

g ,

21

1

1)( ++−−= CM in D

SS mm

m V R R g g

g ,

21

2

1)( ++−−=






D

SS mm

mm

CM in

Y X DM CM V R

R g g g g

V V V A

1)( 21

21

,

,++

−−=

−=−

Common-Mode Gains



•

of common-mode gain:• A : Sin le-ended

Y X CM V V V A , ==

,

output due to CM

signal.

CM inCM in ,,

• AV,CM-DM : Differential

output due to CM Y X V V −=

signal. CM inV ,

, −

Common-Mode Rejection Ratio (CMRR)

Definitions



Definitions

CM

DM

SE ACMRRCMRR==

DM

di

A

CMRRCMRR == DM CM −

In both cases we want CMRR to be as lar e as

possible, and it translates into small matchingerrors and RSS as large as possible



MOS Loads

MOS Loads



a Diode-connected load

(b) Current-Source load

MOS Loads: Analysis Method



y

• Differential Analysis: Use half-circuit method, with.

• Common-Mode Analysis: Again use half-circuitmethod, with appropriate accommodation for

para e trans stors, an or SS .

MOS Loads: Differential Gain Formulas



oP oN mP mN diff v r r g g A )||||( 1

, −= −

P p

N n

mP

mN

LW g

g

)/( μ

μ

−=−≈

, oP oN mN diff v −

Problems with Diode-connected MOS Loads



• Tradeoff among swing, gain and input CM range:

• In order to achieve high gain, (W/L)P must be sufficientlylow. Therefore PMOS overdrive voltage must besufficientl hi h. As a result CM si nal ran e is reduced.

Overcoming Diode-connected Load swing

problem for higher gains:



p g g

Use PMOS current sources which reduce g m of diode-connected MOS, instead of lowering (W/L)P of load. Gain

can e ncrease y ac or o .

Problems with Current-Source MOS Loads



’,

to obtain differential gains higher than 10-20.

Solution to low-gain problem: Cascoding



)](||)[( 7551331, oomoommdiff v r r g r r g g A ≈

Summary



• Need for Differential amplifiers

• -

• Analysis of Differential amplifiers

• Qualitative and Quantitative

• Common mode analysis

• Effects of transistor mismatch



.



References



1. Behzad Razavi, “ Design of Analog CMOS IntegratedCircuits”, Tata-McGraw Hill, 2002.

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