4장 Combinational Logic Circuitartoa.hanbat.ac.kr/lecture_data/digital_system/08.pdf ·...
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[email protected] 4장 Combinational Logic Circuit 4.1 개요 4.2 설계과정 4.3 가산기 4.4 감산기 4.5 코드변환 4.6 분석과정 4.7 다단 NAND회로 4.8 다단 NOR 회로 4.9 XOR 함수
Transcript of 4장 Combinational Logic Circuitartoa.hanbat.ac.kr/lecture_data/digital_system/08.pdf ·...
4장 Combinational Logic Circuit
4.1 개요
4.2 설계과정
4.3 가산기
4.4 감산기
4.5 코드변환
4.6 분석과정
4.7 다단 NAND회로
4.8 다단 NOR 회로
4.9 XOR 함수
Combinational Logic Circuit
q Digital Logic Circuit
u Combinational logic circuit)
l 출력 = f(현재입력)
l 현재의 입력에 의해서만 출력이 결정
n개의 입력이일정시간후 m개의 출력을생성
l No feedback
u Sequential logic circuitl 출력 = f(현재입력, 현재상태)
l 현재의 입력뿐만 아니라 현재의 상태도출력에 영향
l feedback
CombinationalLogic Circuit
CombinationalLogic Circuit
n inputvariables
m outputvariables
Design of Combinational Circuit
q Design Procedure(1) 문제기술
(2) Input, output variable의 갯수 결정
(3) Input, output variable의 이름 할당
(4) Truth table 작성 - 입력의 조합수를 파악하여무관조건항 설정
(5) Boolean function의 minimization
(6) Logic diagram 작성
(7) Design verification
q 설계시 제약조건
u 최소갯수의 논리게이트
u 게이트당 최소입력수
u 최소의 전달지연시간
u 최소의 연결선 수
u 각 논리게이트의 구동한계(fanout)
Half-Adder
x y S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
1
0 1
0
1
yx
C = xy
1
1
0 1
0
1
yx
S = xy’+x’y= x⊕ y
HAHAx
y
s
c
S
C
xy
Half-Adder의 구현
S = xy’+x’y
C = xy
xy’x’yxy
S
C
x’y’xy
S
C
S = (C+x’y’)’
C = xy
xy
x’y’
S
C
S = (x+y)(x’+y’)
C = (x’+y’)’
S = (x+y)(x’+y’)
C = xy
xyx’y’xy
S
C
Full-Adder
FAFAxy
S
Cz
x y z S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
x 00 01 11 10
0
1
yz
1
1
1
1
x 00 01 11 10
0
1
yz
1
1
1 1
S = xy’z’+x’y’z+x’yz’+xyz= x’(y’z+yz’)+x(yz+y’z’)= x’(y⊕z)+x(y⊕ z)’= x⊕y⊕z
C = xy+yz+xz
x 00 01 11 10
0
1
yz
1
1
1 1
C = xy+x’yz+xy’z= xy+z(x’y+xy’)= xy+z(x⊕y)
Full-Adder의 논리회로도
xy
yz
zx
C
xy’z’x’y’zx’yz’xyz
S
xy
z
S
C
S = xy’z’+x’y’z+x’yz’+xyz S = x⊕y⊕zC = xy+yz+xz C = xy+z(x⊕y)
Half-Subtractor
x y D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
HSHSx
y
D
B1
0 1
0
1
yx
B = x’y
1
1
0 1
0
1
yx
D = xy’+x’y= x⊕ y
xy D
B
Full-Subtracter
FSFSxy
D
Bz
x y z D B
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
x 00 01 11 10
0
1
yz
1 1
1
1
B = x’y+yz+x’z B = x’y+xyz+x’y’z= x’y+z(xy+x’y’)= x’y+z(x⊕y)’
00 01 11 10
0
1
yz
1 1
1
1
D = xy’z’+x’y’z+x’yz’+xyz= x’(y’z+yz’)+x(yz+y’z’)= x’(y⊕z)+x(y⊕ z)’= x⊕y⊕z
x 00 01 11 10
0
1
yz
1
1
1
1
BCD to Excess-3 Code Converter
A B C D w x y z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
w(A,B,C,D) = ∑(5,6,7,8,9)x(A,B,C,D) = ∑(1,2,3,4,9)y(A,B,C,D) = ∑(0,3,4,7,8,)z(A,B,C,D) = ∑(0,2,4,6,8)d(A,B,C,D) = ∑(10,11,12,13,14,15)
1
1 1 1
X X
1
X
X
X
X
ABCD
00
01
11
10
00 01 11 10
1
1
1
1
X
1
X X
X
X
X
ABCD
00
01
11
10
00 01 11 10
x = B’C+B’D+BC’D’
1 1 1
X
1
X
1
X
X
X
X
ABCD
00
01
11
10
00 01 11 10
w = A+BC+BD
1
1
1
1
X
1
X X
X
X
X
ABCD
00
01
11
10
00 01 11 10
y = CD+C’D’ z = D’
BCD to Excess-3 Code Converter의 논리회로도
q 출력함수의 변형
w = A+BC+BD
= A+B(C+D)
x = B’C+B’D+BC’D’
= B’(C+D)+BC’D’
= B’(C+D)+B(C+D)’
y = CD+C’D’
= CD+(C+D)’
z = D’
DC
B
A w
x
y
z
※ 식의 변형 전과 후의 게이트 수 비교전 : AND(7), OR(3)후 : AND(4), OR(4)
BCD to 7-Segment Display
W X Y Z a b c d e f g
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
0 0 1 1W X Y Z
a b c d e f g
BCD to 7-segmentdisplay
a b
c
d
e
f
g
Analysis of Combinational Circuit
F1
F2
T3F2’
T2
T1
ABC
AB
ABC
AC
BC
F2= AB+BC+CA
T1= A+B+C
T2= ABC
T3= F2’T1
F1= T2+T3
F1= T2+T3
= ABC+F2’T1
= ABC+( AB+BC+CA)’(A+B+C)= A’BC’+A’B’C+AB’C’+ABC
= A⊕B⊕C
(1)부울대수식유도
ㅇ 입력변수로 부터각 게이트의 출력에중간변수 할당
ㅇ 중간변수에 대한부울대수식 유도
ㅇ 회로의 출력에대한 부울대수식을 얻을때까지반복
ㅇ 중간변수를 대입하여최종출력을 입력변수에 대하여표현
Analysis of Combinational Circuit
A B C F2 F2’ T1 T2 T3 F1
0 0 0 0 1 0 0 0 0
0 0 1 0 1 1 0 1 0
0 1 0 0 1 1 0 1 0
0 1 1 1 0 1 0 0 1
1 0 0 0 1 1 0 1 0
1 0 1 1 0 1 0 0 1
1 1 0 1 0 1 0 0 1
1 1 1 1 0 1 1 0 1
(2) 진리표작성후 map을 이용
F1
F2
T3F2’
T2
T1
ABC
AB
ABC
AC
BC
A 00 01 11 10
0
1
BC
1
1
1
1
A 00 01 11 10
0
1
BC
1
1
1 1
F2= AB+BC+CAF1= A⊕B⊕C
Multi-Level NAND Circuit
A A’
AB AB
(AB)’
A
B(A’B’)’=A+B
A’
B’
≡ABC
(ABC)’ABC
A’+B’+C’ = (ABC)’
NOT
AND
OR
Multi-Level NAND Circuit의 구현
AB’CD’BE’
F
A’BC’DBE’
F
A’BC’DBE’
F
CDEAB’
F
CDE’AB’
F
CDE’AB’
F
Analysis of Multi-Level NAND Circuit
CD
B’
A
BC’
F
T1
T3
T4
T2
T1= (CD)’ = C’+D’
T2= (BC’)’ = B’+C
T3= (T1B’)’ = [ (C’+D’)B’ ]’ = (B’C’+B’D’)’
= (B+C)(B+D) = B+CD
T4= (AT3)’ = [ (A(B+CD) ]’
F= (T2 T4 )’ = (BC’)[ A(B+CD) ]’
= BC’+A(B+CD)
(1) 부울대수식유도
Analysis of Multi-Level NAND Circuit
CD
B’
A
BC’
F
T1
T3
T4
T2
A B C D T1 T2 T3 T4 F
0 0 0 0 1 1 0 0 0
0 0 0 1 1 1 0 0 0
0 0 1 0 1 1 0 0 0
0 0 1 1 0 1 1 1 0
0 1 0 0 1 0 1 1 1
0 1 0 1 1 0 1 1 1
0 1 1 0 1 1 1 1 0
0 1 1 1 0 1 1 1 0
1 0 0 0 1 1 0 0 0
1 0 0 1 1 1 0 0 0
1 0 1 0 1 1 0 0 0
1 0 1 1 0 1 1 1 1
1 1 0 0 1 0 1 1 1
1 1 0 1 1 0 1 1 1
1 1 1 0 1 1 1 1 1
1 1 1 1 0 1 1 1 1
1 1
1 1 1
1
1
ABCD
00
01
11
10
00 01 11 10
F = AB+BC’+ACD= A(B+CD)+BC’
(2) Truth table작성후 map을 이용
Analysis of Multi-Level NAND Circuit
(3) AND-OR 회로도로 변환
CD
B’
A
BC’
F
CD
B’
ABC’
F
CD
B
ABC’
F
F = A(B+CD)+BC’
Multi-Level NOR Circuit
A A’
≡ABC
(A+B+C)’
NOT
AND
OR
ABC
A’B’C’ = (A+B+C)’
AB A+B
(A+B)’
A
B(A’+B’)’=AB
A’
B’
Multi-Level NOR Circuit의 구현
AB
E
CD
F
A’B’
E
CD
F
A’B’
E
CD
F
Multi-Level NOR Circuit의 해석
CD
B
ABC’
F
CD
B
ABC’
F
CD
B’
ABC’
F
XOR function
x⊕y = x’y+xy’
x⊕0 = x
x⊕1 = x’
x⊕x = 0
x⊕x’ = 1
x⊕y’ = (x⊕y)’ = x⊙y
x’⊕y = (x⊕y)’ = x⊙yx⊙y’ = (x⊙y)’ = x⊕y x’⊙y = (x⊙y)’ = x⊕y
x
x⊕y
y
x⊕y
x
y
Odd function
A 00 01 11 10
0
1
BC
1
1
1
1 F= A⊕B⊕C
= A⊙(B⊕C)’
= A⊙B⊙C
“1”의갯수가 홀수일때 “1”출력
Even function
“1”의갯수가짝수일때 “1”출력
A 00 01 11 10
0
1
BC
1
1
1
1
F= (A⊕B⊕C)’
= A⊕(B⊕C)’ = A⊕(B⊙C)
= (A⊕B)’⊕C = (A⊙B)⊕C
ABC
FABC
F
ABC
F
ABC
F
ABC
F
Parity Generator
x y z Podd Peven
0 0 0 1 0
0 0 1 0 1
0 0 0 0 1
0 1 1 1 0
1 1 0 0 1
1 0 1 1 0
1 0 0 1 0
1 1 1 0 1
A 00 01 11 10
0
1
BC
1
1
1
1
Podd = (x⊕y⊕z)’
= x⊕(y⊙z)
= (x⊙y)⊕z
xy
z
Peven
Odd parity
A 00 01 11 10
0
1
BC
1
1
1
1
Peven = x⊕y⊕z
= [x⊕y⊕z]’’
= [x⊕(y⊙z)]’= x⊙y⊙z
Even parity
xy
z
Podd
(cf) (x⊕)y⊙z = x⊕(y⊙z)
Parity Checker
x y z P Codd Ceven
0 0 0 0 1 0
0 0 0 1 0 1
0 0 1 0 0 1
0 0 1 1 1 0
0 1 0 0 0 1
0 1 0 1 1 0
0 1 1 0 1 0
0 1 1 1 0 1
1 0 0 0 0 1
1 0 0 1 1 0
1 0 1 0 1 0
1 0 1 1 0 1
1 1 0 0 1 0
1 1 0 1 0 1
1 1 1 0 0 1
1 1 1 1 1 0
1
1
1
1
1
1
1
1
xyzP
00
01
11
10
00 01 11 10
1
1
1
1
1
1
1
1
xyzP
00
01
11
10
00 01 11 10
Odd parity Even parity
Ceven = x⊕y⊕z⊕PCodd = (x⊕y⊕z⊕P)’
= x⊙(y⊕z⊕P)
= x⊙y⊙(z⊕P)’
= x⊙y⊙z⊙P
