3A6 Computing Systems Laboratory Michaelmas …dwm/Courses/3CSlab_2001/...0 3A6 Computing Systems...

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3A6 Computing Systems Laboratory

Michaelmas Term 2001

3A6 Laboratory Sessions 1,2,3Michaelmas 2001 Prof DWMurray/Dr PJ Smith

Overview

The three sessions in this laboratory are designed to reinforce issues discussed in the 3A3 course onComputer Architecture.

They touch on

• Design and Implementation using a PLA;

• Data transfer on a bus; and

• Macro and microprogramming.

With sensible preparation, which means reading the sheet beforehand and completing some “compre-hension” exercises, and focussedwork during the practical, you should be able to complete each exercisewell within the 2 hours allotted, and you are urged most strongly to get your work signed off on theday. If you can’t you must have it signed off at your next session.

Recording results. The lab sheets contain space for results.

Working as a trio. During these sessions you will work in groups of three. Please make sure each ofyou gets a turn at driving, and that each contributes intellectually to solving the problems.

Computer Systems Laboratory 2001 1

3A6 Computing Systems Laboratory 2001

Cover Sheet

Name ................................................................................................................................

College ................................................................................................................................

ExperimentsNo Experiment Attendance Report Accepted

Title Date Initials Date Initials

CS1 PLA Design using CAD orDiscrete component CPU

CS2 Bus communications

CS3 Macro and micro programming

Lab Session 1

CS1: PLA Design using CAD

Important Notes

1. Before entering the lab, you MUST complete the initial design of the circuit. You will not beallowed to start until you have done this.

2. There is no formal report for this practical work. To complete the exercise, you must convince thedemonstrator (a) that you have produced adequate documentation to describe your design (logicdiagrams, listings of PAL definition files) (b) that your logic design functions correctly.

3. Undergraduate files are wiped from the PC’s each morning. If for some reason you need to retainyour work you must arrange for a demonstrator to save it onto a floppy disc for you.

1.1 Aims

The main aims of this practical are to give you some experience in using CAD tools in the design andspecification of logic circuits, and to examine methods of implementation based on the use of Pro-grammable Logic Devices. You use a commercial CAD package to complete the design of a logic circuit.The circuit you are going to implement is shown part completed below. You must finish the design (Ex-ercises 1A and 1B) and then use special packages to convert the logic components into a form suitablefor downloading in a programmable gate array. The final part of the experiment downloads the codeyou have created into the LCA chip on the circuit board and tests the implementation.

1.2 Circuit Design

The input to the circuit below (at the bottom left) is a regular clock signal from an external generatorbox. The output is a 7-segment display that counts in repeated cycles from 0 to F in hex.

At the top left is a 4-bit counter C16BCRD which counts binary 4-bit numbers on the outputs Q0 to Q3as it is clocked (output Q3 is the MSB). The key element is a PAL or PLA (programmable array logic)chip. Four inputs to the PAL are taken from the outputs of the binary counter. Seven outputs from thePAL drive the segments of the 7-segment LCD.

The internal logic of the PAL is to be set up to display on the LCD the (hex) number (0-9,A,b,C,d,E,F)selected by the binary input lines — eg, 1010 → A on the display. The circuit diagram shows howthe LCD segments are labelled by letters, and the following “PAL Definition File” shows that SegmentA of the display is driven by pin 19. The Definition File also shows that, for example, Segment A isilluminated for the hex numbers 0,2,3,5,6,7,8,9,A,C,E,F.

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Note that the outputs from the PAL should be connected to segments A to F of the display through thepins 1 of XOR gates. These are considered later, along with the other binary counter at the bottom left.

CE

C

Q0Q1Q2Q3TC

RDI

+5

GND

CE

C

Q0Q1Q2Q3TC

RDI

+5

GND

(A)

(B)

(C)

(D)

(E)

(F)

(G)

P65

IPAD

II

IBUFO

GCLK

I O

C16BCRD

C16BCRD

PAL

FILE=

1234567891011

12

13

14

15

16

17

18

19

OBUFO

OPAD

2XOR

OOBUF

OOPAD1

2XOR

OOBUF

OOPAD1

2XOR

OOBUF

OOPAD1

2XOR

OOBUF

OOPAD1

2XOR

OOBUF

OOPAD1

2XOR

OOBUF

OOPAD1

2XOR

OOBUF

OOPAD

P561

P57

P58

P59

P60

P61

P62

P63

(A)

LCD segments

(B)

(C)

(D)

(E)

(F)

(G)

I

I

I

I

I

I

I

I

The PAL definition file

(1) The first section declares various background information and defines the type of PAL to be used.

(2) The second section gives the names of the logic signals to be associated with the input and outputpins. These names are used internally in the PAL definition file to set up the appropriate logic; it is upto you to connect up the circuit later so they are the correct signals. “NC” indicates that the pin is NotConnected.

(3) Then intermediate signal names are set up to simplify the entry of the Boolean equations. The key-word STRING is used to equate a name to the text declared between single quotation marks. For exam-ple, S0 is when all the input digits are zero: ie not.D0 and not.D1 and not.D2 and not.D3 (/D0 * /D1 */D2 * /D3 in the definition file language). Signal names S1 to S15 should be set up similarly. Here, “ * ”denotes Boolean AND, and “ / ” denotes logical inversion.

(4) Finally the relationship between the input and output pins are defined. The keyword EQUATIONS

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is followed by the Boolean equations that define the output signal names in terms of the intermediatesignal names (the intermediate names could be omitted in favour of the input names, but this way ismuchmore readable). Here “+ ” denotes BooleanOR, “:+:” denotes Boolean EOR, and “=” is an operatorindicating a combinatorial output equation.

TITLE MYPAL.PDSAUTHORCOMPANYDATE OCTOBER 2001CHIP 7SEGS PAL16LD;input pins 1 2 3 4 5 6 7 8 9 10

D0 D1 D2 D3 NC NC NC NC NC NC;output pins 11 12 13 14 15 16 17 18 19 20

B A NC <-- FIXME;input combinationsSTRING S0 ’/D3 * /D2 * /D1 * /D0’STRING S1 ’/D3 * /D2 * /D1 * D0’STRING S2 ’/D3 * /D2 * D1 * /D0’STRING S3 <-- FIXMESTRING S4STRING S5STRING S6STRING S7STRING S8STRING S9STRING S10STRING S11STRING S12STRING S13STRING S14STRING S15 <-- FIXME

EQUATIONSA = S0 + S1 + S3 + S5 + S6 + S7 + S8 + S9 + S10 + S12 + S14 + S15B = <-- FIXMEC = <-- FIXMED = <-- FIXMEE = <-- FIXMEF = <-- FIXMEG = <-- FIXME


EXERCISE 1A: Complete the PAL Definition File above.

1.2.1 Completing the timing and interface circuitry

The PAL outputs are gated through XOR gates to the LCD display. Use Q0 of the lower 16 bit counterto provide the gating input to each XOR gate.

The upper counter must be clocked more slowly to ensure that the LCD display is always valid. Choosean about from the lower counter so that the upper counter is clocked at 1/8 the rate of the Q0 output ofthe lower counter.

The external connections to the LCD are from the output pads (OPADs). Each segment of the LCDhas two contacts, one from the output pad connected to the XOR gates (OPADs P56-62) and the otherconnected in common to OPAD P63. For example, the p.d. across segment A is that between P63 andP56. Notes. (1) Connect Q0 from the lower counter to the buffer of OPAD P63.(2) The buffers are “straight through” not inverting.

EXERCISE 1B: Complete the circuit diagram.

EXERCISE 1C: Make a sketch of the p.d. across a segment when it is on and when it is off. Why issuch a p.d. used?

Hints:(1) Consider the pd when pin 19 is high then low. Remember Q0 is clocking faster. (2) Also think aboutLCDs, polarization and capacitors.

OBUFO

OPAD

P63I

Q0

2XOR

OOBUF

OOPAD

P561

(A)I

19

pd

Pin 19

Q0

XOR

PD

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1.3 Computer Aided Generation of the Logic Circuit

In this section you complete the logic drawing.

A commercial program (called Futurenet DASH4) will be used to generate the schematic diagrams on apersonal computer. The software is menu- driven and makes use of a three button “mouse”. Diagramsare drawn on the screen by interconnecting logic symbols that you will load from a software library. Thevisual description of the logic circuit is converted into digital form automatically and can be stored in adata file on the disk of the computer. The data file will then be used to specify the digital logic circuitsthat are needed to implement your design.

EXERCISE 2

1. Make sure the PC is displaying the prompt C:\UGRAD> If it isn’t, consult a demonstrator. Geta directory listing by typing “DIR ” (and check that you have files there called CIRC.DWG andPALDEF.PDS. Note the size of CIRC.DWG.

2. Run the schematic entry program by entering

FN 2

The program is described in detail in the Appendix, but the easiest way to get a feel is to draw afew lines with the mouse, and load a few circuit symbols. Notice that it is the right hand mousebutton that cuts a wire after drawing. HELP information is available by selecting? HELP ”.

3. Use the file load option to read in the partially completed drawing of the counter and encodinglogic. The part finished drawing is “CIRC.DWG”, but you don’t need to give the .DWG extension.

4. Enter the rest of the logic diagram including your design in the proforma using the commandsdescribed in the simple guide given below. NOTE: After entering the program, you should pressthe right-hand button of the mouse to switch the display to the command menu.

5. Provide a file name for the PAL definition file on the PAL symbol. Point the mouse at the start ofFILE= text. The text should light up. Press ESC. Then give the PAL a name by typing FILE=MYPALor whatever. The name can be anything apart from PALDEF, but for the rest of this document we willassume that you called it MYPAL.

6. Fill in the name and date details on the bottom right.

• To edit date, position cursor over the writing, press ESC and edit.

• To enter name, etc, position cursor in box, enter ’A 0<return> to switch to comment mode,press ESC, enter your text, and finally press ESC to finish.

7. Ask a demonstrator to check that all details of your drawing are correct.

8. Save your drawing. The Save selection will write into CIRC.DWG. Use the DOS DIR selection tolook at the directory. You should find that CIRC.DWG is now larger. If not, try saving again!

9. Exit the schematic program by issuing the QUIT command.


1.4 Specifying The Programmable Logic Array

In this part of the experiment you enter the design you completed for the PAL. The logic that is to beimplemented by the PAL is part defined in the file PALDEF.PDS that you completed in the proforma,and you first have to edit this file using the editor NE.

EXERCISE 3

1. Enter

NE PALDEF.PDS

to examine and complete the PAL definition file.

2. Ask a demonstrator to check the file.

3. When finished, press the F3 function key followed by the E key to exit the editor and save themodified PAL definition file on disk. It will be saved as PALDEF.PDS. (You could save it underanother .PDS name, but below we will assume it is PALDEF.PDS

1.5 Implementing The Design Using A Logic Cell Array

So far part of your logic design has assumed the use of off- the-shelf logic devices (gates, counters etc.)and part has used a PAL. To allow you to check that your design operates correctly, all of the logicwill be implemented in a single integrated circuit, called a Logic Cell Array (LCA). This device (partnumber 2018PC84-33) consists of a 10 by 10 array of software configurable logic blocks, each having4 inputs, 2 outputs and a single bit memory element. External signals are connected to the array viathe 84 pins of the chip through 84 configurable input/output logic blocks. The configuration and theinterconnection of the blocks is controlled by a configuration program which is stored in an on-chipmemory. The configuration program is defined in a.BIT ” file which is generated by special-purposeCAD software (the XILINX LCA development system) and downloaded into the device from the PC.

In the circuit diagram, the input to the LCA is pad P65. This will be connected to an external clock (apulse generator). Outputs pads P56 to P63 go to the LCD display.

EXERCISE 4

Follow the procedure given below to implement the logic in the LCA connected to your LCD display.ASK THEDEMONSTRATORTO EXPLAINANYWARNINGSOR ERRORMESSAGES THATYOUDONOT UNDERSTAND.

1. First, convert your PAL definition file to the XILINX standard format file PALDEF.XNF by enter-ing

PDS2XNF -N PALDEF.PDS

NOTE: The -N directive ensures that the pin connections specified in your schematic are used inthe final design.

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Configurable logic block Interconnect

Configurable IO block

Figure 1.1: Block diagram of the Logic Cell Array

2. Optimize the PAL design for LCA implementation.

When writing the PAL design file, you took no account of the redundancy theorem. The programXNFOPT does that for you. It produces two optimizations, one which reduces the amount oflogic by using feedback and the other which gives the minimum number of logic levels throughavoiding feedback. The two minimizations are on the left and right of the screen. Enter

XNFOPT PALDEF

The XNFOPT program iterates in an endless loop. Press the “CNTRL BREAK” keys to terminate executionas soon as you think that it has found an acceptable implementation of the logic. About 10 iterations shoulddo. If INPUTS=28, your design is likely to be correct!

The two optimizations are written to two different files. You are going to avoid feedback using theoptimization in BESTCLB.XNF. It is this file which must match the name given to the PAL in yourdrawing. So enter

RENAME BESTCLB.XNF MYPAL.XNF

You now have the Xilinx Netlist Format file for the PAL in you drawing, but you need to producethe same sort of file for the rest of the drawing.

3. So now convert the drawing file generated by the schematic entry program to XILINX standardformat. Enter

DWG2XNF CIRC

This will produce CIRC.XNF. This has a hook ready for the PAL’s XNF file.

4. Pull the two XNF files together into one, called CIRCM.XNF by entering

XNFMERGE CIRC CIRCM

If you get errors here, it probably means there is an error in the drawing file.

5. Now convert the merged file into an LCA file suitable for processing for the LCA array:

XNF2LCA -P 2018PC84-33 CIRCM


6. Auto-place and route the LCA design by typing

APR CIRCM CIRCMAR

This will produce file CIRCMAR.LCA.

Execution of this program takes around 10 minutes, so read on ...

You will see that the placement starts off with a score (probably around 9000) and temperature,and that as time progresses the temperature falls and the score gets lower.

The program is using technique called simulated annealing to do the placement. To start withplacements in the LCA are chosen randomly and a ’badness’ score S computed depending onhow much logic is used and how messy the interconnect is. A high score indicates a bad design.The program then postulates a change in the design. If the change in score, ∆S, is negative, thedesign is getting better and the change is accepted. If the change in score is positive, the design isgetting worse but the change is still accepted with a probability exp(−∆S/T ). T is the temperatureparameterwhich is initially high to allow large changes for theworse butwhich is lowered steadilyas the optimization progresses, so that changes become more and more unlikely.

Why allow changes for the worse? Simply because the badness score is not a convex function andif only changes for the better are allowed there is a danger of getting trapped in a sub-optimalplacement (a local minimum). The exponential probability function is like a Boltzmann function,where s is an energy change and T a temperature. (Strictly then we would need kT where k isthe Boltzmann constant.) The whole process is thus like cooling a melt slowly to obtain a perfectcrystal structure— hence the name. Note that cooling too quickly— ie quenching—would freezein defects in the crystal/circuit placement.

By the time you have read this, most of the annealing has been done. To ensure convergence insimulated annealing you should use a logarithmic cooling schedule, which takes an infinite time.But we are reasonable people ...

Wait until your score is around 5000, then press Cntrl and Break together. This will start a linearcooling schedule — quenching. Wait until one more results comes out and then press Cntrl andBreak again. This will stop the process and start writing out the autorouted design.

1.6 Downloading the design into the LCA

EXERCISE 5

1. Your file CIRCAR.LCA contains the autorouted design. You now need to create a “.BIT” file thatwill configure the LCA on the test board. Follow this procedure using the mouse to select items:

(a) Enter XACT.

(b) Select the Designs command on the main menu followed by the Design command on thepull-down menu. You should of course choose your auto-routed CIRCMAR.LCA file.

(c) Select the Programs command on the main menu followed by the MakeBits command on thepull-down menu.

(d) Select the Misc command followed by the PORT command and choose LPT2.

(e) Select the Config command followed by the MakeBits command, choose the Tie option andselect Done to generate a file CIRCMAR.BIT file from the CIRCMAR.LCA file.

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(f) Select the DOWNLOAD command.

(g) Reset the LCA on the test board.

(h) Press the ENTER key and wait for the message indicating successful completion of the down-load.

You should now see a digit (usually 0) displayed on the LCD. Sometimes the final downloadfails with an error message that the download signal has not gone high, or has gone hightoo early. The problem usually goes away if you repeat from item (6) above — ie from thedownload command.

2. Set the circuit counting by switching on the signal generator (input to the LCA, pin 65) and visuallycheck the operation of your logic on the LCD display.

3. Ask a demonstrator to verify that your design functions correctly.

The LCA is running independently of the PC, so you can quit the XACT program.

1. Select the “Misc” command followed by the “EXIT” command.

2. Select the “Programs” command followed by the “QUIT” command.


APPENDIX: A Brief Guide to Futurenet DASH4

Execution.

To run the Futurenet DASH4 program with the correct library of logic symbols enter

FN 2

Mouse Functions.

BUTTON SCREEN FUNCTIONLEFT MENU Executes the selected command immediately

DRAWING: Draws line segmentsMIDDLE MENU: Enters the selected command into the command line

DRAWING: Executes the command in the command lineRIGHT MENU: Toggles between to drawing

DRAWING: Toggles to menu

Controlling which part of the drawing is to be displayed on the screen

• Move the mouse in the direction of the part of the drawing to be displayed

• Press the PgUp key to display the entire drawing

• Press the PgDn key to zoom in on the part of the drawing within the dotted lines

Saving or loading your logic diagram

• Select SAVE and enter a file name to store your schematic on the disk ( filename.DWG )

• Select LOAD and enter the filename to load an existing schematic from the disk

Drawing logic symbols

• Select .DIR to list the names of all of the logic symbols held in the library

• Select * and enter the symbol name to load and move a symbol

• Select ” .M ” to move a symbol that has already been drawn

• Select ” .C ” to copy a symbol that has already been drawn

• Select ” .E ” to erase a symbol that has already been drawn

NOTE: The cursor must be positioned on the symbol before the command is executed.

The names of the logic symbols used in the example logic diagram are :

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TBLOCK generates the title block for the drawingC16BCRD 4 bit binary counter with clock enable

and direct resetXOR2 2 input exclusive OR gatePAL10H8 Programmable AND/OR array with

10 inputs and 8 active high outputsGCLK clock bufferIBUF input bufferIPAD input pad connected to an external

logic signalOBUF output bufferOPAD output pad connected to an external

logic signalVCC connection to +5 voltsGND connection to 0 volts

Drawing interconnecting signal lines

• Press LEFT and release: superimposes cross-wires

• Move cursor: draws a two segment ’ghost’ line

• Press LEFT and release: draws first of the two segments

• Move cursor: continues as described above

• Press LEFT and release: draws second of the two segments

• Press RIGHT and release: terminates line

NOTE: The line will be locked on to the pin of a logic symbol if the cursor is positioned near to the pin.

Erasing a segment of an interconnecting signal line

• Select /ES with cursor on the line segment to be erased

Joining signal lines

• Select /D with the cursor on the interconnection point: adds an interconnection dot, or erases an existinginterconnecting dot

NOTE: Interconnection is implicit when two signal lines meet at a T-junction whereas you need a dot for acrossover join.

Moving, copying or erasing entire sections of the logic diagram

• Select [D to define the area to be moved, copied or erased

• Select [M to move the defined area

• Select [C to copy the defined area

• Select [ERASE to erase the defined area

• Select [K to cancel the definition of the area


Entering alphanumeric text

• Place the cursor at the point where text is to be entered

• Press the ” ESC ” key to enter text entry mode

• Enter the text on the keyboard

• Press the ” ESC ” key to return to drawing mode

NOTE: Text has to be given an attribute which indicates whether it is a signal name, comment, title and so on.This is done using the ’A selection. See for example Signal Names below.

NOTE: The cursor will lock on to an existing text field when placed close to that field. The cursor keys can beused to move the cursor in text entry mode.

Assigning signal names

• Select ’A 5 to set the correct attribute for the text

• Enter the name of the signal as alphanumeric text

• Select ’P to position the ’POINT OF EFFECT’ of the name (indicated by a green square) on the signal line

NOTE: ’D displays the attribute numbers of all alphanumeric text.

Specifying a pin number

• Place cursor on the ” Pxx ” field of the input or output pad.

• Press the ” ESC ” key and enter the number on top of the ”xx”.

• Press the ” ESC ” key to return to drawing mode.

Leaving the schematic entry program

• SAVE your work first

• Select ” QUIT ” to leave the program and return to the operating system

Revised 14/10/2001 14:28˜ dwm/Teaching/Labs/CO3-00/prac1.tex

Lab Session 2

CS2: Bus Communications

Important Notes

1. Some preparatory work should be completed before attempting this practical exercise.

2. The report for this exercise consists only of completing the proforma at the end of the instructionsheets. You are required to read the instructions and complete those parts of the proforma that aremarked with an asterisk BEFORE you attempt the experimental work.

3. The main aims of the experiment are to investigate the different ways in which data is transferredwithin a computer system and to give you some experience in using special-purpose test equip-ment, a logic analyser and a network monitor. Each group will work with two microcomputers,each consisting of a number of printed circuit boards plugged into an interconnecting backplanebus. Data is transferred in parallel over the backplane bus. In addition, a single computer net-work interconnects all four of microcomputers of the both groups working on this exercise. Datais transferred serially over the network. The experiment, of two hours duration, is concerned withdata communication within one microcomputer over the backplane bus.

2.1 Introduction

Each microcomputer consists of several printed-circuit boards plugged into an interconnecting back-plane, as shown below. The backplane used by these microcomputers is based on the 16 bit VME busstandard. The VME bus has the following lines:

• a 16 bit parallel data bus (D00 to D15)

• a separate 29 bit address bus (A01 to A23 and some address modifier bits that are not used in thissystem)

• 6 data transfer control lines (AS*, WRITE*, DS0*, DS1*, DTACK*, BERR*)

• 10 interrupt control lines (IRQ1* to IRQ7*, IACK*, IACKIN*, IACKOUT*)

• 14 bus allocation control lines (that are not used in these single master microcomputer systems)

• 6 utility control lines (SYSRESET*, SYSFAIL* etc.).

A subset of these signals have been brought out to the sockets on the front-panel of the microcomputer.

Figure 1 shows the hardware configuration for this experiment. Connected through the VME bus arethe following printed circuit boards (PCBs):

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Hello Sailor

AS*DS0*DS1*WRITE*IACK*

DTACK*

Microprocessor

DataMemory

I/OCounter/

Timer

D0-15A0-23

Terminal

IO hardware

LogicAnalyser

PC

Figure 2.1: The hardware configuration

• a microprocessor with on-board memory, connected to a terminal and keyboard

• a data memory board

• an input/output board containing parallel and serial interfaces and a counter/timer

In the experiment you will observe the signals passing along the bus when data transfers take placebetween these PCBs.

2.1.1 Introduction to PC-based Logic Analyser

Logic analysers are used to observe digital signals and, in particular, the timing relationships betweenthese signals.This cannot be done on a conventional oscilloscope because of the difficulty of displayingnon-periodic signals, and because normally we want to look at a large number of signals at once. Mod-ern logic analysers have a large number of extra facilites for setting up a variety of operating modes andfor producing hard copy.

The analyser used in this experiment consists of a printed circuit board inserted into the PC togetherwith a controlling program.

The logic analyser has three pods labelled A, B and C. Each pod has 9 probes for connection to up to 8logic signals ( labelled 0 to 7) and a ground connection (labelled GND). There are four basic menus, onefor each of the analyser’s four basic modes of operation :

1. FORMAT mode in which the user can set-up the analyser.

2. TIMINGmode in which the logic signals can be displayed on a timing diagram.

3. LIST mode in which the digital information can be listed in tabular form.

4. DOS mode in which data and set-up files can be saved to or loaded from disk.

16

Connecting up the pods Each probe can be connected to any logic signal. However it is convenientfor the experiment to connect them up as follows: Pod A to A1 to A8, Pod B to D0 to D7 and Pod C tothe 8 control signals on port C. This connection means that you can see at least some of the address anddata lines during each data transfer.

Entering the logic analyser program Enter ALA to execute the program that operates the Axelen LogicAnalyser.

NOTE: The program will default to FORMAT mode when initially executed. You can usually abort acommand by pressing the ESC key, if you make a mistake during keyboard entry.

EXERCISE 1

1. Familiarise yourselve with the operation of the logic analyser by trying out the commands de-scribed in Appendix A.

HELP information: Press the F1 function key to display the help information

2.2 The Data Transfer Protocol

Address and data transfers are both made under fully interlocked handshake control as shown in thetiming diagram (Figure 2). Explain the function of each of the bus control signals and the operation ofthe data transfer protocol

The microcomputer has been programmed to do the following operations in a continuous loop:

• Operation 1: read a particular location in the VME memory board

• Operation 2: write the code for a single ASCII character into a different location in the memorywhenever a key is pressed on the keyboard

• Operation 3: service interrupts from a counter/timer chip on a VME parallel I/O board

EXERCISE 2

1. Connect the probes of the logic analyser to the data bus, the address bus and the data transfercontrol signals on the front-panel.

2. Trigger the logic analyser on an appropriate combination of signals so as to obtain a timing dia-gram of a read cycle between the microprocessor and the data memory (Operation 1 above). Tochoose the triggering combination, examine again the timing diagram Figure 2. Which controllines are asserted when a valid read operation is occurring? Adjust the time scales to obtain asuitable sized display.

3. Print-out the timing diagram and check that it conforms to your description of the VMEbus datatransfer protocol.


��

��

��

��

��

��

��

��

��

��

��

��

Data

DTACK*

DS1*

DSO*

WRITE*

IACK*

AS*

Address

Figure 2.2: Timing diagram showing the transitions of the bus control signals during the transfer of onebyte of data from the memory to the microprocessor (THE READMEMORY CYCLE)

4. Now repeat the exercise to examine the write cycle described above (operation 2). There are in facttwo write cycles (one associated with the interrupt) and you must make sure you get the correctone. The correct one operates as follows: when a key is pressed on the keyboard the appropriateASCII code is read from the serial line and then sent out to the data memory. You are to observethe character being sent out to the data memory. Decide which key you are going to press and usethe ASCII code table provided in the lab to determine which triggering combination to observe.When you have produced a timing diagram, take a hard copy.

2.3 The Vectored Interrupt Control Protocol

Slave devices (e.g. the counter/timer or the network interface) may interrupt the operation of the mas-ter (the microprocessor) and request attention on any of seven priority levels (IRQ1* to IRQ7*). Sincemore than one slave may generate requests at the same level of priority, the master uses an interruptacknowledge cycle to determine which of its slaves is demanding attention.

The control cycle is as follows. The master (the CPU in this application) sends a signal IACK* on re-ceiving an interrupt request on any of the lines IRQ0* to IRQ7*. At the same time it places the interruptnumber (0 to 7) on the address lines. The IACK* is sent to slot 1 on the VME backplane as the signalIACKIN*. If the device in slot 1 is not the one interrupting at this level it simply passes on the signal asIACKOUT* to the next device on the VME bus. Thus each device examines the acknowledge signal inturn. The device which generated the interrupt does not pass on the IACK*, thus ensuring that only onedevice will be serviced at a time.

When a device acknowledges the interrupt, it puts the address of its interrupt vector on data lines D0 to

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D7. This address is used by the processor to transfer control to the interrupt service routine.

AS*DS0*

D0-15A0-23

DTACK*

IRQ2*IRQ4*

SlaveLevel2

SlaveLevel2

SlaveLevel4

IACK* IACK*IACK*

Figure 2.3: Interrupt connections. The IACK* bus has breaks in it at each board slot. If the slot is empty,a jumper is installed. If the slot is filled, the board takes in the IACK* but passes it along if the board hasnot requested an interrupt at the appropriate level.

EXERCISE 3

1. Connect and trigger the logic analyser so as to display an interrupt acknowledge cycle for thecounter/timer. You will need to find on which interrupt line IRQ it is interrupting. The easiestway to do this is to look for any interrupt by choosing appropriate trigger signals; by examiningthe trace you should then be able to determine on which IRQ line the interrupt is coming through.Alternatively you can try to trigger off each IRQ line in turn.

You will need to alter your time scales to observe the full interrupt cycle.

2. Print-out the observed timing diagram and label its important features


Appendix A: Operation Of The Logic Analyser Program

Changing the mode of operation

Enter

• F to change to FORMAT mode

• T to change to TIMIMGmode

• L to change to LIST mode

• D to change to DOS mode

or, alternatively,

• Press the F10 or F9 function key

• Select the MODE command on the main menu bar at the top of the screen

• Select the appropriate mode command from the pull-down menu

NOTE: The first method will not work from certain menus.

Setting-up the analyser

• Enter FORMAT mode

• Set up the parameters by using the cursor keys to move to the appropriate point on the screen andthe function keys F5 or F6 to cycle backwards or forwards through the possible values.

NOTES:

• The internal clock should be used throughout the experiment.

• All of the signals that you will examine conform to TTL logic levels.

• The time interval over which data will be stored and displayed depends on the sample rate andon the number of channels that are to be monitored.

• The ” Trigger word ” defines the condition of the logic signals ( 0, 1, or x = don’t care ) that willcause the analyser to start sampling and storing the data.

• The ” Trigger displacement ” determines the position of the trigger point on the display ( e.g. ifthe trigger displacement has a value of 128, the trigger point will be in the centre of the screen).

• When placed in the fields associatedwith the ” Trigger condition ”, entries to the right of the cursorare erased by pressing the space bar.

20

Annotating the timing diagrams

NOTE: The following instructions assume that the analyser is in its ” TIMING ” mode

1. Changing the number of signals to be displayed:

• Press the F10 function key

• Select the DISPLAY command from the main menu bar at the top of the screen

• Select the required number of channels to be displayed from the pull-down menu

2. Changing the order of display:


• Select the SEQUENCE command from the main menu bar at the top of the screen

• Enter the channel names in the required positions in the pull-down dialogue box

• Press the TAB key

• Select the OK command

3. Labelling signals :


• Select the LABEL command from the main menu bar at the top of the screen

• Enter the names of the signals into the pull-down dialogue box

• Press the TAB key

• Select the OK command

Collecting data


• Select the MODE command from the main menu bar at the top of the screen

• Select the TRACE command from the pull-down menu

NOTE: The analyser will display the data as a timing diagram after it has been collected

Defining which part of the data is to be displayed on the screen

NOTE: The following instructions assume that the analyser is in its TIMINGmode.

• The analyser can display a maximum of 512 samples of each channel at any one time.

• Display indicates the sample numbers of the start and end of the data currently displayed.

• Press the F6 or F5 function keys to increase or decrease the Magnification .


Measuring time intervals on a timing diagram

NOTE: The following instructions assume that the analyser is in its TIMINGmode

• Use the left right cursor keys to move the display cursor (the red line) to the point of interest


• Select the POSITION command from the main menu bar at the top of the screen

• Select the reset Reference pointer command to move the reference pointer ( ) from the triggerpointer ( Y ) to the position of the display cursor ( C )

NOTE: The duration is the time interval between the reference pointer and the display cursor

Printing the timing diagram

NOTE: The following instructions assume that the analyser is in its TIMINGmode

• Press the F10 function key.

• Select the PRINT command from the main menu bar at the top of the screen.

• Enter into the pull-down dialogue box the sample numbers to define the start and end of the datato be printed.

• Press the TAB key.

• Select the PRINT command.

NOTE: Form : [continuous] will generate a print-out of the data on a single, continuous piece of paper.

Loading and saving data and/or format files

• Enter DOS mode

• Select the SAVE or LOAD command from the main menu bar at the top of the screen

• Select from the pull-down menu the type of file to be saved to or loaded from the disk

• Enter the name of the file

NOTE: Data files contain the trace data and must have the file extension .ALA . Format files contain theset-up information and must have the file extension .FMT .

Leaving the logic analyser program


• Select the MODE command on the main menu bar at the top of the screen

• Select the QUIT command on the pull-down menu

22

PROFORMA REPORT

THIS SECTIONMUST BE COMPLETED BEFORE YOU COME INTO THE LAB

1. Explain the function of each of the VMEbus data transfer control signals and the operation of thedata transfer protocol.


TO BE COMPLETED IN THE LAB

1. Annotate the printed timing diagram of a Read Byte Cycle

2. What is the memory address from which the byte is read? NB remember to look at all the addresslines; you will have to move some of the logic probes.

Remember too that the lowest order address line is A1; you need to examine DS0 and DS1 too todetermine whether a high or low byte is read.

3. How long does it take to complete the data transfer?

4. What is the data transfer rate in bits/sec?

24

5. Annotate the timing diagram of the Write Cycle.

6. Discuss two ways in which it differs from the READ cycle.

7. Which ASCII code did you use to trigger the WRITE cycle?

8. Explain the operation of the protocol that is used to handle multi-level vectored interrupts on theVMEbus


9. Annotate the timing digram of a counter/timer Interrupt Acknowledge Cycle. The diagramshould show the interrupt being generated and acknowledged.

10. What level of interrupt request is being used by the counter/timer?

11. What is the interrupt address of the counter/timer.

12. Estimate the interrupt response time of the microcomputer.

13. Estimate how long it takes before the interrupt is cleared. In which routine does this occur?

EJP/DWMLast revised 14/10/2001 16:31˜ dwm/Teaching/Labs/CO3-00/prac2.tex

Lab Session 3

CS3: Macro- and micro-programming [3/11/00]

Some preparatory reading and Exercise 1 must be completed before arriving in the laboratory. This should take

about 30 minutes, and will help you get maximum benefit from the lab session.

3.1 Aims

The aims of this laboratory are (i) to observe register transfers within a simple processor using a graph-ical simulator and (ii) to appreciate how easy it is to generate the microcode for a controller. The simplecpu architecture simulated in this experiment differs from that seen in lectures — which is instructivein itself because it shows that there can be different outcomes in the design process of even simpleprocessors. The notes below should be sufficient to understand it ahead of the lab1.

3.2 Introduction (preparation: must read)

High-level computer languages are designed to simplify the translation of algorithms written on paper,using mathematical and logical notation, into executable machine code. The languages are designed tobe independent of hardware, and a program written in C, Fortran, Ada, etc, is portable to any computerwhich has the corresponding compiler, even though the data paths and available registers within the com-puter’s central processing unit may be quite different. In other words, the same high level code is translatedinto quite different sets of steps in RTL (Register Transfer Language).

The divide between high level language and lowest level register transfer transfers is bridged in severalstages, thereby increasing the independence of each. The compiler converts the high level code in asequence of macrocode or assembly code instructions in two passes. And the translation from assemblymnemonics into executable binary machine code is straightforward.

Each high level instructions might give rise to several macro instructions. For example, if we write c= a+b in the high level language, the compiler associates memory location Ma with a and so on, andwould produce macro code which might read as in the table on the left. In turn each macro instructionwill require several individual register transfers to fetch and execute it. For example, “LOAD the accu-mulator with the contents ofMa” might involve the micro instructions on the right, where sandwichedbetween the fetch and execute stages are possible transfers to decode the instruction.

1The reference is Chapter 4, Section 4.2, pages 126ff, of Tanenbaum’s Structured Computer Organization ed 2 (Prentice HallInternational ISBN 0-13-854605-3). This is now a rather old book, but one which your college library will (almost) certainlystill have.

26


1. LOAD the accumulator with the contents ofMa

2. ADD to the accumulator the contents ofMb

3. STORE the accumulator in locationMc

f1. mar ← pcf2. mbr ← M<mar>f3. ir ← mbrd1. decoding ir(opcode) ...

dn. ... decodinge1. mar ← pce1. mar ← ir(operand)e3. ac ← mbr

3.3 Data Registers and Paths (preparation: must read)

The data path of the processor being simulated is shown in Figure 1. This picture is a hard copy of theview you will get in the simulation program. In the processor unit there are the following:

Main Memory, accessed via the MAR Memory Address and MBR Memory Buffer Registers. Noticethat to get data from the MBR to the registers it has to go through the ALU.

16 registers, loaded from the C-bus, and outputted onto one or both of the A-bus and B-bus.

• PC – The program counter, used to control the sequence of a program. The program counter holdsthe memory address of the next instruction to be executed.

• AC – The accumulator, used for temporary data storage.

• SP – The stack pointer, used to control the stack, a LIFO temporary storage area in main memory.

• IR – The instruction register (IR) holds the assembly instruction being executed.

• TIR – Temporary instruction register, used during decoding.

• 0,-1,+1 – constant registers

• Amask and Smask – used during decoding.

• A to F – working registers.

The A- and B- latches are loaded from the A- and B-buses. They protect the ALU from changes in theregisters.

The AMUX chooses the source for input into the ALU: either from the Alatch, or from the MBR.

The ALU itself, and a shifter on its output, but separate from it.

28

NZ

Shifter

MARPC

AC

SP

IR

TIR

0

-1

+1

Amask

Smask

A

B

C

D

E

F

Alatch Blatch

AMUX

ALU

MBRData in

Data out

BbusAbusCbus

MainMemory

Fig 1: The Data Paths, Registers, ALU, and Memory

3.4 Micro-controller (preparation: must read)

The individual levels and pulses required to implement the RTL statements, or micro instructions,emerge as control lines from the cpu’s Control Unit. The CU could be hardwired (for example usinga D-type latch sequencer), but it can be conveniently realized using a PROM sequencer. This is shownon the right of Figure 2. The control lines emerge from the micro instruction register, µIR, as does theBranch Address required when jumps are required within the micro-program.

In this architecture each microinstruction has 32 bits, as shown in Figures 3, comprising 24 control linesand and 8 bit Branch Address.


Shifter

microMUX

microPCINC

microPROM

4 subphaseClock

4321

These lines controlthe 16 registers

and A,B,C bus outputs

To memory

NZ

microsequ.logic

Note Shifter is AFTER ALU N and Z flags

Alatch Blatch

AMUX

ALU

MAR

MBR

Address out

Data in

Data out

Cbus

Abus Bbus

The16

Registers

Main

Memory

CADDRABCR

W ENR

DMARR

BM

SHALUCOND

AMUX

Fig 2: The Microcoded controller (right) completing the cpu.

AMUX

MBR

MAR

D

ENC

B A ADDRCR W

R

COND

ALU SH

1 2 2 1 1 1 1 1 4 4 4

No of Bits

82

What the bits mean

AMUX

0=Alatch1=MBR

COND

0=No Jum1=Jump if N=12=Jump if Z=13=Jump always

ALU

1=A AND B2=A3=Complement(A)

SH

0=No Shift1=Shift Right2=Shift Left3=Not Used

MBR,MAR,RD,WR,ENC

0=No1=Yes

0=A PLUS B

Fig 3: Control Bits in the 32 bit µIR.

First 12 control lines. The 12 left-most (most significant) bits map directly onto control lines. As anexample, the leftmost bit of the microinstruction controls the AMUX. If it is 1, then the AMUX selectsthe Alatch input into the left side of the ALU, but if 0 then the MBR input is selected.

30

AMUX 1 bit controls left ALU input: 0 = input from MBR, 1 = input from AlatchALU 2 bits ALU function

See below!

SH 2 bits shifter function:00:no shift, 01:right shift one place, 10:left shift one place

MBR 1 bit 1: load MBR from shifter, 0: don’t load MBRMAR 1 bit 1: load MAR from B latch, 0: don’t load MARRD 1 bit 0: don’t read memory , 1: readWR 1 bit 0: don’t write memory, 1: writeENC 1 bit 1: store into registers from shifter, 0: don’t store

You’ll particularly need to understand the ALU control lines. The ALU can perform the followingoperations: 4 operations controlled by two bits

00 alu← A PLUS B arithmetic add01 alu← A AND B logical bitwise and10 alu← A leave unaltered11 alu← A bitwise complement

where A refers to data on the bus, B refers to data on the B bus, and alu is the output of the ALU. Alldata appearing at the output of the alu sets the N and Z flags. The ALU is 16 bits wide, so N = alu [15],and Z = alu[15] AND alu[14] AND ... AND alu[0].

The 12 control lines controlling main registers. The next 3 groups of 4 bits do not map directly tocontrol lines, but each group is passed through a 4-16 line decoder, and then used to control the inputand output of the 16 registers.

C selects register for loading from the C busB selects register to be Output-Enabled onto the B busA selects register to be Output-Enabled onto the A bus

For example, C=0000 indicates that the PC is to be loaded, C=0001 that the AC is to be loaded, andC=1111 indicates that F is to be loaded. The B and A groups of 4 bits are used to select which registersare output-enabled onto the B and A buses. Note that a register can be oe’d onto both at the same time.

The µPROM branch address. The 8 ADDR bits are used to effect jumps in the microcode. The µPCpoints to the location in the µPROMwhose contents are latched into the µIR. (The µIR could be thoughof as the “µMBR”.) Often the µPC is simply incremented via INC and themicroMUX. But themicroMUXcan select the the ADDR if the COND bits and the N and Z flags indicate it should.

The 4-subphase clock. The final key to understanding the cpu’s operation is to understand the oper-ation of the 4 subphase clock, which allows for data paths to be set up ahead of register transfers. Thesubphases are as follows:1. Latch the current µPROM output into the µIR.3. Clock the A and B latches.2. Clock the MAR (also requires MAR entry in µIR to be 1.4. Clock the µPC. If ENC=1, clock the register selected by C

3.5 The macro instructions (Preparation: must read)

All instructions are 16 bits long, but the opcodes take up either 4 or 7 bits, as shown in the leftmostcolumn below. Take a look at the first few instructions, which act on memory location x, m<x>: an


address y, or a number z.Opcode Mnem- Example Meaning RTL-ishBits onic description

0000 HALT HALT Halt program0001 LDA LDA x Load direct ac ← m<x>0010 STA STA x Store direct m<x> ← ac0011 ADD ADD x Add direct ac ← ac + m<x>0100 SUB SUB x Subtract direct ac ← ac - m<x>0101 BZE BZE y Branch if Z=1 if Z, pc←y0110 JMP JMP y Unconditional jump pc ← y0111 LDAI LDAI z Load immediate ac ← z1000 LODL LODL z Load through stack ac ← m<sp+z>1001 STOL STOL z Store through stack m<z+sp> ← ac1010 ADDL ADDL z Add through stack ac ← ac + m<sp+z>1011 SUBL SUBL z Subtract through stack ac ← ac - m<sp+z>1100 BMI BMI y Branch if N=1 if N, pc ← y1101 BPL BPL y Branch if N=0 if .not.N, pc ← y1110 JSR JSR y Jump to subroutine sp ← sp-1; m<sp>←pc;

pc←y1111000 INC INC Increment accumulator ac ← ac+11111001 DEC DEC Decrement accumulator ac←ac-11111010 PHA PHA Push sp ←sp-1; m<sp>←ac1111011 PLA PLA Pull ac←m<sp>; sp ←sp+11111100 RTS RTS Return form subr. pc←m<sp>;sp←sp+11111101 SWAP SWAP swap ac,sp tmp←ac;ac←sp;sp←tmp1111110 INS INS z Increment sp sp←sp+z1111111 DES DES z Decrement sp sp ← sp-z

3.6 EXERCISE 1A (last bit of preparation)

Suppose we had written and compiled the high level program.

int a;int b;int c;a = 200;b = 100;c = a + b;

In macro code and loaded into memory it appears as follows. Notice that:

• the Instruction in the leftmost column is what is actually loaded into memory into the contents atthe Memory Location. Both of these are in Hex.

• Any numbers use in the Mnemonic are in decimal.

/ prog1.macro---------------------------------------------------------------------Instru Memory Mnemonic % Comments-ction Location %

32

(hex) (hex) (uses decimal) %---------------------------------------------------------------------70c8 # 0000 LDAI 200 % Load the AC with decimal 2002007 # 0001 STA mema % Store in location mema7064 # 0002 LDAI 100 % Load the AC with decimal 1002008 # 0003 STA memb % Store in location memb3007 # 0004 ADD mema % Add cntnts of mema to the AC2009 # 0005 STA memc % Store AC in location memc0000 # 0006 HALT % halt the program0000 # 0007 mema: 0 % NB: Not program, but data !0000 # 0008 memb: 0 % Note that mema etc label0000 # 0009 memc: 0 % memory LOCATIONS---------------------------------------------------------------------

1. Noting that all of the opcodes in this program are 4 bits long, what are the hex opcodes for:

Opcode for LDAI Opcode for STA Opcode for ADD Opcode for HALT

2. Why does the instruction LDAI 100 appear as 7064 (hex) in memory?

3. Why does instruction STA memc appear as 2009 in memory?

4. Suppose the program counter, which indicates the memory location of the next instruction, is resetto 0, the AC is reset to 0, and the program run.

State the hexadecimal value in the accumulator AFTER each instruction executes.After LDAI After STA After LDAI After STA After ADD After STA After HALT

5. What would be the hex contents of the following the memory locations after the program halts?

Contents of mema Contents of memb Contents of memc

6. Suppose the entire block of program and data is relocated in memory to start at memory location000A (hex) rather than 0000.Where and howwould STA memc appear in memory now?


3.7 Getting started in the Lab [11:05]

• Read the instruction sheet provided in the lab for

• logging in, • creating a working directory, • copying files, and • starting simtool.

• You will have to work quite quickly. However don’t just copy down numbers from the simula-

tor mindlessly. Use the simulator to help you understand register transfers, and so on.

• To load the microcode into the µPROM, type engin.micro in the “Read Microcode” box and click

Read Microcode button. Over on the right, notice that the µPC=0, and the µPROM is showingthe contents of its location 0.

• Then loadmainmemory by typing prog1.macro into the “ReadMacrocode” box and hitting Read Macrocode .

Notice that the macro program and data are now in the main memory, with the program in yellowand the data in purple. The little green square in the memory indicates the memory locationpointed to by the MAR. It should be at location 0.

Notice that the PC=0, AC=0, SP=F0, etc. You can re-zero these by pressing Reset .

You can set a break point. Initially set on HALT , it can be changed by pressing the selection arrowand choosing the mnemonic. This will break the program execution just before the fetch of thegiven macro instruction. Leave it where it is for now.

• Now press Step Macro . You should see that PC=1, and that AC=00c8. We have indeed loaded-

immediate the accumulator with decimal 200. Press Step Macro again. Now 00c8 should be

stored in the location labelled by mema, which was 7.

• Now execute the rest of prog1 by pressing Run to Break at HALT. Get rid of the Warning dialogbox.

34

3.8 EXERCISE 1B [11:10]

1. Note down the memory contents of mema, memb, and memc, and confirm they agree with whatyou worked out in Exercise 1A.

2. Press Reset , and note down the PC and AC values as you Step Macro through the program

After LDAI After STA After LDAI After STA After ADD After STA After HALT

PC 0001 0002 0006

AC 00C8

3. Now observe the data paths used for register transfers, and the AMUX switching back a forwards.

Press Flash , Reset , then Step Macro through the program. and watch the data paths used for

register transfers light up, the AMUX switch back and forward and so on. Switch Flash OFFwhen you’ve done.

(If the changes are too fast, press Delay + between runs to slow them. If too slow, press Delay – .)


3.9 EXERCISE 2: Unconditional and Conditional Jumps [11:20]

Now let us look at an assembly language program fback.macro which might form the basis of a simplefeedback controller. It contains both unconditional and conditional jumps.

/ fback.macro100c # 0000 LDA demand % read demand into AC400d # 0001 SUB fback % ac has demand-fback5009 # 0002 BZE leavec006 # 0003 BMI lower7001 # 0004 raise: LDAI 1600a # 0005 JMP store7000 # 0006 lower: LDAI 0f200 # 0007 DEC600a # 0008 JMP store7000 # 0009 leave: LDAI 0200e # 000a store: STA out %store result0000 # 000b HALT000a # 000c demand: 10000c # 000d fback: 120000 # 000e out: 0

1. Using simtool, complete a trace of the registers showing the value of the PC BEFORE each in-struction is executed, the mnemonic for the instruction, and the values of AC and IR AFTER eachinstruction in the program program is executed, in the order of execution. Complete the tablebelow.

Clear Macro Mem , Load macro fback.macro, press Reset , and use Step Macro repeatedly.

PC before Instruction IR after AC after0000 LDA demand

SUB fbackBZE leave

HALT

36

2. In this instruction set, the instructions are 16 bits wide, and the opcodes are either 4 or 7 bits longand occupy themost significant bits. Write the 16-bit binary for the following instructions in blocksof 4-bits (nibbles), and underline (i) the opcode bits and, if relevant, (ii) the operand bits.

Mnemonic nibble nibble nibble nibbleLDAI 1BZE leaveDECSTA out

3. Suggest why the combination of LDAI 0 followed by DEC has been used to enter –1 into theaccumulator, rather than using LDAI –1. (Hint, think about the 2’s complement representation of−1.)

4. What numbers are in locations demand and fback?

5. Note down the values of the PC in detail. To do this, press Delay – a few times to reduce the flash

delay. Press Flash ON, Reset , and start watching the PC. Press Run to Break ,

(If it is too fast, press Delay + Reset , Run to Break , and try again. Better this way than starting

off with it too slow.)

6. The PC sequence is as found earlier, but by slowing things down you see that 4 and 9 appear too?Why?

7. What is the number in location out at the end of execution?

8. Edit2 fback.macro so the demand is bigger than fback. Save the macro file. Now set Flash OFF,

Clear Macro Mem , Load Macro fback.macro, Reset and Run to Break .

9. What is the value in memory location out?

2See the machine guidance on editing.


3.10 EXERCISE 3: Subroutines and IO addresses [Time 11:45]

We will now modify the previous program in two, quite unrelated, ways.

First, we will introduces io addresses. In a real system, the memory at these locations might be on a cardslotted into the buses rather than belonging to the main memory. When you load the program, theselocation will appear in cyan.

Secondly and more significantly, we will perform the comparison with a subroutine. The code mighthave been compiled from a high level statement like out = compare (demand, feedback).

An area of memory called the stack is used to transfer the parameters to the subroutine, and to store thereturn address, and to store the return value. For returnvalue = subname (param1, param2), the callingprogram pushes the parameters onto the stack in reverse order. By using JSR comp, it then pushes thereturn address (here 5) onto the stack, and jumps to location comp (see the table of macrocodes earlier).

Within the subroutine, instead of popping the parameters off the stack (which would be messy, becausethe return address would have to be popped, stored, then pushed), the instructions LODL and SUBL areused which perform indexed addressing relative to the stack pointer. Because we pushed in reversedorder, parameter number P is accessible using LODL P.

/ fbacksub.macro10f9 # 0000 LDA cardf % read fback from cardf400 # 0001 PHA % push onto stack10f8 # 0002 LDA cardd % read demand from cardf400 # 0003 PHA % push onto stacke009 # 0004 JSR comp % jump to subroutine compf600 # 0005 PLA % pull answer from stack20fa # 0006 STA cardo % output the answerfc01 # 0007 INS 1 % increment SP to clean up0000 # 0008 HALT %

8001 # 0009 compare:LODL 1 % indexed relative to SPb002 # 000a SUBL 2 % indexed relative to SP5012 # 000b BZE leave %c00f # 000c BMI lower %7001 # 000d raise: LDAI 1 %6013 # 000e JMP store %7000 # 000f lower: LDAI 0 %f200 # 0010 DEC6013 # 0011 JMP store %7001 # 0012 leave: LDAI 0 %9001 # 0013 store: STOL 1 % store result relative to SPf800 # 0014 RTS % return from subroutine

000a # 00f8 cardd: 10000c # 00f9 cardf: 110000 # 00fa cardo: 0

38

1. Clear Macro Mem Load Macro fbacksub.macro, Reset . Now Step Macro through the pro-gram.

The stack is empty initially, and SP=F0. Note that in this cpu, the SP is decremented before writingto the stack, so the SP points to the “last filled location”. In the notes we write to the stack thandecrement, so the SP points to the “next empty location”.)

The simulator will indicate values in the stack using RED.

For each of the 7 times the stack or values on the stack change, fill a table of stack contents, anddraw an arrow in the leftmost column to indicate where the SP is pointing. Add a comment toindicate what has happened.

Stack after 1st PHA (push) executesSPLocation Contents

F0 never part of stack→ EF 000B

EEEDECEB

Com: Pushed on Param2 (feedback)

Stack after ..................... executesSP Location Contents

F0 never part of stackEFEEEDECEB

Com:



Com:



Com:



Com:



Com:



Com:


3.11 Exploring Microcode [Time 12:10]

The file engin.micro contains the microcode to interpret each macro instruction of the assembly languageprogram. In this section you are to examine the microcode implementation of the ADD instruction, andthen to modify it. We will use prog1.macro.

/ prog1.macro70c8 # 0000 LDAI 200 % Load the AC with decimal 2002007 # 0001 STA mema % Store in location mema7064 # 0002 LDAI 100 % Load the AC with decimal 1002008 # 0003 STA memb % Store in location memb3007 # 0004 ADD mema % Add cntnts of mema to the AC2009 # 0005 STA memc % Store in location memb0000 # 0006 HALT % halt the program0000 # 0007 mema: 0 % NB: Not program, but data !0000 # 0008 memb: 0 % Note that mema etc label0000 # 0009 memc: 0 % memory LOCATIONS

EXERCISE 3A

Reset macro mem , Load macro file prog1.macro, Reset , Set Break at , ADD, then Run , then Set Break atHALT.

The processor is sitting at the start of the fetch of the ADD instruction. You should see that the µPC=0,and the microcode for “mar:=pc” is in the µPROM.

Let’s first check out how each microinstruction is performed in four steps. To better see what changes,

put on Flash , and press Delay + a couple of times to slow things down substantially. In any case,

don’t rush this part.

The steps of the subphase clock do the following:

1. Latch the current µPROM output into the µIR.

So look at the µIR, and press Step SubPhase . The SubPhase light will move onto the next phase,

and the binary 00011000100...0000 is transferred from the PROM into the µIR as 1880000 (hex).

2. Clock the A and B latches.

Because the BBUS and ABUS bits are both 0, the PC gets latched in both. Press Step SubPhase .

3. If MAR bit is 1, clock the MAR.

It is 1, so thismoveswhat is in the B latch into theMAR.Watch theMAR and press Step SubPhase .

4. Clock the µPC. If ENC=1, clock the register selected by C

Watch the µPC. Notice that the µMUX is connecting the incrementer to the µPC. ENC=0, so no

action in the registers. Press Step SubPhase .

Now do the same for the next microinstruction “pc=pc+1;rd”.

1. Latch the current µPROM output into the µIR. Step SubPhase . The µIR as 80506000 (hex). No-

tice that AMUX connects to the Alatch, because the AMUX bit is 1. Also notice that the BBUS bits

40

are 0110, saying that the +1 register is output-enabled onto the Bbus, and ABUS=0000, saying thatthe PC is output-enabled onto the Abus.

2. Clock the A and B latches.

Watch the Alatch and Blatch. Step SubPhase . The Blatch is load with 1. Notice that the ALU bits

are 00 making the ALU add up 4 plus to give an output of 5.

3. If MAR bit is 1, clock the MAR.

The MAR bit is 0, so nowt happens. Press Step SubPhase .

4. Clock the µPC. If ENC=1, clock the register selected by CBUS bits.

Now these are 0, so the PC is going to get loaded with the output of the ALU/Shifter. Also RD=1.So the MBR will get loaded with the contents pointed to by the MAR — that is location 4. Watchthe MBR change to 3007.

As before the µPC also increments.

So Step SubPhase .

EXERCISE 3B [12:20]

The 1st Subphase light should now be on.

Press Delay – a few times to reduce the flashing time, and repeatedly press Step Micro through the

remaining fetch, decode and execute microinstructions of ADD.

1. Confirm, just for one or two lines, that the following table gives the register and flag contents lineof microcode in the instruction cycle for the ADD instruction.

(The N flag is observable in the ALU, and the COND bits are bits 2 and 3 (counting from the left)in the µIR.)

Microinstruction uPC PC IR TIR AC MAR MBR N CONDBefore mar←pc; 0 0004 2008 0040 0064 0008 0064 0 00

Before pc←pc+1;rd; 1 0004 2008 0040 0064 0004 0064 1 00

Before ir←mbr;if n then goto 35; 2 0005 2008 0040 0064 0004 3007 0 01

Before tir←lshift(ir+ir);if n then goto 16; 3 0005 3007 0040 0064 0004 3007 0 01

Before tir←lshift(tir);if n then goto 10; 4 0005 3007 c01c 0064 0004 3007 0 01

Before alu←tir;if n then goto 13; a 0005 3007 8038 0064 0004 3007 1 01

Before mar←ir; d 0005 3007 8038 0064 0004 3007 1 00

Before rd; e 0005 3007 8038 0064 0007 3007 0 00

Before ac←mbr+ac;goto 0; f 0005 3007 8038 0064 0007 00c8 0 11

Before mar←pc; 0 0005 3007 8038 012c 0007 00c8 0 00


2. Identify on the table the instruction fetch, decoding and execution phases of the instruction cycle.

3. Illustrate by drawing arrows between values on the above trace why register values change as they do.For example, before mar←pc, the PC=4 and MAR=8. Afterwards, MAR=4.

4. Opcodes are decoded serially, ie. bit by bit, in this architecture. By determining whether the left-most msb bit of the instruction is 0 or 1, the set of opcodes is divided into two; then by determiningwhether the next bit is 0 or 1, the set is split again. The microprogram traverses a binary decisiontree. (See the microcode at the end.)

(a) Look at the data path that the instruction takes fromMBR to IR during ir←mbr. Explain howthe 1st bit (the msb) of the opcode is determined using the N flag.

(b) Note that the N flag emerges from the ALU, not the Shifter. How is the 2nd bit determinedduring tir←lshift(ir+ir)? (+ is PLUS here. tir denotes temporary instruction register).

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3.12 Altering the Microcode [12:40]

In this final part, you are going to mess about with the microcode.

EXERCISE 4

1. Using Appendix C and/or the table of the previous exercise, identify the appropriate line of mi-crocodewhere the addition actually takes place.

LINE =

2. What device on the CPU actually does the addition? Use Figure 3 to determine where exactly thedevice’s function-select bits occur in the µIR.

3. Now edit the line in the micro file engin.micro, changing the bits so that the macrocode mnemonicADD actually performs a logical AND instead.

4. Save the newmicrocode as corrupt.micro. Clear Micro Memory and Load Microcode corrupt.micro,

Reset , and Run .

5. What value is now in the AC after execution?

6. Remember that before you were adding c8 to 64.

What is the ADD actually doing now?

Hence explain the AC’s value.


APPENDIX: The MICROPROGRAM

The binary version of this file is contained in engin.micro.

mic description comment0: mar←pc;rd; instruction fetch starts1: pc←pc+1;rd;2: ir←mbr;if n then goto 35; decoding starts here3: tir←lshift(ir+ir);if n then goto 16;4: tir←lshift(tir);if n then goto 10;5: alu←tir;if n then goto 7;6: goto 6; halt execution7: mar←ir;rd; lda execution8: rd;9: ac←mbr;goto 0;10: alu←tir;if n then goto 13;11: mar←ir;mbr←ac;wr; sta execution12: wr;goto 0;13: mar←ir;rd; add execution14: rd;15: ac←mbr+ac;goto 0;16: tir←lshift(tir);if n then goto 32;17: alu←tir;if n then goto 22;18: mar←ir;rd; sub execution19: ac←ac+1;rd;20: a←inv(mbr);21: ac←ac+a;goto 0;22: alu←ac; if z goto 24; bze execution23: goto 0;24: pc←band(amask,ir);goto 0;

(Some old stuff removed: hence gap)32: alu←tir;if n then goto 34;33: pc←band(amask,ir);goto 0; jump execution34: ac←band(ir,amask);goto 0; ldai execution35: tir←lshift(ir+ir);if n then goto 47;36: tir←lshift(tir);if n then goto 42;37: alu←tir;if n then goto 40;38: a←ir+sp; lodl execution39: mar←a;rd;goto 8;40: a←ir+sp; stol execution41: mar←a;mbr←ac;wr;goto 12;42: alu←tir;if n then goto 45;43: a←ir+sp; addl execution44: mar←a;rd;goto 14;45: a←ir+sp; subl execution46: mar←a;rd;goto 19;47: tir←lshift(tir);if n then goto 55;48: alu←tir;if n then goto 53;49: alu←ac;if n then goto 51; bmi execution50: goto 0;51: pc←band(amask,ir);goto 0;

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(gap)53: alu←ac; if n goto 0; bpl execution54: pc←band(amask,ir); goto 0;55: tir←lshift(tir);if n then goto 59;56: sp←sp+(-1); call execution57: mar←sp;mbr←pc;wr;58: pc←band(ir,amask);wr;goto 0;59: tir←lshift(tir);if n then goto 70;60: tir←lshift(tir);if n then goto 64;61: alu←tir;if n then goto 63;62: ac←ac+1;goto 0; inc execution63: ac←ac+(-1);goto 0; dec execution64: alu←tir;if n then goto 67;65: sp←sp+(-1); push execution66: mar←sp;mbr←ac;wr;goto 12;67: mar←sp;sp←1+sp;rd; pop execution68: rd;69: ac←mbr;goto 0;70: tir←lshift(tir);if n then goto 78;71: alu←tir;if n then goto 75;72: mar←sp;sp←1+sp;rd; rts execution73: rd;74: pc←mbr;goto 0;75: a←ac; swap execution76: ac←sp;77: sp←a;goto 0;78: tir←lshift(tir);if n then goto 81;79: a←band(ir,smask); ins execution80: sp←sp+a;goto 0;81: a←band(ir,smask); des execution82: a←inv(a);83: a←a+1;goto 80;

Last revised 3/11/2000 11:10˜ dwm/Teaching/Labs/CO3-00/prac3.tex

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