352 IEEE TRANSACTIONS ON COMPONENTS,...

352 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 1, NO. 3, MARCH 2011

Effects of Electrical Characteristics on theNon-Rectangular Gate Structure Variations

for the Multifinger MOSFETsChulhyun Park, Student Member, IEEE, Youngkyu Song, Student Member, IEEE, Jung Han Kang, Student Member,

IEEE, Seong-Ook Jung, Senior Member, IEEE, and Ilgu Yun, Senior Member, IEEE

Abstract—In this paper, modeling methodology of electricalcharacteristics for non-rectangular gate structured multifingermetal-oxide-semiconductor field-effect transistors based on min-imum channel length is proposed. The test structures are fabri-cated and the parasitic model parameters are extracted using themeasured data for the proposed model. The proposed model cansupport better physical explanation than the previously presentedintegrated length model. The proposed model can preciselyexplain the electrical characteristics and is supported by theoret-ical equations for non-rectangular gates, such as the thresholdvoltage, the saturation voltage, the saturation current, and theleakage current. However, the previous integrated length modelcannot sufficiently explain the electrical characteristics for non-rectangular gates although it is sustained by theoretical equations.Furthermore, this paper shows the relationship between gate polyarea and the electrical characteristics. As a result, the electricalcharacteristics are dependent on the variation of the minimum ofthe gate length, rather than the profile of gate length variation.

Index Terms—Characteristic fluctuation, large-signal model-ing, multifinger MOSFET, non-rectangular gate.

I. Introduction

DUE TO THE limitation of semiconductor process, es-pecially, lithography and diffusion, the printed images

through the process have the variation of the patterned geome-try. The variation causes problems, such as electrical character-istic fluctuations, and it is aggravated by the technology scal-ing. If these phenomena occurred during the lithography anddiffusion process to form the gate poly structure, the devicecharacteristics, such as the threshold voltage, the sub-thresholdleakage current, and the on-current, should have very largevariations. References [1] and [2] showed using lithographyprocess result via technology computer-aided design (TCAD)aerial image simulations. However, it is not feasible to forma rectangular gate structure due to lithography variations and

Manuscript received July 14, 2010; revised October 10, 2010; acceptedNovember 13, 2010. Date of publication March 7, 2011; date of cur-rent version April 8, 2011. This work was supported by the Institute ofTelecommunication, Multimedia, and SOC Information Technology, YonseiUniversity, Seoul, Korea, under the Brain Korea 21 Program. Recommendedfor publication by Associate Editor B. Courtois upon evaluation of reviewers’comments.

The authors are with the Department of Electrical and Electronic En-gineering, Yonsei University, Seoul 120-749, Korea (e-mail: chulhyun−[email protected]; [email protected]; [email protected];[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCPMT.2010.2099532

line edge roughness effect. Thus, the gate length is not uniformin the device structure after the lithography process. Thisaggravates the leakage current in the area where gate lengthis shorter than nominal. Furthermore, this can make thresholdvoltage dependent on the position [3].

Threshold voltage is lower at the short-gate length thanat the long-gate length. Leakage current predominantly flowsat the shorter gate length, especially, the edge of gate poly.To reduce the leakage current or to compensate the thresholdvoltage at short-gate length, previous research suggested thelayout method that is verified by TCAD simulation [4], [5].However, the limitation is that their results are only basedon the rectangular gate structures. Thus, in this paper, theelectrical characteristics of the non-rectangular gate structuresof multifinger metal-oxide-semiconductor field-effect transis-tors (MOSFETs) are measured and analyzed. Based on theparasitic model parameter extraction results, the relationshipbetween the geometry-dependent gate length variation andthe electrical characteristics, such as the threshold voltage,the saturation voltage, the saturation current, and the leakagecurrent, is analyzed and compared with the results of theprevious integrated length model [5].

II. Test Structure SETs and Fabrication

Test structures are composed of three sets: SET1 is com-posed of the test structures with unit length such as 140 nm and260 nm for reference shown in Fig. 1(a); SET2 is constructedwith the test structures where gate length is shrunken from260 nm to 140 nm at inside width shown in Fig. 1(b); andSET3 is made up of the test structures where gate lengthis shrunken from 260 nm to 140 nm at outside width shownin Fig. 1(c). All of the test structures are composed ofmultifinger type gates with four fingers and they are fabricatedby Samsung 130 nm process technology. Connection betweeninside and outside width is realized by the oblique line andthe angle is designed to be 45°. Minimum gate length for allof the test structures is 140 nm and maximum gate length is260 nm. In addition, the gate width of test structures is 600 nmand the number of the finger is 4. The layout condition fortest structure fabrication is summarized in Table I.

The test structures are measured using standard analysistechniques. For the I–V measurements, HP 4145B semicon-

2156-3950/$26.00 c© 2011 IEEE

PARK et al.: EFFECTS OF ELECTRICAL CHARACTERISTICS ON THE NON-RECTANGULAR GATE STRUCTURE VARIATIONS FOR THE MULTIFINGER 353

TABLE I

Fabrication Condition for Experiment

SET Structure Inside Width (nm) Outside Width (nm) Reference

1C1 Length = 140 nm, width = 600 nm

Fig. 1(a)C2 Length = 260 nm, width = 600 nmC3 100 500

2 C4 300 300 Fig. 1(b)C5 500 100C6 100 500

3 C7 300 300 Fig. 1(c)C8 500 100

Fig. 1. Schematic images of test structures. (a) SET1. (b) SET2. (c) SET3.

ductor parameter analyzer is used in conjunction with a probestation and the ground-signal-ground configuration probes.The measured data is stored with the aid of computer dataacquisition software and equipment. For removing the padparasitic components, the de-embedding patterns, such as thru,short, and open patterns, are also fabricated. Fig. 2 showsthe microscopic image after dicing. Here, the pad patterns arelocated by extremely right column.

III. Equivalent Circuit Model and the Parameter

Extraction

Simulations are based on Berkeley short-channel insulatedgate field effect transistor model (BSIM)4v4.2 [6]–[8] andlevel 54 for simulation program with integrated circuit em-phasis. Thus, the equivalent circuit model is composed ofthe BSIM4v4.2 core model and four parasitic components asshown in Fig. 3 [9].

The parasitic resistances are composed of the gate resistance(RGATE), the source resistance (RSOURCE), the drain resistance(RDRAIN), and the substrate resistance (RSUBSTRATE) as shownin Fig. 3. RSOURCE and RDRAIN include the metal contact

Fig. 2. Microscopic image of the test structures and the de-embeddingpatterns.

Fig. 3. Equivalent circuit MOSFET model with parasitic resistances.

resistances for the source and the drain, respectively. RGATE

include the silicon oxide (SiO2) resistance. In addition, thesubstrate of all test structures is tied with the source. RGATE

and RSUBSTRATE are almost unchanged because the gate isfloated and then, the gate leakage is very small in simulationand the substrate has very large resistance due to be tied withthe source. However, RSOURCE and RDRAIN are the key factorsto affect the device characteristics [9]. Thus, RSOURCE andRDRAIN should be examined to analyze the device character-istics in this paper.

To simulate the characteristics of the non-rectangular gatedevices, the integrated length model is previously proposedas shown in Fig. 4 [1]. In case of the non-rectangular gatedevices, the flowing current density is different according tothe gate length. Thus, for the integrated length model, eachcurrent density is represented by the corresponding currentsource shown in Fig. 4. Finally, the total current for the non-rectangular gate device can be approximately expressed bysingle transistor which the value of gate length is calculatedusing the integration along width direction as follows:

Linteg =

∑

WidthL

Width. (1)

However, the integrated length model requires time-consuming process to calculate the gate length and it is noteasy to know the gate length exactly using (1). In order toremove the complexity of calculation, the proposed model issuggested which is based on the minimum gate length. Thesimulation conditions for both the integrated length and theproposed model are summarized in Table II.


Fig. 4. Integrated length model for simulation.

TABLE II

Simulation Conditions for the Integrated Length and the

Proposed Model

SET Structure Integrated Length Proposed ModelModel (nm) (nm)

1C1 140 140C2 260 260C3 241.2 140

2 C4 201.2 140C5 161.2 140C6 158.8 140

3 C7 198.8 140C8 238.8 140

For simulations using the two models, the measurement dataare extracted from three dies in order to ensure the reliabilityof measurement and to confirm the inter-die variation. Theerror is then calculated so as to compare the accuracy of themodels. The error is extracted as follows:

Error (%)=

[abs(Measured data − Simulated data)

Measured data

]

× 100.

(2)Based on (2), the parasitic resistances are extracted to

make minimum error using two models. For the case of theintegrated length model, if the current level of the simulationresults is lower than that of measurement, then it is impossibleto extract the parasitic resistances and optimize to makeminimum error. Thus, all four resistance values are set tobe the same minimum value of 2.237 � which contains onlythe pad resistance. The extracted parasitic model parametersof the proposed model are summarized in Table III. Here, thepad resistance is found from the de-embedding patterns, suchas thru, open, and short patterns, in the test chip.

The comparison of ID−VG plots of the test structure C3 forvarious modeling results with the measured data is presented inFig. 5 to prove whether the proposed model is underestimatedor overestimated. It is indicated that the proposed modelis neither underestimated nor overestimated in sub-thresholdregion. Here, in the gate voltage near 0-V, the measured datais little deviated from the modeling data since the modelingdid not include the defect model. Other test structures alsoshowed similar results.

Fig. 5. Comparison of ID −IG plots for various modeling results for the teststructure C3 with the measured data.

Fig. 6. Comparison of ID − VD plots for various modeling results for thetest structure C3 with the measured data.

Fig. 6 also shows the comparison of ID−VD plots ofthe test structure C3 for various modeling results with themeasured data. The data for BSIM with minimum lengthis the simulation result using BSIM core model and theminimum gate length. For this case, parasitic effect is notconsidered. If we add the parasitic components to this model,the combined model is defined as the proposed model. On thecontrary, the data for BSIM with the integrated length is thesimulation result using BSIM core model with the integratedgate length without considering any parasitic components. Ifwe add the parasitic components to this model, the combinedmodel becomes the integrated length model. Based on theresults, the proposed model is proven to be the most accuratemodel. Other test structures also showed similar results.

The calculated errors using two models for various teststructures are presented in Fig. 7. Since the simulation condi-tion of the integrated length and the proposed model are equalto each other in C1 and C2, the errors of C1 and C2 are thesame. However, the error of C2 is larger than that of C1. Thatis, it is hard to explain the characteristics of C2 using two mod-els since the current level of simulation is lower than that ofthe measurement. From this fact, it is possible to infer that thegate length of C2 is smaller than the layout of C2 because theprocess is optimized for minimum gate length. Based on the


TABLE III

Summary of the Extracted Parasitic Parameters for the Proposed Model

SET StructureLength Width Gate Poly Area Avg. of Std. of Avg. of Std. of

RPAD (�)(nm) (nm) (µm2) RDRAIN (�) RDRAIN RSOURCE (�) RSOURCE

1C1 140 600 0.84 2.2370 0.0000 4.7788 0.9241 2.237C2 260 600 1.56 2.2370 0.0000 2.2370 0.0000 2.237C3 140 600 1.4472 3.2376 1.7158 24.9664 1.9232 2.237

2 C4 140 600 1.2072 3.0737 1.4493 14.3675 3.3471 2.237C5 140 600 0.9672 2.2370 0.0000 5.3219 1.6108 2.237C6 140 600 0.9528 2.2370 0.0000 6.2329 1.0441 2.237

3 C7 140 600 1.1928 2.7948 0.9661 13.7961 2.7885 2.237C8 140 600 1.4328 3.4270 2.0611 28.6234 3.9165 2.237

Fig. 7. Error bar graph of the proposed and the integrated length model forthe test structures.

results from C3 to C8 shown in Fig. 7, it is indicated that theproposed model is more reliable, reasonable, and accuratethan the integrated length model due to smaller error ofthe proposed model in general.

IV. Analysis of Device Characteristics

A. Threshold Voltage Fluctuation

The trend of the threshold voltage using two models isshown in Fig. 8. The trend of the proposed model is dia-metrically opposed to that of the integrated length model. Inorder to analyze the threshold voltage characteristic variation,refer to the BSIM4 equation [10] as follows:

VTH=VTH0 + δNP (�VT,body−effect − �VT,charge−sharing

�VT,DIBL + �VT,reverse−short−channel

+�VT,narrow−width

+�VT,small−size) (3)

�VT,body−effect

=

[

K1TOXE

TOXM· (

√2φf − VBS,eff − √

2φf ) − K2 · VBS,eff

]

×√

1 +LPEB

Leff

− K2TOXE

TOXMVBS,eff (4)

Fig. 8. Threshold voltage fluctuations for the proposed and the integratedlength model.

�VT,small−size

= DVT0W

[

exp

(

−DVT1WWeff Leff

2Ltw

)

+2 exp

(

−DVT1WWeff Leff

Ltw

)](Vbi − 2φf

).

(5)

In case of the proposed model, the threshold voltage isnot related to effective gate length (Leff ) because the modelis based on the usage of the minimum gate length for eachgate structure. Thus, the threshold voltage is influenced by theeffective body-source voltage (VBS,eff ), which is equal to thevalue of body voltage (VB) subtracted by source voltage (VS)in (3) and (4). It is found that the RSOURCE for C5 is almost fivetimes smaller than that of C3 in Table III whereas the currentlevel of C5 is almost 30% larger than that of C3. Thus, thesource voltage (Vs) of C3 is smaller than that of C5 and VBS,eff

of C3 is also smaller than that of C5. Thus, it can be concludedthat the proposed model can support the mechanism based onthe above explanation since the threshold voltage of C3 islarger than that of C5. In addition, the threshold voltage trendusing the proposed model is equal to the expected trend whenlayout is designed. However, for the integrated length modelcase, �VT,small−size is increased by (5) as Leff is decreased.Thus, the threshold voltage is increase from C3 to C5 as shownin Fig. 8. It is possible to adapt easily to the same explanationfor C6, C7, and C8. Based on these results, it can be concluded


Fig. 9. Saturation voltage fluctuations for the proposed and the integratedlength model.

that the value of the threshold voltage rely on the gate polyarea regardless of the geometry of the gate poly.

B. Saturation Voltage Fluctuation

The trend of the saturation voltage which is inverselyproportional to the threshold voltage is presented in Fig. 9. Itcan be explained using the BSIM4 equations. In the equivalentcircuit, the parasitic resistance between drain and source, RDS,does not exist. Thus, it is possible to adopt [10] as follows:

VDSsat =Esat · Leff · (

VGST,efft + 2kT/q)

Abulk · Esat · Leff +(VGST,eff + 2kT/q

) (6)

VGST,eff = Vg − Vs − VTH. (7)

In case of the proposed model, Leff is fixed, thus, thevariation is accounted for the parasitic resistances. Further-more, the effective gate-source threshold voltage (VGST,eff ) isincreased from C3 to C5 because the threshold voltage and VS

is decreased by (7). Finally, the saturation voltage is increasedby (6). However, in the integrated length model, Leff is oneof the factors and thus it has the variation. Since the variationof Leff is larger than that of VGST,eff and Leff is decreased,the saturation voltage is decreased by (6).

VGST,eff is decreased from C6 to C8 due to the thresholdvoltage and VS in the proposed model. Thus, the satura-tion voltage is decreased. However, the saturation voltageis increased since Leff is increased in the integrated lengthmodel. As mentioned in the threshold voltage fluctuation, thesaturation voltage is only dependent on the gate poly area.

C. Saturation Current Fluctuation

The saturation current is measured at the condition on whichboth the gate and the drain voltage are fixed at 1-V as anoperating mode. The difference between the proposed and theintegrated length model in the saturation current is shown inFig. 10. The saturation current of the proposed model is largerthan that of the integrated length model. It is indicated thatthe proposed model is more accurate than the integrated lengthmodel since the error of the proposed model is smaller thanthat of the integrated length model as shown in Fig. 7.

Fig. 10. Saturation current fluctuations for the proposed and the integratedlength model.

The values of the saturation current from C3 to C8 arelocated in between C1 and C2, as expected. It is found that thevalues of the saturation current for both models are validatedand it can be theoretically explained using BSIM4 equation[10] as follows:

IDSsat =IDS,0

1 +RDSIDS,0

VDS,eff

(

1 +1

Cclm

lnVA

VA,sat

)

×(

1 +VDS,sat − VDS,eff

VA,DIBL

)

×(


FA,DITS

)

×(


VA,SCBE

)

× NF (8)

IDS,0 =Weff µeff C

′ox,IV VGST,eff

Leff

[1 + VDS,eff /(εsatLeff )

]

[

1 − AbulkVDS,eff

2(VGST,eff + 2kT/q

)

]

VDS,eff . (9)

In the proposed model, Leff is fixed as the minimum gatelength, 140 nm, however, Leff of the integrated length modelhave the integrated value in Table II. If Leff is larger thanbefore, IDS,0 is decreased as (9) and finally, the saturationcurrent is also decreased as (8). The saturation current isincreased from C3 to C5 since VGST,eff and the saturationvoltage is also increased in the proposed model. On thecontrary, IDS,0 is increased since Leff is decreased thoughVGST,eff is decreased in the integrated length model. In caseof C6, C7, and C8, it is possible to explain the similar wayfor both models. Based on the results and (8) and (9), thesaturation current is only dependent on the gate poly area.

D. Leakage Current Fluctuation

The leakage current is defined as a current flowing betweenthe drain and the source when the gate voltage is fixed at 1-Vto form the channel and the drain voltage is set to be 0.04-V.The trend of the leakage current is presented in Fig. 11, whichis the similar trend of the saturation current. The analysis of


Fig. 11. Leakage current fluctuations for the proposed and the integratedlength model.

the leakage current can be extracted from the BSIM4 equation[10] as follows:

Isub =

(ALPHA0

Leff

+ ALPHA1

)(VDS − VDS,eff

)

exp

[

− BETA0

VDS − VDS,eff

]

× IDS. (10)

The leakage current is proportional to the saturation currentbased on (10). The results shown in Fig. 11 are very reasonablesince the trend of the leakage current is inversely proportionalto that of the threshold voltage as expected in the proposedmodel. Moreover, the result of the proposed model is moreaccurate than that of the integrated length model since the errorof the proposed model is smaller than that of the integratedlength model as in Fig. 7.

V. Conclusion

The effects of process variation on electrical characteristicsof the multifinger MOSFETs with non-rectangular gates havebeen investigated. In order to construct the equivalent circuitmodels for the MOSFETs, two models were explored. Onewas the integrated length model which had been calculatedby dividing the gate area into gate width and the other modelwas the proposed model which used the minimum gate length,and the parasitic resistances were also extracted from I–Vmeasurement data to compensate the effect of non-rectangulargates. Based on the modeling results, the error of the proposedmodel was smaller than that of the integrated length model.Furthermore, the trend of the electrical characteristic usingthe proposed model can support the gate geometry variationeffect where as the integrated length model cannot sufficientlyexplain the trend of the layout-dependent MOSFET character-istics. In order to verify the difference between two models,the device characteristics, such as the threshold voltage, thesaturation voltage, the saturation current, and the leakage cur-rent, were investigated. Therefore, the results of the proposedmodel were well represented by all of the predefined equationsand explained fairly well for layout-dependent MOSFET char-acteristics. For the gate poly area variation, the characteristics

were only related with the quantity of the gate length variation,and they were not influenced by the position of the gate lengthvariation and the device characteristics were almost the sameif the gate areas were similar for the devices.

VI. Acknowledgment

The computer-aided design tool was supported by the Inte-grated Circuit Design Education Center, Daejeon, Korea.

References

[1] R. Singhal, A. Balijepalli, A. Subramaniam, F. Liu, S. Nassif, andY. Cao, “Modeling and analysis of non-rectangular gate for post-lithography circuit simulation,” in Proc. IEEE DAC, Jun. 2007, pp. 823–828.

[2] J. Mitra, P. Yu, and D. Z. Pan, “RADAR: RET-aware detailed routingusing fast lithography simulations,” in Proc. ACM/IEEE DAC, Jun. 2005,pp. 369–372.

[3] P. Gupta, A. Kahng, Y. Kim, S. Shah, and D. Sylvester, “Modeling ofnon-uniform device geometries for post-lithography circuit analysis,” inProc. SPIE, vol. 6156, pp. 237–246, Feb. 2006.

[4] L. W. Liebmann, S. M. Mansfield, A. K. Wong, M. A. Lavin, W.C. Leipold, and T. G. Dunham, “TCAD development for lithographyresolution enhancement,” IBM J. Res. Develop., vol. 45, no. 5, pp. 651–665, Sep. 2001.

[5] S. P. Kornachuk and M. C. Smayling, “New strategies for griddedphysical design for 32 nm technologies and beyond,” in Proc. Int. Symp.Phys. Des., 2009, pp. 61–62.

[6] C. Hu, “BSIM3v3 model release note,” Dept. Electric. Eng. Comput.Sci., Univ. California, Berkeley, Sep. 1995.

[7] Y. Cheng, M. C. Jeng, Z. Liu, J. Huang, M. Chan, K. Chen, P. Ko, and C.Hu, “A physical and scalable I-V model in BSIM3v3 for analog/digitalcircuit simulation,” IEEE Trans. Electron Dev., vol. 44, no. 2, pp. 277–287, Feb. 1997.

[8] BSIM3v3 Model Development Group [Online]. Available: http://www-device.EECS.Berkeley.EDU/bsim3

[9] C. Park, J. Kang, and I. Yun, “Statistical modeling of layout-dependentcharacteristic fluctuations for multifinger MOSFETs,” in Proc. IEEEConf. Electron Devices Solid-State Circuits, Dec. 2008, pp. 1–4.

[10] W. Liu, MOSFET Models for SPICE Simulation, Including BSIM3v3and BSIM4. New York: Wiley, Feb. 2001.

Chulhyun Park (S’08) received the B.S. and M.S.degrees in electrical and electronic engineering fromYonsei University, Seoul, Korea, in 2008 and 2010,respectively.

He is currently a Researcher with Hynix Semicon-ductor, Icheon, Korea. He is working on the analogcircuit design and analysis of process, voltage, andtemperature variation for memory. His current re-search interests include characteristics of MOSFETfor analog and digital, nonlinear, and statisticalmodeling of devices and circuits, and technology

computer-aided design simulations.

Youngkyu Song (S’10) received the B.S. and M.S.degrees from the Department of Electrical and Elec-tronic Engineering from Yonsei University, Seoul,Korea, in 2008 and 2010, respectively.

He worked on technology computer-aided designmodeling of multifinger metal-oxide-semiconductordevices and the performance/reliability degradationeffect of MOSFET devices from laser drilling pro-cess. Since 2010, he has been with LG Display, Paju,Korea. His current research interests include lowtemperature poly silicon thin-film transistor process

and structure, and active matrix organic light emitting diode mask reductionprocess.


Jung Han Kang (S’08) received the B.S. degreein electrical engineering from Yonsei University,Seoul, Korea, in 2005. He is currently pursuing thePh.D. degree from the Department of Electrical andElectronic Engineering, Yonsei University.

His current research interests include modeling andsimulation of semiconductor devices and integratedcircuits, which recently include nanowire field-effecttransistors with high-k dielectric material, silicon-based MOSFETs, and a-IGZO thin-film transistors.

Seong-Ook Jung (M’00–SM’03) received the B.S.and M.S. degrees in electronic engineering fromYonsei University, Seoul, Korea, in 1987 and 1989,respectively, and the Ph.D. degree in electrical en-gineering from the University of Illinois at Urbana-Champaign, Urbana, in 2002.

From 1989 to 1998, he was with Samsung Elec-tronics Company, Ltd., Hwasung, Korea, where heworked on the specialty memories, such as videorandom access memory (RAM), graphic RAM, andwindow RAM, and merged memory logic. From

2001 to 2003, he was with T-RAM, Inc., Mountain View, CA, where he wasthe Leader of the Thyristor-Based Memory Circuit Design Team. From 2003to 2006, he was with Qualcomm, Inc., San Diego, CA, where he worked onhigh-performance low-power embedded memories, process variation-tolerantcircuit design, and low power circuit techniques. Since 2006, he has beenan Associate Professor with Yonsei University. His current research interestsinclude process variation-tolerant circuit design, low power circuit design,mixed-mode circuit design, and future generation memory and technology.

Dr. Jung is currently a Board Member of the IEEE Solid-State CircuitsSociety, Seoul Chapter.

Ilgu Yun (M’98–SM’03) received the B.S. degree inelectrical engineering from Yonsei University, Seoul,Korea, in 1990, and the M.S. and Ph.D. degrees inelectrical and computer engineering from GeorgiaInstitute of Technology, Atlanta, in 1995 and 1997,respectively.

From 1997 to 1999, he was a Research Fellowwith Microelectronics Research Center at the Geor-gia Institute of Technology. From 1999 to 2000,he was a Senior Research Staff Member with theElectronics and Telecommunications Research Insti-

tute, Daejeon, Korea. From 2006 to 2007, he was a Visiting Scholar withthe Department of Industrial and Manufacturing Engineering, University ofWisconsin-Milwaukee, Milwaukee. He is currently a Professor of electricaland electronic engineering, Yonsei University. He is also an Associate Deanof international affairs with the College of Engineering, Yonsei University.His current research interests include material characterization, statistical (andnonlinear) modeling and variations of semiconductor processes, devices, andintegrated circuit (IC) modules, and process modeling, control, and simulationapplied to computer-aided manufacturing of ICs.

Dr. Yun is an Educational Activity Chair of the IEEE Solid-State CircuitsSociety, Seoul Chapter. He is an Editor of Korean Electrical and ElectronicMaterial Engineers and Institute of Electronics Engineers in Korea.

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