TPS54331, TPS54332 PRODUCT PREVIEW REVISION MARCH 25, 2008

TI – Proprietary Information

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Copyright © 2008, Texas Instruments IncorporatedPRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

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28V INPUT, HIGH EFFICIENCY, 3-A OUTPUT, STEP DOWN SWIFTTM CONVERTER

FEATURES • 4.5V to 28V Input Voltage Range • Up to 3A Continuous Output Current • Output Voltage Adjustable Down to 0.8V with

+/- 2% Initial Accuracy • Current Mode Control with Internal Slope

Compensation • Integrated 90 mΩ High Side MOSFET • 1mA Operating Quiescent Current • Two Fixed Switching Frequency Versions:

- TPS54331: 600 kHz - TPS54332: 1.2 MHz

• Adjustable Slow Start / Sequencing • Programmable UVLO Threshold • Cycle by Cycle Current Limit, Thermal and

Frequency Fold Back Protection • Light Load Efficiency with Pulse Skip

Operation • -40°C to +125°C Junction Temperature Range • SOIC8 Package

APPLICATIONS • 12V & 24V Consumer Applications such as

Set-Top Boxes, CPE Equipment, LCD Displays, Peripherals, and Battery Chargers

• Industrial Power Systems

DESCRIPTION The TPS54331/2 device is a 28V, 3A, step down converter with an integrated high side MOSFET. Current mode control provides simple external compensation and flexible component selection. A pulse skip mode reduces the no load, regulated output supply current to 1mA. Using the enable pin, shutdown supply current is reduced to 5uA. Under voltage lockout is internally set at 2.8V, but can be increased using the accurate enable pin threshold. The output voltage startup ramp is controlled by the soft start pin that can also be configured for sequencing/tracking. Frequency fold back and thermal shutdown protects the part during an overload condition. The TPS54331/2 is available in an 8 pin SOIC package.

Simplified Schematic

8 pin SOIC Package

1

2

3

4 5

6

7

8BOOT

VIN

EN

SS/TR

PH

GND

COMP

VSENSE

PH

VIN

GND

BOOT

VSENSE

COMP

TPS54331/2

EN

SS/TR

CSS

C2

CBOOT

CI

CO

LO

D1 RO1

RO2

VIN

VOUT

C1

R3

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ORDERING INFORMATION

TJ PACKAGE SWITCHING FREQUENCY PART NUMBER

-40 °C to +125 °C 8 pin SOIC 600 kHz TPS54331D -40 °C to +125 °C 8 pin SOIC 1.2 MHz TPS54332D PACKAGE DISSIPATION RATINGS(1)(2)

PACKAGE

THERMAL IMPEDANCE

JUNCTION TO AMBIENT

TA = 25°C POWER RATING

TA=60°C POWER RATING

TA=85°C POWER RATING

SOIC 75 C/W TBD TBD TBD (1)Maximum power dissipation may be limited by overcurrent protection (2)Power rating at a specific ambient temperature TA should be determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or below 150°C for best performance and long-term reliability. See TBD in application section of this data sheet for more information. ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range unless otherwise noted(1)

UNIT Input Voltage VIN -0.3 to 30 V EN -0.3 to 5 V BOOT 38 V VSENSE -0.3 to 3 V COMP -0.3 to 3 V SS/TR -0.3 to 3 V Output Voltage BOOT-PH 8 V PH -0.6 to 30 V PH 10ns Transient -2 to 30 V Source Current EN 100 uA BOOT 100 mA VSENSE 10 uA PH 6 A Sink Current VIN 6 A COMP 100 uA SS/TR 200 uA Electrostatic Discharge (HBM) 2 kV Electrostatic Discharge (CDM) 500 V Operating Junction Temperature -40 to +125 ºC Storage Temperature -65 to +150 ºC

(1) Stresses beyond those listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “RECOMMENDED OPERATING CONDITIONS” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

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RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT Operating Input Voltage on (VIN pin) 4.5 28 V Operating junction temperature, TJ -40 125 C ELECTRICAL SPECIFICATIONS TJ = –40°C to +125°C, VIN = 4.5 to 28V (unless otherwise noted)

DESCRIPTION CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE (VIN PIN) Internal undervoltage lockout threshold Rising and Falling 2.8 V

Shutdown supply Current

EN = 0V, 25°C, 4.5 V≤VIN≤28V 5 uA

Operating– non switching supply Current

VSENSE=0.83V, VIN=12V, 25°C, fsw=600kHz or 1.2MHz

1 mA

ENABLE AND UVLO (EN PIN) Enable threshold Rising and Falling 1.2 V Input current Enable threshold – 50mV 1 uA Hysteresis current 3 uA VOLTAGE REFERENCE

4.5 V≤VIN≤28V, 25°C 0.784 0.8 0.816 V Voltage reference 4.5 V≤VIN≤28V,

0 <Tj < 70°C 0.776 0.8 0.824 V

HIGH-SIDE MOSFET 25°C, BOOT-PH=3.0V TBD mohm On resistance 25°C, BOOT-PH=6.0V 90 TBD mohm

ERROR AMPLIFIER Error amplifier transconductance (gm)

-2uA<ICOMP<2uA V(COMP)=1V 100 umhos

Error amplifier DC gain(1) VSENSE = 0.8V 800 V/V

Error amplifier unity gain bandwidth(1)

5pF capacitance from COMP to GND pins 2.7 MHz

Error amplifier source/sink current

V(COMP)=1.0V 100mV Overdrive +/- 7 uA

Switch current to COMP transconductance

11 A/V

SWITCHING FREQUENCY TPS54331 Switching Frequency TBD 600 TBD kHz

TPS54332 Switching Frequency TBD 1200 TBD kHz

Minimum controllable on time

Measured @ 90% to 90% of VIN 130 TBD ns

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DESCRIPTION CONDITIONS MIN TYP MAX UNIT Minimum controllable off time(1) BOOT-PH=6.0V 60 TBD ns

LIGHT LOAD EFFICIENT PULSE SKIP MODE Switch current threshold 180 mA

CURRENT LIMIT Current limit threshold 4 6.2 8.5 A THERMAL SHUTDOWN Thermal Shutdown 165 C SLOW START AND TRACKING (SS/TR PIN) Charge current V(SS/TR) = 0.4V 2 uA SS/TR to VSENSE matching V(SS/TR) = 0.4V 0 mV

SS/TR to reference Crossover 98% nominal 0.9 V

SS/TR discharge voltage VSENSE=0V 40 mV

Max external SS/TR Voltage 1.5 3 V

(1) Specified by design.

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PIN ASSIGNMENTS

1

2

3

4 5

6

7

8BOOT

VIN

EN

SS/TR

PH

GND

COMP

VSENSE

TERMINAL FUNCTIONS Pin Name Number TPS54331/2 Description

BOOT 1

A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the output device, the output is forced to switch off until the capacitor is refreshed.

VIN 2 Input supply voltage, 4.5 V to 28 V.

EN 3 Enable pin. Pull below 1.2V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors.

SS/TR 4

Slow-start and tracking. An external capacitor connected to this pin sets the output rise time. Since the voltage on this pin overrides the internal reference when it is smaller than the internal reference, SS/TR pin can be used for tracking and sequencing.

VSENSE 5 Inverting node of the gm error amplifier.

COMP 6 Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin.

GND 7 Ground PH 8 The source of the internal high side power MOSFET.

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FUNCTIONAL BLOCK DIAGRAM

Error Amplifier

R Q

S

Boot Charge

Boot UVLO

UVLO

Current Sense

OscillatorFrequencyShift

GateDriveLogic

Slope Compensation

PWMLatch

PWMComparator

Light Load EfficientPulse Skip

Maximum Clamp

VoltageReference

Discharge Logic

VSENSE

COMP

PH

BOOT

VIN

GND

Thermal Shutdown

EN

EnableComparator

ShutdownLogic

Shutdown

EnableThreshold

1uA 3uA

1.2V

0.6V

2.8V

0.8V

90 mohmgm=100umhos

DC gain=800V/VBW=2.7 MHz

165C

2.5V

11 A/V

SS/TR

Shutdown

2uA

VSENSE

2kohm

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Characterization Curves (3 x 3 on a page) On Resistance vs Junction Temperature (VIN=12V) Shutdown Quiescent Current vs Input Voltage (Junction Temperature = -40C, 25C, 125C) Switching Frequency vs Junction Temperature Voltage Reference vs Junction Temperature Minimum Controllable on Time vs Junction Temperature Minimum Controllable Duty Ratio vs Junction Temperature SS/TR Charge Current vs Temperature Current Limit vs Junction Temperature (VIN=12V) Supplemental Application Curves (3 x 3 on a page) Minimum Output Voltage vs Input Voltage (IOUT=3A, IOUT=TBDA)

Maximum Output Voltage vs Input Voltage (IOUT=3A, IOUT=TBDA)

Maximum Power Dissipation vs Junction Temperature

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Overview The TPS54331/2 is a 28V, 3A, step-down (buck) converter with an integrated high side n-channel MOSFET. To improve performance during line and load transients, the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design. The TPS54331 has a pre-set switching frequency of 600kHz and the TPS54332 has a pre-set switching frequency of 1.2MHz. The TPS54331/2 has a default start up input voltage of approximately 2.8V. The EN pin has an internal pull-up current source that can be used to adjust the input voltage under voltage lockout (UVLO) with two external resistors. In addition, the pull up current provides a default condition when the EN pin is floating for the device to operate. The operating current is 1 mA or less when not switching and under no load. When the device is disabled, the supply current is 5 uA. The integrated 90 mOhm high side MOSFET allows for high efficiency power supply designs with output currents up to 3A. The TPS54331/2 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high side MOSFET is supplied by an external capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the high side MOSFET off when the voltage falls below a preset threshold which is 2.5V typically. The output voltage can be stepped down to as low as the 0.8V reference. By adding an external capacitor, the slow start time of the TPS54331/2 can be adjustable which provides the favorable flexibility of the output filter selection. If multiple converters need to work together, the TPS54331/2 may be used for sequencing. To improve the efficiency at light load conditions, the TPS54331/2 enters a special pulse skip mode when the peak load current drops below 180mA typically. The frequency foldback reduces the switching frequency during startup and over current conditions to help control the inductor current. The thermal shut down gives the additional protection under fault conditions. Detailed Description Fixed Frequency PWM Control The TPS54331/2 uses a fixed frequency, peak current mode control. The internal switching frequency of the TPS54331 and TPS54332 is fixed at 600kHz and 1.2MHz respectively. Light Load Efficient Pulse Skip Mode The TPS54331/2 operates in a pulse skip mode at light load currents to improve efficiency. When the peak load current is lower than 180 mA typically the device

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will enter a sleep mode. Since the internal sleep mode comparator catches the peak load current only, the average load current entering the light load efficient sleep mode varies with the applications and external output filters. Voltage Reference (Vref) The voltage reference system produces a +/-2% initial accuracy voltage reference (+/- 3% over temperature) by scaling the output of a temperature stable bandgap circuit. Bootstrap Voltage (BOOT) The TPS54331/2 has an integrated boot regulator and requires a 0.1uF ceramic capacitor between the BOOT and PH pin to provide the gate drive voltage for the high side MOSFET. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the stable characteristics over temperature and voltage. To improve drop out, the TPS54331/2 is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is greater than 2.5V typically. Enable and Adjustable Input Under-Voltage Lock Out (VIN UVLO) The EN pin has an internal pull-up current source that provides the default condition of the TPS54331/2 operating when the EN pin floats. The TPS54331/2 is disabled when the VIN pin voltage falls below 2.8 V typically. But it is not recommended to use the internal VIN UVLO because there is no hysterisis. To adjust the VIN UVLO with hysterisis, use the external circuitry connected to the EN pin as shown in Figure 1. Once the EN pin voltage exceeds 1.2V, an additional 3uA of hysteresis is added. Use Equation 1 to set the UVLO hysteresis for the input voltage. Use Equation 2 to set the input start threshold voltage.

Figure 1 Adjustable Input Under Voltage Lock Out

uASTOPVSTARTVn

31Re −= Equation 1

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uAR

ENAVSTARTVENAV

n1

1

2Re+

−= Equation 2

Programmable Slow Start Using SS/TR It is highly recommended to program the slow start time externally because no slow start time is implemented internally. The TPS54331/2 effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the power supply’s reference voltage fed into the error amplifier and will regulate the output accordingly. A capacitor (Css) on the SS/TR pin to ground will implement a slow start time. The TPS54331/2 has an internal pull-up current source of 2uA which will charge the external slow start capacitor. The equation for the slow start time (10 to 90%) is shown in Equation 3. The Vref is 0.8V and the Iss current is 2uA. The slow start capacitor should be no more than 0.1uF.

)()()()(

uAIssVVrefnFCssmsTss •

= Equation 3

If during normal operation, the VIN UVLO is not exceeded, or the EN pin pulled below 1.2V, or a thermal shutdown event occurs, the TPS54331/2 will stop switching and the SS/TR must be discharged to 0V before reinitiating a powering up sequence. Error Amplifier The TPS54331/2 has a transconductance amplifier for the error amplifier. The error amplifier compares the VSENSE voltage to the internal effective voltage reference presented at the input of the error amplifier. The transconductance of the error amplifier is 100 uA/V during normal operation. The frequency compensation components should be added to the COMP pin to ground. Slope Compensation In order to prevent the sub-harmonic oscillations when operating the device at duty cycles greater than 50%, the TPS54331/2 adds a built-in slope compensation which is a compensating ramp to the switch current signal.

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Current Mode Compensation Design To simplify design efforts using the TPS54331/2, the typical designs for common applications are listed below in Table 1. Advanced users may refer to the “Step by Step Design Procedure” in the Application Information section for the detailed guidelines. Table 1: Typical Designs (Referring to Simplified Schematic on page 1) Vin (V)

Vout (V)

Fsw (kHz)

Lo (uF)

Co (uF)

RO1 (kOhm)

RO2 (kOhm)

C2 (pF)

C1 (nF)

R3 (kOhm)

12 5 600 12 3.3 600 12 1.8 600 12 0.9 600 12 5 1200 12 3.3 1200 12 1.8 1200 12 0.9 1200

Overcurrent Protection and Frequency Shift The TPS54331/2 implements current mode control which uses the COMP pin voltage to turn off the high side MOSFET on a cycle by cycle basis. Each cycle the switch current and the COMP pin voltage are compared, when the peak switch current intersects the COMP voltage the high side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier will respond by driving the COMP pin high, increasing the switch current. The COMP pin has a maximum clamp internally. This clamp functions as a switch current limit. The TPS54331/2 provides robust protection during short circuits. In general, short circuits present a potential problem for high input voltage applications where the loop has a finite minimum controllable on time and the output has a very low voltage. During the switch on time, the inductor current ramps quickly to the peak current limit because of the high input voltage and minimum on time. During the switch off time, the inductor current does not have enough off time or output voltage for the inductor to ramp down by the ramp up amount. This scenario can result in an overcurrent runaway condition. The TPS54331/2 solves the issue by increasing the off time during conditions that lower the VSENSE pin voltage. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8V on VSENSE pin.

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Overvoltage Transient Protection The TPS54331/2 incorporates an overvoltage transient protection (OVTP) circuit to minimize output voltage overshoot when recovering from output fault conditions or strong unload transients. The OVTP circuit includes an overvoltage comparator to compare the VSENSE pin voltage and internal thresholds. When the VSENSE pin voltage goes above 109% x Vref, the high-side MOSFET will be forced off. When the VSENSE pin voltage falls below 107% x Vref, the high-side MOSFET will be enabled again. Thermal Shutdown The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 165oC. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature decreases below 165oC, the device reinitiates the power up sequence. Sequencing Using EN and SS/TR Many of the common power supply sequencing methods can be implemented using the SS/TR, EN. Refer to Figure 2 to Figure 3 for examples of sequencing.

Figure 2 Ratiometric Start Up Sequence

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Figure 2 shows a method for ratiometric start up sequence by connecting the SS/TR pins together. The outputs of the converters will ramp up at the same rate. The pull up current source will be doubled. Ratiometric and simultaneous power supply sequencing can be implemented by connecting the resistor network of Rss1 and Rss2 shown in Figure 3 to the output of the power supply that needs to be tracked. Using Equation 4 and Equation 5, the tracking resistors can be calculated to power the Vout2 slightly before, after or same time as Vout1. Equation 5 is the voltage difference between Vout1 and Vout2 at the moment Vout2 reaches regulation. The deltaV variable is zero volts for simultaneous sequencing and the tracking resistors will have the same ratio at the Vout2 voltage adjust resistors.

Figure 3 Ratiometric and Simultaneous Startup Sequence

⎟⎟⎠

⎞⎜⎜⎝

⎛−+

•=VdeltaVVout

VRssRss

8.028.0

12 Equation 4

21 VoutVoutdeltaV −= Equation 5 To design a ratiometric start up in which the Vout2 voltage is slightly greater than the Vout1 voltage when final regulation for Vout2 is achieved, use a negative number in Equation 4 for deltaV. Equation 5 will result in a positive number for

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applications which the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved. Careful selection of the tracking resistors is needed to minimize the tracking offset and to ensure the overload recovery circuit will function properly during fault conditions. The tracking resistor Rss1 needs to be greater than the value determine in Equation 6 for the OLR circuit to function. The offset causes the Vout2 to regulate to a slightly higher voltage than a system without the pull-up current source. The tracking resistor value of Rss2 can be lowered to decrease the difference between Vout1 and Vout2. To determine the actual output voltage when Vout2 reaches final regulation, sum the offset result in Equation 7 with SS/TR pin voltage and divide the voltage adjust resistor ratio.

AVoutRss

μ8.23611> Equation 6

⎟⎠

⎞⎜⎝

⎛+•

•=21212

RssRssRssRssuAOffset Equation 7

Application Information Step by Step Design Procedure TBD Power Dissipation Estimate TBD EMI Considerations TBD

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