Extending Etch and Deposition Capabilities for Implementation of 3D Packaging of MEMS in Volume Production David Butler, VP Product Management & Marketing

SPTS Technologies

•Industry Trends

•TSV Process Flow

•Etch –TSV Etch Evolution

–Endpoint Detection

–Oxide Etching

•Dielectric CVD –Via Last Challenges

–Managing Outgassing

•Metallization –Conventional & Ionized PVD

–LT MOCVD Extendibility

•Conclusions

Contents

•Never a down year in MEMS –But module growth more modest: shrinks

MEMS Market Trends

•Most high volume MEMS production now on 200mm

–ST, Bosch, TSMC, UMC, TowerJazz …

•In transition

–Silex, X-FAB …

•Still on 150mm

–Tronics, IMT, Micralyne, Sony …

•100mm limited mostly to R&D

More Die Per Wafer

100mm

150mm

200mm

2 x 2mm die with 0.1mm separation

MEMS – Drive for Miniaturization

iPhone 3G 3GS

4 4S 5 5S 6

0

2

4

6

8

10

12

14

iPho

ne T

hick

ness

(m

m)

Thinner handsets with MORE functionality: gyros, accelerometers, microphones, cameras and “combo” chips

Accelerometers size dropped from 12 to <1.5mm2 over 7 years

Even Smaller - TSV

MEMS timing device TSVs between ASIC & MEMS

With TSV >30% reduction in X and Y

>80% reduction in resistance

CP Hung SEMI TSV

Summit 2015

Typical Process Flow for Via Last TSV

•Required Via shape depends on subsequent deposition technology

TSV Etching Evolution

Top ~85µm Base ~47µm Profile ~77°

Top ~89µm Base ~49µm Profile ~63°

50 x 130µm Sc ~500nm

Profile ≤92°

10 x 100µm Sc ~100nm Profile 90°

75 x 150µm Sc ~200nm

Profile ≤91°

10 x 100µm Sc ~70nm

Profile 90°

8 x 180µm Sc <200nm

4 x 160µm Sc <50nm

Continuous process SF6 + passivant

Switched (Bosch) process SF6/C4F8 cycling

Apparent wall curvature due

to cleave

End-point Detection Tapered Etches (Reflectance) Vertical etches (Claritas)

Si

Si

Variation due to differing grind

thicknesses of Si

EPD = Better reproducibility & higher yield

•Base layer etching within TSV

Oxide Etching for TSV

Oxide multi-layer

~9µm

Si TSV ~400 x 400µm

PR

Oxide remaining 1-2µm

Si

Oxide 6.3µm partial etch Apparent wall curvature due

to cleave

Oxide etch

•Spacer etch of TSV liner

Oxide Etching for TSV

20 x 120µm TSV

Oxide etched

Oxide removed at Via base

Denotes oxide layer

OES end-point detection

70 x 70µm TSV

LT PECVD Challenges

•PECVD System –Temperature control – wafer and chamber

–Substrate compatibility – SOS, SOG

–Outgassing substrates – the need for degas

•Film Engineering –Electrical isolation – IL & Vbd

–Stability – esp. LT TEOS SiO

–Sidewall coverage – void-free

–Stress tuning & stability

–Diffusion barrier properties

•Integration –Interfacial adhesion – to Si, SiO and inter-stack layer

–CMP compatibility – E & H

–Bow compensation

Challenging to achieve all this with wafer

temperature <190 °C

•Choice of chemistries for TSV liner –Silane for sloped TSV and vertical TSV with AR < 2:1

–TEOS for vertical TSV with AR > 2:1

•Ammonia-free SiN diffusion barrier –Prevent Cu diffusion into Si

Delta fxP LT PECVD

Stable Leakage Current Stable Stress

PECVD SiO in Sloped Sidewall TSV

Top Corner

Base

■ Silane-based SiO at 150°C

■ Excellent adhesion

■ Excellent electrical properties

■ No delamination after wafer dicing

■ Volume production since 2008 ■ 300mm SoG CIS

IMAPS 2010

Linear Ramp Voltage Stress

•SiN, SiO & TEOS SiO with common chamber hardware –SiN barriers

–SiO isolation

•All films ≤200°C

•Aspect ratios ≤ 10:1

TEOS SiO in Vertical TSV

Extensive LT SiN and SiO Production Experience

TEOS SiO liner in

40µm x 125µm TSV

LT TEOS SiO in

10x80 µm TSV

•Minimize out-gassing to preserve PECVD film quality

•Batch process chamber –Long degas times with high system throughput

Managing Out-Gassing in PECVD

Without Degas Step

dc b

ias

(V)

With Degas Step

dc b

ias

(V)

Unstable Plasma

Scrap Wafer!

Conventional PVD Al for Low AR TSV

Tapered Etch Trench Thinned Si bonded to Taped Glass 4 µm Al [4%Cu] Deposition

Wafer Centre

Thickness, μm Step Cov. % Field 4.15 100

50 % depth 3 72 75 % depth 2.74 66

Bottom corner 2.6 63 Base 3.22 78

Ionized PVD Cu Seed for HAR

50 µm x 250 µm, AR 5 Integrated SPTS process flow Rapier DRIE Delta SiN DCVD Sigma Ti barrier Sigma Cu seed

10 µm x 100 µm AR 10

20 µm x 300 µm AR 15

Extendibility – LT MOCVD TiN

3 µm x 15 µm TSV Barrier: 75 nm C3M MOCVD TiN, 200°C Minimum sidewall coverage 46%

Low temp MOCVD TiN

FEOL MOCVD TiN

•Low cost R&D solution –Multiple processes on one platform

•Example configuration –Rapier for Si & SiO etch

–1x APM PECVD oxide & nitride

–1x AHF ionized PVD barrier

–1x AHF ionized PVD Cu

•System capability –Etch deep Si via by Bosch process

–Etch oxide hard-mask and liner

–PECVD of low temperature oxide

–Ionized PVD of barrier & Cu seed

–Via reveal Si and dielectric etches

Versalis fxP: Reduced Cost R&D

Rapier Si/SiO etch

PVD Ti

APM PECVD SiO/SiN

Versalis reduces capex and footprint

PVD Cu

Degas

Sputter Etch

•Via-last TSV for low I/O is ramping

–Image sensors, MEMS, RFIC, PMIC

•DRIE Si and SiO etch

–TSV etch and base oxide liner removal

•Low temperature PECVD SiO liners

–Silane and TEOS based

–Tapered TSV to high aspect ratio

•Range of metallization options

–PVD – ionized PVD – low temp MOCVD

•Versalis fxP multi-tech cluster system

–Reduced initial capital costs

Summary

THANK YOU

QUESTIONS?