16 sept. 2005 G.-F. Dalla BettaSCIPP Maurizio Boscardin a, Claudio Piemonte a, Alberto Pozza a,...

G.-F. Dalla Betta SCIPP 16 sept. 2005

Maurizio Boscardina, Claudio Piemontea, Alberto Pozzaa, Sabina Ronchina,

Nicola Zorzia, Gian-Franco Dalla Bettab

a ITC-irst, Microsystems Division, via Sommarive, 18 38050 Povo di Trento, Italy b DIT, University of Trento, Via Sommarive, 14, 38050 Povo di Trento, Italy

Development of 3D detectors

at ITC-irst


Introduction Single-Type Column 3D detectors Simulation results Technological tests Fabrication of the first batch Preliminary electrical results Conclusion

Outline


IntroductionIntroduction

ITC-irst is developing the process for the fabrication of 3D sensors.

Framework:• RD50 collaboration - for the development of radiation tolerant detectors• INFN-PAT agreement

We have started with a simplified process, since all necessary clean-room equipment is not available yet


““Standard” 3D detectorsStandard” 3D detectors - concept - conceptFirst 3D architecture, proposed by S.I. Parker et al. [1] in 1997: columnar electrodes of both doping types

n-columns p-columns

wafer surface

ionizing particle

Short distance between electrodes:• low full depletion voltage• short collection distance more radiation tolerant than planar detectors!!n-type substrate

[1] S.I. Parker et al., Nucl. Instr. Meth. Phys. Res. A 395 (1997) 328

DRAWBACK: Fabrication process rather long and not standard, so mass production of 3D devices very critical and very expensive.


““Standard” 3D detectorsStandard” 3D detectors - fabrication - fabrication

Kenney et al. IEEE TNS, vol. 46, n. 4 (1999)

1) wafer bonding

support wafer

detector wafer

2) n+ hole definition and etching

resist

oxide

3) hole doping and filling

n+ polysilicon

4) p+ hole definition and etching

resist

5) hole doping and filling

p+ polysilicon

6) Metal deposition and definition

metal


Single-Type-Column 3D detectorsSingle-Type-Column 3D detectors - concept- concept

Sketch of the detector:

grid-like bulk contact

ionizing particle

cross-sectionbetween twoelectrodes

n+ n+

electrons are swept away by the transversalfield

holes drift in the central region and diffuse towards p+contact

n-columns

p-type substrate

Etching and column doping performed only once

Functioning:


3DSTC detectors3DSTC detectors - concept (2) - concept (2)

Further simplification: not passing-through holes

p-type substraten+ electrodes

Uniform p+ layer

Bulk contact is provided by a Backside uniform p+ implant single side process.

No need of support wafer.


TCAD Simulations - static (1)TCAD Simulations - static (1)

3D simulations are necessary DEVICE3D tool by Silvaco

Important to exploit the structuresymmetries to minimize the regionto be simulated

n+

cell50m

• p-type substrate

• Wafer thickness: 300m

• Holes: 5m-radius

250m-deep



Potential distribution(vertical cross-section)

0V

-10V

-5V

50m

300

m

Potential distribution(horizontal cross-section)

null field regions

-15V



Potential and Electric field along a cut-line from the electrode to the center of the cell

To increase the electric field strength one can act on the substrate doping concentration

Na=1e12 1/cm3

Na=5e12 1/cm3

Na=1e13 1/cm3

Na=1e12 1/cm3

Na=5e12 1/cm3

Na=1e13 1/cm3


TCAD Simulations - dynamic (1)TCAD Simulations - dynamic (1)

Current signal in response to an ionizing particle.

Vertical tracks in 3 different positions Electron cloud evolution (b)

1 2

3 4

n+ n+

n+ n+

a b c


TCAD Simulations - dynamic (2)TCAD Simulations - dynamic (2)

Case b.

Case c.

Nsub=1e12 cm-3

Nsub=5e12 cm-3

Nsub=1e13 cm-3

Nsub=1e12 cm-3

Nsub=5e12 cm-3

Nsub=1e13 cm-3

1ns

10ns

Cur

rent

(A

)C

urre

nt (

A)

In the worst casethe induced currentpeak is within 10ns

For a hit 5m from theelectrode the peak is within 1ns.


TCAD Simulations TCAD Simulations – – critical points evidencedcritical points evidenced

• Long low tail in the current signal due to hole diffusion. Simulation have shown that this effect can be strongly minimized using passing-through electrodes.

• High electric field at the bottom of the hole. Anyway we should not reach critical values because of the low bias voltages needed.

• In case of p-spray isolation, high electric field at the column/p-spray junction. Again, may be of concern depending on the bias voltage needed.


Technological tests - lithographyTechnological tests - lithography

as-deposited: Photoresist tends to penetrate inside the hole forming a thicker layer in these region

after exposure and development: residual photoresist in the hole region

Important to note that resist can be defined in the proximity of the hole.

The resist trapped in the hole is removed after the process


Technological tests - depositionTechnological tests - deposition

Surface

Top botton

Poly 1m 0.8m 0.7m

TEOS 1m 0.7m 0.6m

Poly and oxide deposition

top

bottom

hole

holesurface

oxide

poly

poly

oxide


Technological tests – oxide growthTechnological tests – oxide growth

Oxide Growth (500nm) in a 5m diameter hole

metal

oxide

oxide

hole

top bottom


hole

Aluminum does not penetrate inside the hole

contacts have to be made on the wafer surface

aluminum

Technological tests – metal sputteringTechnological tests – metal sputtering


initial oxide p+-doping of back Isolation: p-stop or p-spray masking for deep- RIE process

deep-RIE(CNM, Barcelona-Spain)

Fabrication process (1)

oxidep-stop

p+ doping

holes


P-diffusion

(no hole filling)

Oxidation (hole passivation) Opening contacts Metal and sintering

Fabrication process (2)

P- diffused regions

Hole passivation

contacts

metal


Mask layoutMask layout

Small version of strip detectors

Planar and 3D test structures

“Low density layout”to increase mechanicalrobustness of the wafer

“Large” strip-like detectors


Mask Layout-Test structures

3D-Diode

Pitch 80 µm

10x10 matrixØ hole 10

µm44 holes GR

Standard (planar) test structures


Mask layout - strip detectors layout - strip detectors

metal

p-stop

hole

Contact opening n+

•AC and DC coupling•Inter-columns pitch 80-100 m•Two different p-stop layouts•Holes Ø 6 or 10 m

Inner guard ring (bias line)


Fabrication run:main characteristics

Substrate: Si High Resistivity, p-type, <100> FZ (500 m) >5.0 kcm

Cz (300m) >1.8 kcm

Wafers with lower resistivity are not easy to find

Surface isolation: p-stop p-spray


SEM micrographs

Portion of a strip detector

Top-side of a column

strip

Column-section

100 m

6 m

metal

oxide


Electrical Characterization (1)

Parameter Unitp-spray p-stop

Nd [1E12 cm-3]Vdep [V]Ileak [nA/cm2]Vbreak [V] 60 - 140 155 - 175Tox [nm] 570 - 585 860 - 875Nox [1E10 cm-2] 9.5 - 11 6 - 9.6So [cm/s] 1.3 - 1.7 7 - 7.5

typical range

1 - 3.5200 - 500

1 - 20

Different sub-typesand thicknesses

2% to 13% variationon single wafer

Ileak measured below full depletiondue to breakdown

Standard (planar) test structures

electrical parameters compatible with standard planar processes

DRIE does not endanger device performances


1.0E-12

1.0E-11

1.0E-10

1.0E-09

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04

0 20 40 60 80 100Vbias [V]

I lea

k [A

]

1.0E-12

1.0E-11

1.0E-10

1.0E-09

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04

0 20 40 60 80 100

Vbias [V]

I lea

k [A

]

Electrical Characterization (2)IV measurements

3D-Diode

P-stop

P-stop

P-sprayP-spray

Ileak/column @ 20V 0.67 ±0.12 pA

Ileak/column @ 20V 0.33 ±0.24 pA

CZ FZ

diode

─ guard ring

10x10 matrixØ hole 10 µmPitch 80 µm

Active area ~0.64 mm2

diode

─ guard ring


0

5

10

15

20

25

30

0 5 10 15 20 25 30 35 40 45 50 >50

I bias line [nA]

Det

ecto

rs c

ou

nt

Electrical Characterization (3)Strip detectors

Current distribution @ 40V of 70 different devices

1detector:230 columns x 64

strips on 1 cm2

~ 15000 columns

average current per column < 1pA

Good process yield

FZ

1.0E-10

1.0E-09

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04

0 50 100 150 200 250

p-spray

p-stop

I BL I GR

Reverse Voltage [V]

Lea

kag

e C

urr

ent

[A]

1.0E-10

1.0E-09

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04

0 50 100 150 200 250

p-spray

p-stop

I BL I GR

Reverse Voltage [V]

Lea

kag

e C

urr

ent

[A]


Conclusions

A new type of 3D detector has been conceived whichleads to a significant simplification of the process: hole etching performed only once no hole filling no wafer bonding

First production is completed: Good electrical parameters (DRIE does not endanger device performance) Low leakage currents < 1pA/column and BD ~ 50V for p-spray and >100V for p-stop in 3D diodes Good yield for strip detectors (Current/hole < 1pA/column for 93% of detectors)

Accurate analysis of CV measurement results is in progress with the aid of TCAD simulations …

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0 2 4 6 8 10|Vback| [V]

Cin

t [p

F]

Lateral depletion-voltageLateral depletion-voltagePreliminary “3d-diode”/GR capacitance measurements

Cint-Vback

Weak capacitive coupling at very low voltages (conductive substrate layer between columns)

~ 5V lateral full depletion voltage (100µm pitch)

Vback

Capacitive coupling between 40 columns (100um=pitch, 150um depth)

Cint

Backplane full-depletion-voltageBackplane full-depletion-voltage

Preliminary “3d-diode”/back capacitance measurements

0

2

4

6

8

10

12

0 10 20 30 40 50 60Vrev [V]

Cd

iod

e [p

F]

D4_4

0.00

0.50

1.00

1.50

2.00

2.50

0 10 20 30 40 50 60Vrev [V]

C-2

[p

F-2

]

C-V

1/C2-V

Lateral depletion contribution to measured capacitance at low voltages

Linear 1/C2 vs V region corresponding to the same doping level of planar diodes

Saturation capacitance corresponding to a depleted width of ~ 150µm) Column depth ~ 150µm

~ 40V full depletion voltage (300µm wafer)

16 sept. 2005 G.-F. Dalla BettaSCIPP Maurizio Boscardin a, Claudio Piemonte a, Alberto Pozza a,...

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