12. Dynamic CMOS Logic
Transcript of 12. Dynamic CMOS Logic
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12. Dynamic CMOS Logic
Jacob Abraham
Department of Electrical and Computer EngineeringThe University of Texas at Austin
VLSI DesignFall 2020
October 8, 2020
ECE Department, University of Texas at Austin Lecture 12. Dynamic CMOS Logic Jacob Abraham, October 8, 2020 1 / 25
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Review: Fixing Hold-Time Violations
Measure all hold times with respect to the main clock
Adjust the hold time if the flop is receiving a delayed clock
Compute the shortest path delay from the rising edge of theclock
Check to see if there are any hold time failures
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Example: Fixing Hold-Time Violations
Shortest path delay from A → E = 100 + 40 + 40 + 20 = 200 psDelay between CLK1 and CLK = 50 psAdjusted hold time = 200 + 50 = 250 psHold Slack = (Path Delay) − (Adjusted Hold Time) = 200 − 250
= −50 ps=⇒ FAIL (Hold slack should be ≥ 0)
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Example: Fixing Hold-Time Violations, Cont’d
Insert 4 inverters after D, with each adding a 20 ps(or can insert one AND gate)
Long path (4 invs.) = 100 + 50 + 50 + 20 + 80 + 10 = 310 psNow the minimum cycle time at which the path can operate =(Path Delay) − (CLK → CLK1 Delay) = 310 − 50 = 260 ps
If possible, add the additional delay to fix hold time violations inthe short path (without affecting the long paths)
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Dynamic Logic
Dynamic gates use a clocked pMOS pullup
Two modes of operation: precharge and evaluate
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The “Foot” Transistor
What if pulldown network is ON during precharge?
Use series evaluation transistor to prevent fight betweenpMOS and nMOS transistors
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Logical Effort
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Monotonicity
Dynamic gates require monotonicallyrising inputs during evaluation
0→ 00→ 11→ 1But not 1→ 0
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Monotonicity Woes
But dynamic gates produce monotonically falling outputsduring evaluation
Illegal for one dynamic gate to drive another!
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Domino Gates
Follow dynamic stage with inverting static gate
Dynamic/static pair is called domino gateProduces monotonic outputs
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Domino Optimizations
Each domino gate triggers next one, like a string of dominostoppling overGates evaluate sequentially, precharge in parallelEvaluation is more critical than prechargeHI-skewed static stages can perform logic
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Dual-Rail Domino
Domino only performs noninverting functions:
AND, OR but not NAND, NOR, or XOR
Dual-rail domino solves this problem
Takes true and complementary inputsProduces true and complementary outputs
sig h sig l Meaning
0 0 Precharged
0 1 ‘0’
1 0 ‘1’
1 1 Invalid
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Example: AND/NAND
Given A h, A l, B h, B l
Compute Y h = A * B, Y l = ∼(A * B)
Pulldown networks are conduction complements
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Example: XOR/XNOR
Sometimes possible to share transistors
Sharing works well in implementations of symmetric functionsSee papers on “relay logic” published over 50 years ago
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Leakage
Dynamic node floats high during evaluationTransistors are leaky (Ioff 6= 0)Dynamic value will leak away over timeFormerly milliseconds, now nanoseconds!
Use keeper to hold dynamic nodeMust be weak enough not to fight evaluation
Leakage Power!
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Charge Sharing
Dynamic gates suffer from charge sharing
Vx = Vy =Cy
Cx + CyVDD
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Secondary Precharge
Solution: add secondary precharge transistors
Typically need to precharge every other node
Big load capacitance on Y helps as well
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Noise Sensitivity
Dynamic gates are very sensitive to noiseInputs: VIH ≈ Vtn
Outputs: floating output susceptible noiseNoise sources
Capacitive crosstalkCharge sharingPower supply noiseFeedthrough noiseAnd more!
Chip power supply voltage map
when executing a program
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Alternating N & P Domino Logic
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Cascade Voltage Switch Logic (CVSL)
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Dynamic CVSL XOR Gate
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Dual-Rail Domino Full Adder Design
Very fast, but large and power hungry
Used in very fast multipliers
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Domino Summary
Domino logic is attractive for high-speed circuits
1.5 2x faster than static CMOS
Many Challenges
MonotonicityLeakageCharge sharingNoise
Used in previous generation high-performance microprocessorsand in some recent embedded processors
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Domino Logic in Current Designs
Domino design from Intrinsity used in 1-GHz 0.75W ARMCortex A8 from Samsung (Intrinsity later acquired by Apple)Fast Domino (called “Fast14 NDL”) gates are insertedselectively into critical speed paths, with custom SRAMs andoptimized synthesized logic elsewhereStandard power saving techniques are also usedDomino gates are clocked by multiphase clocksA type of “super-pipeline” where the domino footers form thebarrier for the pipeline operation
(Source: Electronic Design – Embedded, August 29, 2009)
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Intrinsity OR/NOR Implementation with “N-nary Logic”
2-bit function using 1-out-of-4 signals
Ref: U. S. Patent 6066965, Method and apparatus for a N-naryLogic Circuit Using 1 of 4 Signals
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Intrinsity XOR/Equivalence Implementation
Using 1-out-of-2 signals
Ref: U. S. Patent 6066965, Method and apparatus for a N-naryLogic Circuit Using 1 of 4 Signals
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