11/10/2004 EE 42 fall 2004 lecture 30 1

Lecture #30 Finite State Machines

• Last lecture: – CMOS fabrication– Clocked and latched circuits

• This lecture:– Finite State Machines

11/10/2004 EE 42 fall 2004 lecture 30 2

Finite State Machines

• The digital model we are looking at is an implementation of a finite state machine.

• A FSM has several states, corresponding to the values of each of the registers. Inputs into the machine are combined with the current state of the machine to determine the next state of the machine.

• Most complex digital systems are made from one or more finite state machines, because they can be more easily analyzed than asynchronous digital logic

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Block diagram

This is a block diagram of a particular kind of FSM. (a Mealy machine with delayed outputs)

Inputs (N) outputs

Clock

Current state of the system: Q(M)

Clock

Combinatorial

Logic

Register

(N+M edge

triggered

flip-flops)

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Timing diagram for synchronous FSM

Clock

Inputs

State

Output

Logic

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A computer as a FSM

• A computer could be viewed as a FSM,• or you could view just the CPU as a FSM,

accesses from the main memory as outputting addresses, followed by input of data from the memory, etc.

• A CPU might also be viewed as several interacting FSMs.– An accumulator– A memory interface unit– An instruction sequencer

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State Transition tables

It is implicit that transitions occur only at discrete times (such as clock edges)

State Input Next state Output

(received 6 bits so far)

Next bit Received 7 bits so far

none

(received 7 bits so far)

Next bit Have received byte

The byte received

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Defining State Machines

Example: Suppose I am playing a game by tossing a coin.If I toss 3 heads in a row, I win.If I toss a tail before tossing three heads, I lose.

States = {0_heads, 1_head, 2_heads}

Inputs = {head, tail, absent}

Outputs = {win, lose, absent}

initialState = 0_heads

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Defining State Machines: TableThis state machine can be defined using a table:

(s(n+1), y(n)) = update(s(n), x(n))

x(n) = head x(n) = tail

s(n) = 0_heads

s(n) = 1_head

s(n) = 2_heads

Output absent means that there is no output at this transitionThere is a more visually appealing way to define theupdate function: a state diagram.

(1_head, absent) (0_heads, lose)(2_heads, absent)(0_heads, lose)

(0_heads, win) (0_heads, lose)

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Defining State Machines: State DiagramTo create a state diagram for a state machine, first draw circles representing the states.

0_heads 1_head 2_heads

For each combination of input and state, draw an arrow from the current state to the next state.Label the arrow with the input and output that create the transition as shown: “input/output”

head / absent head / absent

tail / lose

tail / lose

tail / lose head / win

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State Machines: State ResponseThe state response is sequence of states resulting from a particular input sequence.

Example: Find the state response and output sequence for

x =

0_heads 1_head 2_heads

head / absent head / absent

tail / lose

tail / lose

tail / lose head / win

tail head head tail

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Facts About State Machines• The state machines addressed here are called Mealy

machines. Mealy machines generate outputs during state transitions.

• Moore machines generate output while the system is in a particular state (output depends on state only).

• Each transition and output depends only on the current state and current input.

• Previous input elements only affect the transitions and output insofar as they determine the current state.

• A transition will be defined for every possible combination of input and current state.

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Deterministic vs Nondeterministic

• For the state machines studied in this lecture, there is exactly one possible transition for each combination of current state and input. These state machines are called deterministic.

• Sometimes it is useful to model a system using a state machine that has more than one possible transition for each combination of current state and input. These state machines are called non-deterministic.

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FSMs in programs

• The finite state machine model can be useful in the design of software as well as the design of hardware.

• If a program is responding to external events, which are not happening in a controlled order, a FSM description of the program can describe its high level operation better than sequential descriptions.

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Implementing Sequential Logic

• Sequential Circuits– Simple circuits with feedback– Latches– Edge-triggered flip-flops

• Timing Methodologies– Cascading flip-flops for proper operation– Clock skew

• Asynchronous Inputs– Metastability and synchronization

• Basic Registers– Shift registers

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Sequential Circuits

• Circuits with Feedback– Outputs = f(inputs, past inputs, past outputs)

– Basis for building "memory" into logic circuits• State is memory• State is an "output" and an "input" to combinational logic• Combination storage elements are also memory

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X1X2•••

Xn

switchingnetwork

Z1Z2•••

Zn

Circuits with Feedback

Need to stop values from cycling around endlessly

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R

S

Q

Q'

R

S

Q

R'

S'Q

Q

Q'

S'

R'

Memory with Cross-coupled Gates

• Cross-coupled NOR gates– Similar to inverter pair, with capability to force output to 0 (reset=1) or

1 (set=1)

• Cross-coupled NAND gates– Similar to inverter pair, with capability to force output to 0 (reset=0) or

1 (set=0)

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Reset Hold Set SetReset Race

R

S

Q

\Q

100

Timing Behavior

R

S

Q

Q'

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Q(t+)

R

S

Q(t)

S R Q(t) Q(t+)0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 X1 1 1 X

hold

reset

set

not allowed characteristic equationQ(t+) = S + R’ Q(t)

R-S Latch Analysis

• Break feedback pathR

S

Q

Q'

0 0

1 0

X 1

X 1Q(t)

R

S

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enable'

S'Q'

QR' R

S

Gated R-S Latch

• Control when R and S inputs matter– Otherwise, the

slightest glitch on R or S while enable is low could cause change in value stored

Set Reset

S'

R'

enable'

Q

Q'

100

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period

duty cycle (in this case, 50%)

Clocks

• Used to keep time– Wait long enough for inputs (R' and S') to settle– Then allow to have effect on value stored

• Clocks are regular periodic signals– Period (time between ticks)– Duty-cycle (time clock is high between ticks - expressed as % of

period)

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clock

R' and S'

changing stable changing stablestable

Clocks (cont’d)

• Controlling an R-S latch with a clock– Can't let R and S change while clock is active (allowing R and S

to pass)– Only have half of clock period for signal changes to propagate– Signals must be stable for the other half of clock period

clock'

S'Q'

QR' R

S

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clock

R

S Q

Q' R

S Q

Q'R

S

Cascading Latches

• Connect output of one latch to input of another• How to stop changes from racing through chain?

– Need to control flow of data from one latch to the next– Advance from one latch per clock period– Worry about logic between latches (arrows) that is too

fast

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Master-Slave Structure

• Break flow by alternating clocks (like an air-lock)– Use positive clock to latch inputs into one R-S latch– Use negative clock to change outputs with another R-S latch

• View pair as one basic unit– master-slave flip-flop– twice as much logic– output changes a few gate delays after the falling edge of clock

but does not affect any cascaded flip-flopsmaster stage slave stage

P

P'

CLK

R

S Q

Q' R

S Q

Q'R

S

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Set1s

catch

SR

CLKPP'QQ'

Reset

MasterOutputs

SlaveOutputs

The Catching Problem

• In first R-S stage of master-slave FF– 0-1-0 glitch on R or S while clock is high "caught" by master

stage– Leads to constraints on logic to be hazard-free

master stage slave stage

P

P'

CLK

R

S Q

Q' R

S Q

Q'R

S

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D Flip-Flop

• Make S and R complements of each other– Eliminates catching problem– Can't just hold previous value (must have new value ready every

clock period)– Value of D just before clock goes low is what is stored in flip-flop– Can make R-S flip-flop by adding logic to make D = S + R' Q

D Q

Q'

master stage slave stage

P

P'

CLK

R

S Q

Q' R

S Q

Q'

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Q

D

Clk=1

R

S

0

D’

0

D’ D

Q’

negative edge-triggered D flip-flop (D-FF)

4-5 gate delays

must respect setup and hold time constraints to successfully

capture input

characteristic equationQ(t+1) = D

holds D' whenclock goes low

holds D whenclock goes low

Edge-Triggered Flip-Flops

• More efficient solution: only 6 gates– sensitive to inputs only near edge of clock signal (not while high)