Lecture 15 Finite State Machine Implementation

ECE C03 Lecture 15 1

Lecture 15Finite State Machine Implementation

Prith Banerjee

ECE C03

Advanced Digital Design

Spring 1998


Outline

• Mapping FSM to random logic• Mapping FSM to ROMS• Mapping FSM to PLAs• Mapping FSM to Programmable Logic Devices

(Xilinx)• READING: Katz 10.1.1, 10.1.2, 10.3, Dewey 9.5


FSM Implementation Strategies

• Discrete Gate Logic

Emphasis so far

• MSI Logic (e.g., Counters)

• Structured Logic (e.g., PLA/PAL, ROM)

• Field Programmable Gate Arrays (FPGAs)

Function can be configured "on the fly" or in the field

Flipflops/Registers plus discrete gates on the same chip


FSM Design with Structured Logic

Block Diagram forSynchronous Mealy Machine

Block Diagram forSynchronous Mealy Machine

ROM-based RealizationROM-based Realization

• Inputs & Current State form the address

• ROM data bits form the Outputs & Next State

Combinational Logic Registers

OutputsOutput Function

Next State Function

Inputs

ROM Registers

OutputsInputsA0

An-1

An

An+m-1 Dk+m-1

D0

Dk-1

Dk

State

State


ROM-Based Implementation

Example: BCD to Excess 3 Serial Converter

BCD Excess 3 Code 0000 0011 0001 0100 0010 0101 0011 0110 0100 0111 0101 1000 0110 1001 0111 1010 1000 1011 1001 1100

Conversion Process

Bits are presented in bit serial fashionstarting with the least significant bit

Single input X, single output Z


BCD to Excess-3 Converter

State Transition Table

Derived State Diagram

Present State S0 S1 S2 S3 S4 S5 S6

Next State OutputX=0 S1 S3 S4 S5 S5 S0 S0

X=1 S2 S4 S4 S5 S6 S0 --

X=0 1 1 0 0 1 0 1

X=1 0 0 1 1 0 1 --

Reset

S00/1 1/0

S10/1

1/0 S2

0/0, 1/1

S30/0, 1/1

S4

1/00/1

S50/0, 1/1

S60/1


ROM-Based ImplementationBCD to Excess 3 Converter

Truth Table/ROM I/Os

Circuit Level Realization74175 = 4 x positive edge triggered D FFs

In ROM-based designs, no need to consider state assignment

QA QA

QB QB

QC QC

QD QD

CLK

CLR1

converter ROMX Q2 Q1 Q0

Z D2 D1 D0

15 14

10 11

7 6

2 3

D CB A

CLK

13 12

10 \Reset

X10

175

1

Z9

5 4

X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Q2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

Q1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

Q0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

D2 0 0 1 1 1 0 0 X 0 1 1 1 1 0 X X

Z 1 1 0 0 1 0 1 X 0 0 1 1 0 1 X X

D1 0 1 0 0 0 0 0 X 1 0 0 0 1 0 X X

D0 1 1 0 1 1 0 0 X 0 0 0 1 0 0 X X

ROM Address ROM Outputs


ROM Based Implementation

BCD to Excess-3 Converter

Timing Behavior for input strings 0 0 0 0 (0) and 1 1 1 0 (7)

0 0 0 0 1 1 0 0 1 1 1 0 0 1 0 1

LSB MSB

LSB LSB

0 0 0 0

1 1 0 0

1 1 1 0

0 1 0 1


PLA Based Design

BCD to Excess 3 Converter

State Assignment with NOVA

S0 = 000S1 = 001S2 = 011S3 = 110S4 = 100S5 = 111S6 = 101

NOVA derived state assignment

9 product termimplementation

0 S0 S1 11 S0 S2 00 S1 S3 11 S1 S4 00 S2 S4 01 S2 S4 10 S3 S5 01 S3 S5 10 S4 S5 11 S4 S6 00 S5 S0 01 S5 S0 10 S6 S0 1

NOVA input file


PLA ImplementationBCD to Excess 3 Converter

Espresso Inputs

Espresso Outputs

.i 4

.o 4

.ilb x q2 q1 q0

.ob d2 d1 d0 z

.p 16 0 000 001 11 000 011 00 001 110 11 001 100 00 011 100 01 011 100 10 110 111 01 110 111 10 100 111 11 100 101 00 111 000 01 111 000 10 101 000 11 101 --- -0 010 --- -1 010 --- -.e

.i 4

.o 4

.ilb x q2 q1 q0

.ob d2 d1 d0 z

.p 90001 010010-0 010001-0 01001-1- 0001-0-1 10000-0- 0001-1-0 1000--10 0100---0 0010.e


PLA ImplementationBCD to Excess 3 Converter

D2 = Q2 • Q0 + Q2 • Q0

D1 = X • Q2 • Q1 • Q0 + X • Q2 • Q0 + X • Q2 • Q0 + Q1 • Q0

D0 = Q0

Z = X• Q1 + X • Q1

175X Q2 Q1 Q0

Z D2 D1 D0

converter PLA10

CLK

10

1

\Reset

CLK

13 12

X D C B A

QD QD

QC QC

QB QB

QA QACLR

9

1

15 14

10 117 6

2 3

Z

5 4


PAL ImplementationBCD to Excess 3 Serial Converter10H8 PAL: 10 inputs, 8 outputs, 2 product terms per OR gate

D1 = D11 + D12

D11 = X • Q2 • Q1 • Q0 + X • Q2 • Q0

D12 = X • Q2 • Q0 + Q1 • Q0

0. Q2 • Q01. Q2 • Q08. X • Q2 • Q1 • Q09. X • Q2 • Q016. X • Q2 • Q017. Q1 • Q024. D1125. D1232. Q033. not used40. X • Q141. X • Q1

X

Q2

Q1

Q0

D11

D12

D2

D11

D12

D1

D0

Z

0 1 2 3 4 5 8 9 12 13 16 17 20 21 24 25 28 29 30 31

0 1

8 9

16 17

24 25

32 33

40 41


PAL ImplementationBCD to Excess 3 Serial Converter

X

Q2

Q1

Q0

D11

D12

D2

D11

D12

D1

D0

Z

0 1 2 3 4 5 8 9 12 13 16 17 20 21 24 25 28 29 30 31

0 1

8 9

16 17

24 25

32 33

40 41

PAL10H8

X Q2 Q1 Q0

D2

D1

D0

Z

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

1211

AND Gate Array


More Advanced PAL ArchitecturesRegistered PAL Architecture

Buffered Inputor product term

Negative LogicFeedbackD2 = Q2 • Q0 + Q2 • Q0

D1 = X • Q2 • Q1 • Q0 + X • Q2 + X • Q0 + Q2 • Q0 + Q1 • Q0

D0 = Q0

Z = X • Q1 + X • Q1

CLK OE

D2 Q2+

Q2+

Q2 Q2 Q0 Q0

X

D Q

Q

Q2 • Q0

Q2 • Q0

Q2 • Q0 + Q2 • Q0

Q2 • Q0 + Q2 • Q0

Q2+


Advanced PAL ArchitecturesProgrammable Output Polarity/XOR PALs

Buried Registers: decouple FF from the output pin

CLK OE

D Q

Q

A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D

A B C D A B A B

C D C D

A B C D

Advantage of XOR PALs: Parity and Arithmetic Operations


Examples of XOR and Registered PALs

1

040

80120

23D Q

Q

2

160200

240280

22D Q

Q

3

320360

400440

21D Q

Q

4

480520

560600

20D Q

Q

5

640680

720760

19D Q

Q

6

800840

880920

18D Q

Q

7

9601000

10401080

17D Q

Q

8

11201160

12001240

16D Q

Q

9

12801320

13601400

15D Q

Q

10

14401480

15201560

14D Q

Q

11 13

0 4 8 12 16 20 24 28 32 36

0 4 8 12 16 20 24 28 32 36

NOTE: FUSE NUMBER = FIRST FUSE NUMBER + INCREMENT

INCREMENT

FIRST FUSE

NUMBER

INCREMENT

Example of XOR PAL

1

11

0 4 8 12 16 20 24 28

INCREMENT

0

19

2

326496

128160192224

256

18

3

288320352384416448480

D Q

Q

512

17

4

544576608640672704736

D Q

Q

768

16

5

800832864896928960992

D Q

Q

1024

15

6

1056108811201152118412161248

D Q

Q

1280

14

7

1312134413761408144014721504

D Q

Q

1536

13

8

1568160016321664169617281760

D Q

Q

1792

12

9

1824185618881920195219842016

FIRST FUSE NUMBERS

Example of Registered PAL


FSM Design With CountersSynchronous Counters: CLR, LD, CNT

Four kinds of transitions for each state:

(1) to State 0 (CLR)

(2) to next state in sequence (CNT)

(3) to arbitrary next state (LD)

(4) loop in current state

Careful state assignment is needed to reflect basic sequencingof the counter

Careful state assignment is needed to reflect basic sequencingof the counter

0

n

n+1 m

no signals

assertedCLR

CNT LD


Implementation StrategiesFSM Design with Counters

Excess 3 Converter Revisited

Note the sequential natureof the state assignments

Reset

0/10

1/0

1

0/11/0

40/0, 1/1

20/0, 1/1

0/1

5

1/0

0/0, 1/1

3 6

0/1


Implementation StrategiesFSM Design with Counters

Excess 3 Converter

CLR signal dominates LD which dominates Count

Inputs/Current State

Next State Outputs

X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Q2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

Q1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

Q0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Q2+ 0 0 0 0 1 0 0 X 1 1 0 0 1 1 X X

Q1+ 0 1 1 0 0 1 0 X 0 0 1 0 0 1 X X

Q0+ 1 0 1 0 1 1 0 X 0 1 1 0 1 0 X X

Z 1 1 0 0 1 0 1 X 0 0 1 1 0 1 X X

CLR 1 1 1 0 1 1 0 X 1 1 1 0 1 1 X X

LD 1 1 1 X 1 0 X X 0 0 1 X 1 1 X X

EN 1 1 1 X 1 X X X X X 1 X 1 1 X X

C X X X X X 0 X X 1 1 X X X X X X

B X X X X X 1 X X 0 0 X X X X X X

A X X X X X 0 X X 0 1 X X X X X X


Implementation FSM With CountersExcess 3 Converter

Espresso Input File

Espresso Output File

.i 5

.o 7

.ilb res x q2 q1 q0

.ob z clr ld en c b a

.p 171---- -0-----00000 1111---00001 1111---00010 0111---00011 00-----00100 0111---00101 110-01100110 10-----00111 -------01000 010-10001001 010-10101010 1111---01011 10-----01100 1111---01101 0111---01110 -------01111 -------.e

.i 5

.o 7

.ilb res x q2 q1 q0

.ob z clr ld en c b a

.p 100-001 0101101-0-01 1000000-11-0 10000000-0-0 0101100-000- 1010000-0--0 00100000-10- 0101011--11- 1000000-11-- 0010000-1-1- 1010000.e


Implementing FSM with CountersExcess 3 Converter Schematic

Synchronous Output Register

1 01 0

excess 3 PLA

Reset X Q2 Q1 Q0

Z \CLR

\LD EN

C B A

CLK

X

7 10

2

9

1

P T

CLKD C B A

LOAD

CLR

RCO

QD QC QB QA

15

D Q

C Q

Z163

11121314

6543


FSM Design with FPGAs

Programmable Logic Devices = PLD

Field Programmable Gate Arrays = FPGAs

• Altera MAX Family

• Actel Programmable Gate Array

• Xilinx Logical Cell Array

PALs, PLAs = 10 - 100 Gate Equivalents

100 - 1000(s) of Gate Equivalents!


Xilinx Logic Cell Arrays

CMOS Static RAM Technology: programmable on the fly!

All personality elements connected into serial shift register

Shift in string of 1's and 0's on power up

General Chip Architecture: • Logic Blocks (CLBs) • IO Blocks (IOBs) • Wiring Channels

IOB IOB IOB IOB

CLB CLB

CLB CLB

IOB

IOB

IOB

IOB

Wiring Channels


Xilinx LCA Architecture

Inputs: Tri-state enable bit to output input, output clocks

Outputs: input bit

Internal FFs for input & output paths

Fast/Slow outputs 5 ns vs. 30 ns rise

Pull-up used with unused IOBs

D Q

OUT INV

TS INV

OUTPUT SOURCE

SLEW RATE

PASSIVE PULLUP

MUX

R

DQ

R

Vcc

PAD

Output Buffer

TTL or CMOS Input Buffer

Global ResetClocks

Enable Output

Out

Direct In

Registered In

Program Controlled Options


Xilinx LCA Architecture

Configurable Logic Block: CLB

2 FFs

Any function of 5 Variables

Global Reset

Clock, Clock Enb

Independent DIN

Combinational Function Generator

D RDQ

CEMux

D RDQ

CE

Mux

Mux

Mux

Mux

A B C D E

Q1

Q2

Reset

DIN

Clock

Clock Enable

F

G

X

Y


Xilinx CLB Function Generator

CLB Function Generator

Any function of 5 variables

Two Independent Functionsof 4 variables each

Function of 5

Variables

F

G

Mux

Mux

AB

C

DE

Q1

Q2

Function of 4

VariablesF

Mux

Mux

AB

C

DE

Q1

Q2

Mux

Function of 4

VariablesG

Mux

Mux

AB

C

DE

Q1

Q2

Mux


Xilinx CLB Function Generator

Certain LimitedFunctions of 6 Variables

Function of 4

VariablesE

Mux

Mux

AB

C

D

Q1

Q2

Function of 4

Variables

Mux

Mux

AB

C

D

Q1

Q2

Mux

F

G


Xilinx Interconnect Architecture

Interconnect

Direct Connections

Global Long Line

Horizontal/Vertical Long Lines

Switching Matrix Connections

X

YCLB3

A

D

DIBCKE R

CE

X

YCLB1

A

D

DIBCKE R

CEX

YCLB0

A

D

DIBCKE R

CE

Direct Connections

Horizontal Long Line

Vertical Long Lines

Global Long Line

Switching Matrix

Horizontal Long Line

X

YCLB2

A

D

DIBCKE R

CE


Implementing FSM with Xilinx LCA

Implementing the BCD to Excess 3 FSM

Q2+ = Q2 • Q0 + Q2 • Q0

Q1+ = X • Q2 • Q1 • Q0 + X • Q2 • Q0 + X • Q2 • Q0 + Q1 • Q0

Q0+ = Q0

Z = Z • Q1 + X • Q1

No function more complex than 4 variables 4 FFs implies 2 CLBs

Synchronous Mealy Machine

Global Reset to be used

Place Q2+, Q0+ in once CLB Q1, Z in second CLB maximize use of direct & general purpose interconnections


Implementing FSM with Xilinx LCA

Implementing the BCD to Excess 3 FSM

FG

FG

ACEDI

B

C

K

ED RES

X

Y

Q2

Q0

Q2Q0

Q0

FG

FG

ACEDI

B

C

K

ED RES

X

Y

Q1

Z

Q1Q0

Q1X

Q2X

X

CE

Clk Clk

CLB1 CLB2


Summary

• Mapping FSM to random logic• Mapping FSM to ROMS• Mapping FSM to PLAs• Mapping FSM to Programmable Logic Devices

(Xilinx)• NEXT LECTURE: VHDL Language• READING: Dewey 11.2, 11.3, 11.4, 11.5, 11.6,

12.2, 12.2

Lecture 15 Finite State Machine Implementation

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