Introduction to HPC resources for BCB 660 Nirav Merchant [email protected] .
1 Tutorial: Lab 4 Nirav Dave Computer Science & Artificial Intelligence Lab Massachusetts Institute...
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1
Tutorial: Lab 4
Nirav Dave Computer Science & Artificial Intelligence LabMassachusetts Institute of Technology
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June 3, 2008 2
Quick Notes on the Class
Lab Grades: You guys are doing well Almost perfect scores on Lab 1, with a few
exceptions
Common Problems: Not all files are checked in Forgot to check in the written answers
Grading Labs Wanted to get test scripts out to you before due date Our fault. Trying to rectify (need your names &
emails)
If you haven’t sent me your email, do so.
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June 3, 2008 3
Lab 4 – The Processor Lab
Good News! Unlike previous labs, we’ve done this
lab many times before Hopefully a lot less pain
Lab Goals: Explore design refinement Hands on experience on tuning
scheduling
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June 3, 2008 4
The Processor:
SMIPSv2 ISA (simplified MIPS) 35 Instructions
add/sub/xor bz/blt lw/sw Special ops (toHost/fromHost)
Helps for testing
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June 3, 2008 5
What you’ve been given
pc
epochPCGe
nPCGe
nExecExec WBWB
ICache DCache
RFileOnly one instruction at a time
PCGenExecWBPCGen
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June 3, 2008 6
The Multi-stage Design
3 Rules (one for each stage)1 instruction active at a time2-3 stages / instruction Do WB part in Exec if we aren’t doing
a memop
Little inter-stage bufferingMulti-cycle memory interface as discussed in class
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June 3, 2008 7
First Task: Pipelined CPU
pc
epochPCGe
nPCGe
nExecExec WBWB
ICache DCache
RFileNew Instruction can start before the first finishes
Need more buffering
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June 3, 2008 8
High-Level Steps
Add inter-stage bufferingIsolate data usage to single stagesAdd program counter speculationMake executing each stage correct Stalling logic (as in lectures)
Get correct schedule (fully pipelined) Select correct state elements (correct
bypassing)
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June 3, 2008 9
Branch Prediction
Pipeline has simple speculation
rule pcGen (True);
pc <= pc + 4;
otherActions;
endrule
Simplest prediction:Always not-taken
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June 3, 2008 10
First Task: Pipelined CPU
pc
epochPCGe
nPCGe
nExecExec WBWB
ICache DCache
RFilepred
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June 3, 2008 11
Branch Predictioninterface BranchPredictor; method Addr getNextPC(Addr pc); method Action update (Addr pc, Addr correct_next_pc);endinterfacerule pcGen (True);
pc <= pred.getNextPC(pc);
otherActions;
endrule
rule execute …
if (nextPC != correctPC) pred.update(curPc, nextPC);
case (instr) matches …
BzTaken: if (mispredicted) …
endrule
Update predictions
Make prediction
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June 3, 2008 12
End Notes
This Lab is “easy”
Do it early anyways