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Metal-Oxide-Semicondutor FET(MOSFET)

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Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3 m, W = 0.2 to 100 m, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.

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Figure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate.

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Device structure of MOSFET (n-type)

p-type SemiconductorSubstrate (Body)

Body(B)

n+ n+

Oxide(SiO2)

Source(S)Gate(G)

Drain(D)

Metal

For normal operation, it is needed to create a conducting channel between Source and Drain

Channel area

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An n channel can be induced at the top of the substrate beneath the gate by applying a positive voltage to the gate

The channel is an inversion layer

The value of VGS at which a sufficient number of mobile electrons accumulate to form a conducting channel is called the threshold voltage (Vt)

Creating a channel for current flow

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L = 0.1 to 3 m

W = 0.2 to 100 m

Tox= 2 to 50 nm

Device structure of MOSFET (n-type)

Cross-section view

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Figure 4.3 An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is determined by vGS. Specifically, the channel conductance is proportional to vGS – Vt’ and thus iD is proportional to (vGS – Vt) vDS. Note that the depletion region is not shown (for simplicity).

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Figure 4.5 Operation of the enhancement NMOS transistor as vDS is increased. The induced channel acquires a tapered shape, and its resistance increases as vDS is increased. Here, vGS is kept constant at a value > Vt.

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Figure 4.4 The iD–vDS characteristics of the MOSFET in Fig. 4.3 when the voltage applied between drain and source, vDS, is kept small. The device operates as a linear resistor whose value is controlled by vGS.

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Figure 4.6 The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS > Vt.

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Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well. Not shown are the connections made to the p-type body and to the n well; the latter functions as the body terminal for the p-channel device.

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The PMOS transistor is formed in n well.

Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well.

CMOS is the most widely used of all the analog and digital IC circuits.

Complementary MOS or CMOS

Copyright 2004 by Oxford University Press, Inc.

Figure: n-Channel JFET.

The Junction Field Effect Transistor (JFET)

Copyright 2004 by Oxford University Press, Inc.

Figure: n-Channel JFET and Biasing Circuit.

Biasing the JFET

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Figure: The nonconductive depletion region becomes broader with increased reverse bias. (Note: The two gate regions of each FET are connected to each other.)

Operation of JFET at Various Gate Bias Potentials

Copyright 2004 by Oxford University Press, Inc.

P P +

-

DC Voltage Source

+

-+

-

N

N

Operation of a JFET

Gate

Drain

Source

Copyright 2004 by Oxford University Press, Inc.

Figure: Circuit for drain characteristics of the n-channel JFET and its Drain characteristics.

Characteristics of n-JFET

Copyright 2004 by Oxford University Press, Inc.

Figure: n-Channel FET for vGS = 0.

n-Channel JFET

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N-ch

ann

elN

-chan

nel

Depletion Depletion layerlayer

GG

DD

SS

GG

DD

SSnn-type -type

SemiconductorSemiconductor

Junction FET

PP++ PP++

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UUGS GS = 0= 0 UUGSGS < 0 < 0 UUGS GS = = UUGS(off)GS(off)

DD

SS

PP++

Physical operation under vDS=0

GGPP++

DD

SS

PP++

GGPP++

DD

SS

GGPP++ PP++

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The effect of UDS on ID for UGS(off) <UGS < 0