1 COMP541 Interrupts, DMA, Serial I/O Montek Singh Nov 19, 2014.
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Transcript of 1 COMP541 Interrupts, DMA, Serial I/O Montek Singh Nov 19, 2014.
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COMP541
Interrupts, DMA, Serial I/O
Montek Singh
Nov 19, 2014
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Interrupts Two main kinds Internal
Error when executing an instructionFloating point exceptionVirtual memory page faultTrying to access protected memory Invalid opcode!
System call requested by softwareTo request OS services
External I/O
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Internal More complicated because two possible
actionsmay abort instruction
access to protected memory not allowedor, OS corrects the situation and restarts instruction
e.g., virtual memory page fault
Question:What happens for arithmetic overflow/divide-by-0?
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When Interrupt Occurs Interrupt enable register
Sometimes levels of interrupts individually enabled/disabled
PC is changed to new locationOne or more interrupt locations stored
“vectored interrupts”Or a fixed location
example: MIPS (e.g., 0xC000 0000)
Old PC saved to register or stackMany machines have stack pointer
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Registers Sometimes registers saved by hardware
Some machines have one or more sets of registers Often: software must save registers
Push them onto stack Return from interrupt
Some CPUs provide a special instruction to return from interrupt“rfi” or “iret”
Others use the standard procedure return instruction jr, ret, etc.
Restore registers before returning
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Cause of Interrupt Need way to determine what caused interrupt
Note it can be more than one thing Vectored Interrupts
Different types cause branches to different locationsSometimes prioritized
Register to store cause“Cause” register
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Supervisory Mode Modern computers have user mode and one or
more “supervisory modes” User mode restricted
Can’t write to many system registers, such as interrupt enable
Can’t write to some parts of memoryUsually I/O restricted
Interrupts cause switch to supervisory mode In this mode, software has access to several
privileged parts of the system e.g.: kernel memory, IE register, etc.
Question: Which interrupts?
Some Interrupt Hardware An example
implementationInterrupts ORedResponse if IE and at
end of instructionAck interruptVector address to PC
new PC calculated using the interrupt number
e.g., IntNum * a + b
Save current PC on stack to return
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Return from interrupt Very similar to return from procedure Some additional actions
PSR holds IE bitRestoring PSR turns interrupts on
Exception (from Patterson Hennessey, multicycle MIPS) MIPS has a simpler impl.
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Just two causes
PC – 4 stored
Branch to fixed addr
Undefined instruction and arithmetic overflow
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Restarting Instruction? Imagine the interrupt (exception) was a page
faultNeed to get the page, and then rerun the instructionHence: subtract 4 from PCPlus4, so this instruction is
redone
Keeping instructions simple/short helps out!Otherwise may need to save some intermediate state
Imagine block-move instruction such as the Pentium MOVS– moves/copies an entire string (of variable length) in a single
instruction!
Types of I/O
Programmed I/ODirect Memory Access (DMA)
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Direct Memory Access (DMA) Programmed I/O is when CPU reads/writes
every wordSpecific instructions included for I/O, e.g.:
in 0xff00out 0xffe0
Problem: overhead is high; nothing else getting done on CPU
Especially for mass-storage devices like disk
DMA: Let device controller read/write mem directlyCPU goes about its usual business of executing other
instructionsdelegates the reading/writing to DMA controllertypically cannot access memory while DMA is going on!
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DMA Protocol DMA protocol
DMA device takes over main busBecomes bus masterAsserts addressesBasically interfaces to memory or memory controller
How? DMA device requests bus (assert BR) CPU grants request (assert BG) CPU takes its signals to Hi-Z
now DMA can use its signals to connect with memoryno conflict with CPU’s signals (they are floating)
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Transfer Modes Several types of transfer modes
Continuous: DMA controller transfers all data (say a disk sector) at onceAs many memory cycles as data
Burst: DMA controller cycle steals, takes a cycle at end of every CPU instruction
Note: today’s processors are more sophisticated there is a memory controller (“Northbridge”)sits in-between CPU and memoryWhy? Memories are more complex, caches, etc.
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End of DMA Controller needs to inform CPU
De-assert BRThen CPU lowers BG and proceeds
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DMA Controller Needs typical I/O signals
Interrupt requestStatus of device
Also needs controls for DMA transferMemory addressWord count
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Block Diagram
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Typical Driver Interface Software drivers
Set the memory addressSet word countAssert “GO” (usually bit in control word)DMA controller starts copying …… and requests interrupt when transfer complete
Trends in Communications Older bus standards, such as ISA and PCI, were
parallel (conventional “bus”) Newer (PCI Express) use serial channels
(lanes)So slots for slower devices can be x1Slots for devices such as GPUs can be x16 (max x32
in spec)
16 lane PCI-E (below)1 lane (right)
Disks Change from ATA/IDE to SATA
IDE had 16 data channelsSATA has 2 twisted pair (xmit and recv)
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RS-232/UART Called “Asynchronous”
But both sides have precise clocksAgree on speedReceiver syncs during start bit
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USB One master
The PC Idea was to have thin
cables and plug and play
Specs include hardware and softwareWe only cover
hardware
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USB – Packet serial I/O Four wires total +5v and GND Two signal wires
Twisted pairDifferential signalingDifferential 1 is D+ > 2.8v and D- < 0.3vDifferential 0 is oppositeAlso a single-ended zero when D+ & D- low (end of
packet, reset, disconnect)
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Speed Three speeds
High is 480 Mb/s (USB 2.0) Full is 12 Mb/s (USB 1.1) Low is 1.5 Mb/s (USB 1.0) New Super Speed, 5Gb/s!! (USB 3.0)
High speed starts as full, then handshakes and transitions
High and low speeds interpret zeros and ones inverted
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Coding NRZI
Non-Return to Zero InvertedTransition if sending 0, none if sending 1
Bit stuffingSince a string of 1s causes no transitions,
synchronization may be lostA zero is stuffed in after six consecutive ones
Sync fieldEach packet starts with a sync8 bits: 00000001
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Packets Won’t go into
details
Summary Many types of I/O
memory-mapped is most commondifferent devices given different address ranges
many different device protocolsPS/2: keyboard, miceRS-232: serial portsUSB: most common todayalso Firewire, Thunderbolt, … ethernet
also monitors, displayswe did VGA (other higher resolutions also possible)DVI is most common today
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