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COMP541COMP541
Combinational Logic - 4Combinational Logic - 4
Montek SinghMontek Singh
Jan 30, 2012Jan 30, 2012
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Today’s TopicsToday’s Topics Combinational Building BlocksCombinational Building Blocks
MultiplexersMultiplexers DecodersDecoders EncodersEncoders
Delays and TimingDelays and Timing
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Multiplexer (Mux)Multiplexer (Mux)
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Selects one of out of N Selects one of out of N inputsinputs a control input (“select” a control input (“select”
signal) determines which signal) determines which input is choseninput is chosen
# bits in select = # bits in select = ceil(logceil(log22N)N)
Example: 2:1 MuxExample: 2:1 Mux 2 inputs2 inputs 1 output1 output 1-bit select signal1-bit select signal
Y0 00 11 01 1
0101
0000
0 00 11 01 1
1111
0011
0
1
S
D0Y
D1
D1 D0S Y01 D1
D0
S
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Multiplexer ImplementationsMultiplexer Implementations Logic gatesLogic gates
Sum-of-products formSum-of-products form
Tristate buffersTristate buffers For an N-input mux, For an N-input mux,
use N tristate buffersuse N tristate buffers Turn on exactly one Turn on exactly one
buffer to propagate buffer to propagate the appropriate inputthe appropriate inputall others are in all others are in
floating (Hi-Z) statefloating (Hi-Z) state
Y
D0
S
D1
D1
Y
D0
S
Y = D0S + D1S
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Multiplexer with Hi-ZMultiplexer with Hi-Z
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Normal operation is blue areaNormal operation is blue area
Smoke
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Combinational Logic using Combinational Logic using MultiplexersMultiplexers Implement a truth table Implement a truth table
using a muxusing a mux use a mux with as many use a mux with as many
input lines are rows in the input lines are rows in the tabletable
YY values are fed into the values are fed into the mux’s data inputsmux’s data inputs
ABAB values become the values become the mux’s select inputsmux’s select inputs
A B Y0 0 00 1 01 0 01 1 1
Y = AB
00
Y0110
11
A B
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Verilog for MultiplexerVerilog for Multiplexer
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Just a conditional statement:Just a conditional statement:module mux(input d0, d1, module mux(input d0, d1,
input s,input s,
output y);output y);
assign y = s ? d1 : d0; assign y = s ? d1 : d0;
endmoduleendmodule
Easily extends to multi-bit data inputs:Easily extends to multi-bit data inputs:module mux4bit(input [3:0] d0, d1, module mux4bit(input [3:0] d0, d1,
input s,input s,
output [3:0] y);output [3:0] y);
assign y = s ? d1 : d0; assign y = s ? d1 : d0;
endmoduleendmodule
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Verilog for MultiplexerVerilog for Multiplexer
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Also extends to N-way multiplexers:Also extends to N-way multiplexers:module mux4way4bit(module mux4way4bit(
input [3:0] d0, d1, d2, d3input [3:0] d0, d1, d2, d3
input [1:0] s,input [1:0] s,
output [3:0] y);output [3:0] y);
assign y = s[1] ? (S[0]? d3 : d2)assign y = s[1] ? (S[0]? d3 : d2)
: (S[0]? d1 : d0);: (S[0]? d1 : d0);
endmoduleendmodule
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DecodersDecoders N inputs, 2N inputs, 2NN outputs outputs ““One-hotOne-hot”” outputs outputs
only one output HIGH only one output HIGH timetime
2:4Decoder
A1
A0
Y3Y2Y1Y000
011011
0 00 11 01 1
0001
Y3 Y2 Y1 Y0A0A1
0010
0100
1000
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Decoder ImplementationDecoder Implementation
Y3
Y2
Y1
Y0
A0A1
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Aside: EnableAside: Enable Enable is a common input to logic functionsEnable is a common input to logic functions See it in memories and today’s logic blocksSee it in memories and today’s logic blocks
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2-to-4 Decoder with Enable2-to-4 Decoder with Enable
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VerilogVerilog
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DecodersDecoders How about a…How about a…
1-to-2 decoder?1-to-2 decoder? 3-to-8 decoder?3-to-8 decoder? (N)-to-2(N)-to-2(N)(N) decoder? decoder? (N+1)-to-2(N+1)-to-2(N+1)(N+1) decoder? decoder?
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3-to-8 Decoder: Truth Table3-to-8 Decoder: Truth Table
Notice they are mintermsNotice they are minterms
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3-to-8 Decoder: Schematic3-to-8 Decoder: Schematic
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3-to-8 Decoder: Multilevel Circuit3-to-8 Decoder: Multilevel Circuit
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3-to-8 Decoder: 3-to-8 Decoder: “Enable” used for “Enable” used for expansionexpansion
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Multi-Level 6-to-64 DecoderMulti-Level 6-to-64 Decoder
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Uses for DecodersUses for Decoders Binary number might serve to select some Binary number might serve to select some
operationoperation Number might encode a Number might encode a CPU InstructionCPU Instruction (op codes) (op codes)
Decoder lines might select add, or subtract, or multiply, Decoder lines might select add, or subtract, or multiply, etc.etc.
Number might encode a Number might encode a Memory AddressMemory AddressTo read or write a particular location in memoryTo read or write a particular location in memory
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Logic using DecodersLogic using Decoders OR the ON-set OR the ON-set
mintermsminterms2:4
Decoder
AB
00011011
Y = AB + AB
Y
ABABABAB
Minterm
= A B
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Demultiplexer (demux)Demultiplexer (demux) Dual of multiplexerDual of multiplexer
One input, multiple outputs (destinations)One input, multiple outputs (destinations) Select signal Select signal routesroutes input to one of the outputs input to one of the outputs
n-bit select implies 2n-bit select implies 2nn outputs outputs e.g., 4-way demux uses a 2-bit selecte.g., 4-way demux uses a 2-bit select
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Demux vs. DecoderDemux vs. Decoder SimilaritiesSimilarities
decoder decoder produces a “1” produces a “1” on one of the 2on one of the 2NN outputs outputs… “… “0” elsewhere0” elsewhere
demultiplexer demultiplexer transmits datatransmits data to one of the 2 to one of the 2NN outputs outputs… “… “0” elsewhere0” elsewhere
Possible to make one from the otherPossible to make one from the other How?How?
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EncoderEncoder Encoder is the opposite of decoderEncoder is the opposite of decoder
22NN inputs (or fewer) inputs (or fewer) N outputsN outputs
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Encoder: ImplementationEncoder: Implementation Inputs are already minterms!Inputs are already minterms!
Simply OR them together appropriatelySimply OR them together appropriately e.g.: Ae.g.: A00 = D = D11 + D + D33 + D + D55 + D + D77
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Encoder Implementation: Encoder Implementation: ProblemProblem Requirement:Requirement:
Only one of the D inputs can be highOnly one of the D inputs can be high What if, say, D3 and D6 are both high?What if, say, D3 and D6 are both high?
Simple OR circuit will set A to 7Simple OR circuit will set A to 7
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Solution: Priority EncoderSolution: Priority Encoder Chooses one with highest priorityChooses one with highest priority
Largest number, usuallyLargest number, usually
Note “don’t cares”Note “don’t cares”
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Priority EncoderPriority Encoder What if all inputs are zero?What if all inputs are zero?
Need another output: “Valid”Need another output: “Valid”
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Priority Encoder ImplementationPriority Encoder Implementation Valid is simply the OR of all the data inputsValid is simply the OR of all the data inputs
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Code Converters Code Converters General ConvertersGeneral Converters
convert one code to anotherconvert one code to another examples?examples?
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Example: Seven-Segment Example: Seven-Segment DecoderDecoder 7-segment display7-segment display
convert single hex digit …convert single hex digit … … … to a display character code)to a display character code)
Will be first lab using the hardware kit (Feb 10)Will be first lab using the hardware kit (Feb 10)
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TimingTiming What is Delay?What is Delay?
Time from input change to Time from input change to output changeoutput changeTransient responseTransient response
e.g., rising edge to rising e.g., rising edge to rising edgeedge
Usually measured from 50% Usually measured from 50% pointpoint A
Y
Time
delay
A Y
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Types of DelaysTypes of Delays Transport delay = “pure” delayTransport delay = “pure” delay
Whatever goes in …Whatever goes in … … … comes out after a specified amount of timecomes out after a specified amount of time
Inertial delayInertial delay Inputs have an effect only if they persist for a Inputs have an effect only if they persist for a
specified amount of timespecified amount of timeNo effect if input changes and changes back in too short a No effect if input changes and changes back in too short a
time (can’t overcome inertia)time (can’t overcome inertia)can filter out glitchescan filter out glitches
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Effect of Transport Delay (blue)Effect of Transport Delay (blue) Delay just shifts signal in timeDelay just shifts signal in time
focus on the blue bars; ignore the black onesfocus on the blue bars; ignore the black ones
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Effect of Inertial DelayEffect of Inertial Delay
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Blue – Propagation delay time Black – Rejection time (filter out)Blue – Propagation delay time Black – Rejection time (filter out)
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Propagation & Contamination Propagation & Contamination DelayDelay Propagation delay: Propagation delay: ttpdpd
maxmax delay from input to delay from input to outputoutput
Contamination delay: Contamination delay: ttcdcdminmin delay from input to delay from input to
outputoutput
A
Y
Time
A Y
tpd
tcd
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Propagation & Contamination Propagation & Contamination DelayDelay Delay is caused byDelay is caused by
Capacitance and resistance in a circuitCapacitance and resistance in a circuitMore gates More gates driven,driven, longer delay longer delayLonger wires at output, longer delayLonger wires at output, longer delay
Speed of light is the ultimate limitationSpeed of light is the ultimate limitation
Reasons why Reasons why ttpdpd and and ttcdcd may be vary: may be vary: Different rising and falling delaysDifferent rising and falling delays
What is typically reported? Greater of the twoWhat is typically reported? Greater of the two Multiple inputs and outputs, some faster than othersMultiple inputs and outputs, some faster than others Circuits slow down when hot and speed up when coldCircuits slow down when hot and speed up when cold
So, both maximum and typical given So, both maximum and typical given
Specs provided in data sheetsSpecs provided in data sheets
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Propagation & Contamination Propagation & Contamination DelayDelay
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Critical (Long) Path: tpd = 2tpd_AND + tpd_OR
Short Path: tcd = tcd_AND
Critical and Short PathsCritical and Short Paths
AB
C
D Y
Critical Path
Short Path
n1
n2
Critical (Long) and Short Paths
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GlitchesGlitches What is a Glitch?What is a Glitch?
a non-monotonic change in a signala non-monotonic change in a signal e.g., a single input change can cause multiple e.g., a single input change can cause multiple
changes on the same outputchanges on the same output a multi-input transition can also cause glitchesa multi-input transition can also cause glitches
Are glitches a problem?Are glitches a problem? Not really in synchronous designNot really in synchronous design
Clock time period must be long enough for all glitches to Clock time period must be long enough for all glitches to subsidesubside
Yes, in asynchronous designYes, in asynchronous designAbsence of clock means there should ideally be no Absence of clock means there should ideally be no
spurious signal transitions, esp. in control signalsspurious signal transitions, esp. in control signals It is important to recognize a glitch when you see one It is important to recognize a glitch when you see one
in simulations or on an oscilloscopein simulations or on an oscilloscope Often cannot get rid of all glitchesOften cannot get rid of all glitches
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Glitch Example: Self-StudyGlitch Example: Self-Study What happens when:What happens when:
A = 0, C = 1, andA = 0, C = 1, and B goes from 1 to 0?B goes from 1 to 0?
Logically, nothingLogically, nothing Because although 2nd Because although 2nd
term goes to falseterm goes to false 1st term now is true1st term now is true
But, output may glitchBut, output may glitch if one input to OR goes if one input to OR goes
low before the other input low before the other input goes highgoes high
AB
C
Y
Y = AB + BC
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Glitch Example: Self-Study (cont.)Glitch Example: Self-Study (cont.)
A = 0B = 1 0
C = 1
Y = 1 0 1
Short Path
Critical Path
B
Y
Time
1 0
0 1
glitch
n1
n2
n2
n1
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Glitch Example: Self-Study (cont.)Glitch Example: Self-Study (cont.) Fixing the glitch: Add Fixing the glitch: Add
redundant logic termredundant logic term
Y = AB + BC + AC
B = 1 0Y = 1
A = 0
C = 1
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